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Begin with the access EL. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 +-- target/arm/mmuidx-internal.h | 29 +++++++++++++++++++++++++ target/arm/helper.c | 27 ------------------------ target/arm/mmuidx.c | 41 ++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 7 +++++- 5 files changed, 77 insertions(+), 30 deletions(-) create mode 100644 target/arm/mmuidx-internal.h create mode 100644 target/arm/mmuidx.c diff --git a/target/arm/internals.h b/target/arm/internals.h index 889669c67c..4e0c057a8c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -34,6 +34,7 @@ #include "system/memory.h" #include "syndrome.h" #include "cpu-features.h" +#include "mmuidx-internal.h" =20 /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -984,8 +985,6 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_id= x) return mmu_idx | ARM_MMU_IDX_A; } =20 -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); - /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); =20 diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h new file mode 100644 index 0000000000..29bba4ecb5 --- /dev/null +++ b/target/arm/mmuidx-internal.h @@ -0,0 +1,29 @@ +/* + * QEMU Arm software mmu index internal definitions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_ARM_MMUIDX_INTERNAL_H +#define TARGET_ARM_MMUIDX_INTERNAL_H + +#include "mmuidx.h" +#include "tcg/debug-assert.h" +#include "hw/registerfields.h" + + +FIELD(MMUIDXINFO, EL, 0, 2) +FIELD(MMUIDXINFO, ELVALID, 2, 1) + +extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; + +#define arm_mmuidx_is_valid(x) ((unsigned)(x) < ARRAY_SIZE(arm_mmuidx_tab= le)) + +/* Return the exception level associated with this mmu index. */ +static inline int arm_mmu_idx_to_el(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + tcg_debug_assert(FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, ELVALID= )); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, EL); +} + +#endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index fc95010727..eaa6766a36 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9789,33 +9789,6 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 -/* Return the exception level we're running at if this is our mmu_idx */ -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) -{ - if (mmu_idx & ARM_MMU_IDX_M) { - return mmu_idx & ARM_MMU_IDX_M_PRIV; - } - - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E30_0: - return 0; - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - return 1; - case ARMMMUIdx_E2: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - return 2; - case ARMMMUIdx_E3: - case ARMMMUIdx_E30_3_PAN: - return 3; - default: - g_assert_not_reached(); - } -} - #ifndef CONFIG_TCG ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c new file mode 100644 index 0000000000..309b1d68df --- /dev/null +++ b/target/arm/mmuidx.c @@ -0,0 +1,41 @@ +/* + * QEMU Arm software mmu index definitions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "mmuidx-internal.h" + + +#define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) + +const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { + /* + * A-profile. + */ + [ARMMMUIdx_E10_0] =3D EL(0), + [ARMMMUIdx_E10_1] =3D EL(1), + [ARMMMUIdx_E10_1_PAN] =3D EL(1), + + [ARMMMUIdx_E20_0] =3D EL(0), + [ARMMMUIdx_E20_2] =3D EL(2), + [ARMMMUIdx_E20_2_PAN] =3D EL(2), + + [ARMMMUIdx_E2] =3D EL(2), + + [ARMMMUIdx_E3] =3D EL(3), + [ARMMMUIdx_E30_0] =3D EL(0), + [ARMMMUIdx_E30_3_PAN] =3D EL(3), + + /* + * M-profile. + */ + [ARMMMUIdx_MUser] =3D EL(0), + [ARMMMUIdx_MPriv] =3D EL(1), + [ARMMMUIdx_MUserNegPri] =3D EL(0), + [ARMMMUIdx_MPrivNegPri] =3D EL(1), + [ARMMMUIdx_MSUser] =3D EL(0), + [ARMMMUIdx_MSPriv] =3D EL(1), + [ARMMMUIdx_MSUserNegPri] =3D EL(0), + [ARMMMUIdx_MSPrivNegPri] =3D EL(1), +}; diff --git a/target/arm/meson.build b/target/arm/meson.build index 07d9271aa4..91630a1f72 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -6,7 +6,12 @@ arm_ss.add(files( =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', - 'gdbstub64.c')) + 'gdbstub64.c' +)) + +arm_common_ss.add(files( + 'mmuidx.c', +)) =20 arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() --=20 2.43.0