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[122.150.204.48]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4d96829a66sm2435905a12.6.2025.08.29.22.42.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:43:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756532580; x=1757137380; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7+ER0bRwaWJSVZXuKMTaNBSXf4hbZ3aeU4lFfN33xP8=; b=RlotFGoVZ4cQE/edn06eiZXmRz+bmqX8PVcDueWCdLr8b6fPTFEOuSra1tKx9vK/25 fClw8YlT5raUEAIVeN4HblZkus5xYpqcax+591Xupf3Tlza+0frVaQaXyItFmCNbzX1P zKrHBGeY8tkRyrRv8YOQGZkrokyW/AnMgXPpQNYJEGBrjDp7DwjjQoeWnfgk5hpwJfwq xYCL/JKlqNaf+elh3cLf3dxAjeW4sqYE3hhOEwBUq+XUr6SSdzsKFNUa68PsPBU9lUkO SL/e+QFHZLE65GoRK8RHugEqr2T62cH20Ebvrkgq7FSF+U8yASiVvlQIfBomSZmjAdCU APPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756532580; x=1757137380; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7+ER0bRwaWJSVZXuKMTaNBSXf4hbZ3aeU4lFfN33xP8=; b=QB2w+0DKjWRKt/qvj2SyH5/+GuvVwe+TVI5994aDwLxe6DvnE/y2/EAV9tl41Ngdrv tkgcu9/4t5rwBoaXvkNvJX6W/vGvNBYfxgDP6L0nLsGtrCfOM3oiAEiTBJPKV+18dtoP JAJg5TdBIY6Dn1C3jZZFs0kHWM9VAoXe2/OZg/4/IAaEAILR0at73o43TRqaJ6N9ZQH5 wwHxlzS1iQOdGo1c+mzRybBM2SiIC6+9iBbH62DfR0xA/tGGGswNSjWY2yXWyNp0yagU OwoG2hG9/zgSNGOwQJKNErYIhTO8MIqivS7sH2KtTdnDKY67RwjTLw//kjh6xEEi2dMO MP1Q== X-Gm-Message-State: AOJu0YxaN/XTgMs/D1V85DEW9spU+yyXByAklgUcN5tixVJi8DgcHF7D fgG2DCjxzDVEhCAKC3FUAZ/jAJQ/iBnfUnIwEjvjVDZeMnKPenkPkyAcIeZxp2Uy5I76u6BbqJb tq3Diq00= X-Gm-Gg: ASbGnct5bkbMAb/c2m1ji+XPJXCNLExT+J6OS/MN0aPc7F4TXr1DHt1ySFhTdkltuLP p3PHNIvDpUd3hp704Azc7Nfs4vgMGdw3Xf3g2p0/d6xIUkMdsYA5+U7mgLclSqq2r+pUP2WEETO XryxHFSMjnFjt+ehY+6JP1aYl1GW9Nv5NKxWfaMSFsYfiZd2VQ8e4CXk+Sa0ysjHL0yF5eeiGXE vANxoUFdzkJxylkE0HzvrUzLplN2vNwYKyzOEHFfzhQ9T7rpam7sud2LUF9HEQtlTJv372PxmLD nceQSMhtHHfhFC16bVmlxl30XNvn5JhBX+BwLNIZbBTfs/RVQna+jQsbhadw5zUFTTzmyBALGpt H3YtBKzmZgzXxkpSj5JEZBJIFIZSbLVnerrLBZTDz5L9M4C6OY72cnnqbfsSltt3SyfBxF6Y= X-Google-Smtp-Source: AGHT+IF0GzHSibwBrIdnpkkw5gj7w65Vb5Z9XfZX58mDgZe8ftvWBcDfJ72rdoT+NbZNWyoLPVCgew== X-Received: by 2002:a05:6a21:3287:b0:243:a705:af7a with SMTP id adf61e73a8af0-243d6f379a1mr1564062637.40.1756532580635; Fri, 29 Aug 2025 22:43:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 31/84] include/hw/core/cpu: Widen MMUIdxMap Date: Sat, 30 Aug 2025 15:40:35 +1000 Message-ID: <20250830054128.448363-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756573125141124100 Content-Type: text/plain; charset="utf-8" Widen MMUIdxMap to 32 bits. Do not yet expand NB_MMU_MODES, but widen the map type in preparation. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- accel/tcg/cputlb.c | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 23eb849a9b..fc9a2291d5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -201,7 +201,7 @@ struct CPUClass { * Fix the number of mmu modes to 16. */ #define NB_MMU_MODES 16 -typedef uint16_t MMUIdxMap; +typedef uint32_t MMUIdxMap; =20 /* Use a fully associative victim tlb of 8 entries. */ #define CPU_VTLB_SIZE 8 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2a6aa01c57..416aaa1040 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -89,9 +89,6 @@ */ QEMU_BUILD_BUG_ON(sizeof(vaddr) > sizeof(run_on_cpu_data)); =20 -/* We currently can't handle more than 16 bits in the MMUIDX bitmask. - */ -QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) =20 static inline size_t tlb_n_entries(CPUTLBDescFast *fast) --=20 2.43.0