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Put the stage2 permissions for page table walking in CPUTLBEntryFull.prot. This allows the permission checks in S1_ptw_translate and arm_casq_ptw to see the right permission. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 7 ++++ target/arm/ptw.c | 81 +++++++++++++++++++++++++++++++----------- 2 files changed, 68 insertions(+), 20 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e1f0ec2b7f..285b338aeb 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1572,6 +1572,13 @@ typedef struct ARMCacheAttrs { typedef struct GetPhysAddrResult { CPUTLBEntryFull f; ARMCacheAttrs cacheattrs; + /* + * For ARMMMUIdx_Stage2*, the protection installed into f.prot + * is the result for AccessType_TTW, i.e. the page table walk itself. + * The protection installed info s2prot is the one to be merged + * with the stage1 protection. + */ + int s2prot; } GetPhysAddrResult; =20 /** diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0432fdeed9..7ddae90f69 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1281,7 +1281,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot_noexecute(int s2ap) +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) { int prot =3D 0; =20 @@ -1291,12 +1291,6 @@ static int get_S2prot_noexecute(int s2ap) if (s2ap & 2) { prot |=3D PAGE_WRITE; } - return prot; -} - -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) -{ - int prot =3D get_S2prot_noexecute(s2ap); =20 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -1328,6 +1322,44 @@ static int get_S2prot(CPUARMState *env, int s2ap, in= t xn, bool s1_is_el0) return prot; } =20 +static int get_S2prot_indirect(CPUARMState *env, GetPhysAddrResult *result, + int pi_index, int po_index, bool s1_is_el0) +{ + /* Last index is (priv, unpriv, ttw) */ + static const uint8_t perm_table[16][3] =3D { + /* 0 */ { 0, 0, 0 }, /* no access */ + /* 1 */ { 0, 0, 0 }, /* reserved */ + /* 2 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 3 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 4 */ { PAGE_WRITE, PAGE_WRITE, 0 }, + /* 5 */ { 0, 0, 0 }, /* reserved */ + /* 6 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 7 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 8 */ { PAGE_READ, PAGE_READ, PAGE_READ }, + /* 9 */ { PAGE_READ, PAGE_READ | PAGE_EXEC, PAGE_READ }, + /* A */ { PAGE_READ | PAGE_EXEC, PAGE_READ, PAGE_READ }, + /* B */ { PAGE_READ | PAGE_EXEC, PAGE_READ | PAGE_EXEC, PAGE_READ = }, + /* C */ { PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE }, + /* D */ { PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE }, + /* E */ { PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE }, + /* F */ { PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE }, + }; + + uint64_t pir =3D (env->cp15.scr_el3 & SCR_PIEN ? env->cp15.s2pir_el2 := 0); + int s2pi =3D extract64(pir, pi_index * 4, 4); + + result->f.prot =3D perm_table[s2pi][2]; + return perm_table[s2pi][s1_is_el0]; +} + /* * Translate section/page access permissions to protection flags * @env: CPUARMState @@ -1778,7 +1810,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap; + int ap, prot; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); @@ -2096,6 +2128,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, ap =3D extract32(attrs, 6, 2); out_space =3D ptw->in_space; if (regime_is_stage2(mmu_idx)) { + if (param.pie) { + int pi =3D extract64(attrs, 6, 1) + | (extract64(attrs, 51, 1) << 1) + | (extract64(attrs, 53, 2) << 2); + int po =3D extract64(attrs, 60, 3); + prot =3D get_S2prot_indirect(env, result, pi, po, ptw->in_s1_i= s_el0); + } else { + int xn =3D extract64(attrs, 53, 2); + prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); + /* Install TTW permissions in f.prot. */ + result->f.prot =3D prot & (PAGE_READ | PAGE_WRITE); + } /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. @@ -2104,11 +2148,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, */ if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { out_space =3D ARMSS_NonSecure; - result->f.prot =3D get_S2prot_noexecute(ap); - } else { - int xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); + prot &=3D ~PAGE_EXEC; } + result->s2prot =3D prot; =20 result->cacheattrs.is_s2_format =3D true; result->cacheattrs.attrs =3D extract32(attrs, 2, 4); @@ -2180,9 +2222,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security spa= ce. */ - result->f.prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, = po, - result->f.attrs.space, - out_space); + prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, po, + result->f.attrs.space, out_space); } else { int xn =3D extract64(attrs, 54, 1); int pxn =3D extract64(attrs, 53, 1); @@ -2211,10 +2252,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security spa= ce. */ - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, - user_rw, prot_rw, xn, pxn, - result->f.attrs.space, out_space); + prot =3D get_S1prot(env, mmu_idx, aarch64, user_rw, prot_rw, x= n, pxn, + result->f.attrs.space, out_space); } + result->f.prot =3D prot; =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); @@ -2260,7 +2301,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.tlb_fill_flags =3D 0; } =20 - if (ptw->in_prot_check & ~result->f.prot) { + if (ptw->in_prot_check & ~prot) { fi->type =3D ARMFault_Permission; goto do_fault; } @@ -3458,7 +3499,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ - result->f.prot &=3D s1_prot; + result->f.prot =3D s1_prot & result->s2prot; =20 /* If S2 fails, return early. */ if (ret) { --=20 2.43.0