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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpu-features.h | 5 ++++ target/arm/tcg/cpregs-at.c | 44 +++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu64.c | 1 + docs/system/arm/emulation.rst | 1 + 5 files changed, 52 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1d103b577f..2a4826f5c4 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -854,6 +854,7 @@ typedef enum FGTBit { DO_BIT(HFGITR, DVPRCTX), DO_BIT(HFGITR, CPPRCTX), DO_BIT(HFGITR, DCCVAC), + DO_BIT(HFGITR, ATS1E1A), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e49e0ae3af..512eeaf551 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -619,6 +619,11 @@ static inline bool isar_feature_aa64_lut(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR2, LUT); } =20 +static inline bool isar_feature_aa64_ats1a(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, ATS1A); +} + static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index bebf168997..0e8f229aa7 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -488,6 +488,47 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { .writefn =3D ats_write }, }; =20 +static void ats_s1e1a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | = HCR_TGE); + ARMMMUIdx mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_= E1; + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, mmu_idx, ss); +} + +static void ats_s1e2a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + ARMMMUIdx mmu_idx =3D hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_= E2; + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, mmu_idx, ss); +} + +static void ats_s1e3a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, ARMMMUIdx_E3, + arm_security_space(env)); +} + +static const ARMCPRegInfo ats1a_reginfo[] =3D { + { .name =3D "AT_S1E1A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1A, + .accessfn =3D at_s1e01_access, .writefn =3D ats_s1e1a }, + { .name =3D "AT_S1E2A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .accessfn =3D at_s1e2_access, .writefn =3D ats_s1e2a }, + { .name =3D "AT_S1E3A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_s1e3a }, +}; + void define_at_insn_regs(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -509,4 +550,7 @@ void define_at_insn_regs(ARMCPU *cpu) if (cpu_isar_feature(aa32_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1cp_reginfo); } + if (cpu_isar_feature(aa64_ats1a, cpu)) { + define_arm_cp_regs(cpu, ats1a_reginfo); + } } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b8b1981e70..abef6a246e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1179,6 +1179,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* FEAT_CSSC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR0); diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 4e8aca8b5d..6b04c96c8c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -23,6 +23,7 @@ the following architecture extensions: - FEAT_AFP (Alternate floating-point behavior) - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) - FEAT_ASID16 (16 bit ASID) +- FEAT_ATS1A (Address Translation operations that ignore stage 1 permissio= ns) - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) --=20 2.43.0