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Fri, 29 Aug 2025 22:41:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v4 01/84] linux-user/aarch64: Split out signal_for_exception Date: Sat, 30 Aug 2025 15:40:05 +1000 Message-ID: <20250830054128.448363-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756571246357116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 84 ++++++++++++++++++++--------------- 1 file changed, 47 insertions(+), 37 deletions(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 4c4921152e..3b2782581b 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -27,11 +27,56 @@ #include "target/arm/syndrome.h" #include "target/arm/cpu-features.h" =20 +/* Use the exception syndrome to map a cpu exception to a signal. */ +static void signal_for_exception(CPUARMState *env, vaddr addr) +{ + uint32_t syn =3D env->exception.syndrome; + int si_code, si_signo; + + switch (syn_get_ec(syn)) { + case EC_DATAABORT: + case EC_INSNABORT: + /* Both EC have the same format for FSC, or close enough. */ + switch (extract32(syn, 0, 6)) { + case 0x04 ... 0x07: /* Translation fault, level {0-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MAPERR; + break; + case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ + case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_ACCERR; + break; + case 0x11: /* Synchronous Tag Check Fault */ + si_signo =3D TARGET_SIGSEGV; + si_code =3D TARGET_SEGV_MTESERR; + break; + case 0x21: /* Alignment fault */ + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + default: + g_assert_not_reached(); + } + break; + + case EC_PCALIGNMENT: + si_signo =3D TARGET_SIGBUS; + si_code =3D TARGET_BUS_ADRALN; + break; + + default: + g_assert_not_reached(); + } + + force_sig_fault(si_signo, si_code, addr); +} + /* AArch64 main loop */ void cpu_loop(CPUARMState *env) { CPUState *cs =3D env_cpu(env); - int trapnr, ec, fsc, si_code, si_signo; + int trapnr; abi_long ret; =20 for (;;) { @@ -67,42 +112,7 @@ void cpu_loop(CPUARMState *env) break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: - ec =3D syn_get_ec(env->exception.syndrome); - switch (ec) { - case EC_DATAABORT: - case EC_INSNABORT: - /* Both EC have the same format for FSC, or close enough. = */ - fsc =3D extract32(env->exception.syndrome, 0, 6); - switch (fsc) { - case 0x04 ... 0x07: /* Translation fault, level {0-3} */ - si_signo =3D TARGET_SIGSEGV; - si_code =3D TARGET_SEGV_MAPERR; - break; - case 0x09 ... 0x0b: /* Access flag fault, level {1-3} */ - case 0x0d ... 0x0f: /* Permission fault, level {1-3} */ - si_signo =3D TARGET_SIGSEGV; - si_code =3D TARGET_SEGV_ACCERR; - break; - case 0x11: /* Synchronous Tag Check Fault */ - si_signo =3D TARGET_SIGSEGV; - si_code =3D TARGET_SEGV_MTESERR; - break; - case 0x21: /* Alignment fault */ - si_signo =3D TARGET_SIGBUS; - si_code =3D TARGET_BUS_ADRALN; - break; - default: - g_assert_not_reached(); - } - break; - case EC_PCALIGNMENT: - si_signo =3D TARGET_SIGBUS; - si_code =3D TARGET_BUS_ADRALN; - break; - default: - g_assert_not_reached(); - } - force_sig_fault(si_signo, si_code, env->exception.vaddress); + signal_for_exception(env, env->exception.vaddress); break; case EXCP_DEBUG: case EXCP_BKPT: --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756569839; cv=none; d=zohomail.com; s=zohoarc; b=jsWxo9LCVoIGS40qLLcnS84HKwMj1oliGQ4z8PeYn5G5IY9TLeBNe7Q+Tmrwa1vwfXyRpLAAvQ+44bcOnQdFqwFfUBau62/LkLcZatwGqnR8hA3fMHlihZUP1LaFHqsWDFahhisz7PMRkgt0xm3mU0YYPDG3wa9sNt1UJE3BSJg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569839; 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Only pacfail uses ILL_ILLOPN (do_el0_fpac). Note that EC_MOP (do_el0_mops) ought not signal at all. For now, preserve existing behavior signalling ILL_ILLOPN. List all other exception codes and document why they do not apply to user-only. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 75 ++++++++++++++++++++++++++++++++++- 1 file changed, 74 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 3b2782581b..7ad26316de 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -65,6 +65,79 @@ static void signal_for_exception(CPUARMState *env, vaddr= addr) si_code =3D TARGET_BUS_ADRALN; break; =20 + case EC_UNCATEGORIZED: /* E.g. undefined instruction */ + case EC_SYSTEMREGISTERTRAP: /* E.g. inaccessible register */ + case EC_SMETRAP: /* E.g. invalid insn in streaming state= */ + case EC_BTITRAP: /* E.g. invalid guarded branch target */ + case EC_ILLEGALSTATE: + /* + * Illegal state happens via an ERET from a privileged mode, + * so is not normally possible from user-only. However, gdbstub + * is not prevented from writing CPSR_IL, aka PSTATE.IL, which + * would generate a trap from the next translated block. + * In the kernel, default case -> el0_inv -> bad_el0_sync. + */ + si_signo =3D TARGET_SIGILL; + si_code =3D TARGET_ILL_ILLOPC; + break; + + case EC_PACFAIL: + si_signo =3D TARGET_SIGILL; + si_code =3D TARGET_ILL_ILLOPN; + break; + + case EC_MOP: + /* + * FIXME: The kernel fixes up wrong-option exceptions. + * For QEMU linux-user mode, you can only get these if + * the process is doing something silly (not executing + * the MOPS instructions in the required P/M/E sequence), + * so it is not a problem in practice that we do not. + * + * We ought ideally to implement the same "rewind to the + * start of the sequence" logic that the kernel does in + * arm64_mops_reset_regs(). In the meantime, deliver + * the guest a SIGILL, with the same ILLOPN si_code + * we've always used for this. + */ + si_signo =3D TARGET_SIGILL; + si_code =3D TARGET_ILL_ILLOPN; + break; + + case EC_WFX_TRAP: /* user-only WFI implemented as NOP */ + case EC_CP15RTTRAP: /* AArch32 */ + case EC_CP15RRTTRAP: /* AArch32 */ + case EC_CP14RTTRAP: /* AArch32 */ + case EC_CP14DTTRAP: /* AArch32 */ + case EC_ADVSIMDFPACCESSTRAP: /* user-only does not disable fpu */ + case EC_FPIDTRAP: /* AArch32 */ + case EC_PACTRAP: /* user-only does not disable pac regs = */ + case EC_BXJTRAP: /* AArch32 */ + case EC_CP14RRTTRAP: /* AArch32 */ + case EC_AA32_SVC: /* AArch32 */ + case EC_AA32_HVC: /* AArch32 */ + case EC_AA32_SMC: /* AArch32 */ + case EC_AA64_SVC: /* generates EXCP_SWI */ + case EC_AA64_HVC: /* user-only generates EC_UNCATEGORIZED= */ + case EC_AA64_SMC: /* user-only generates EC_UNCATEGORIZED= */ + case EC_SVEACCESSTRAP: /* user-only does not disable sve */ + case EC_ERETTRAP: /* user-only generates EC_UNCATEGORIZED= */ + case EC_GPC: /* user-only has no EL3 gpc tables */ + case EC_INSNABORT_SAME_EL: /* el0 cannot trap to el0 */ + case EC_DATAABORT_SAME_EL: /* el0 cannot trap to el0 */ + case EC_SPALIGNMENT: /* sp alignment checks not implemented = */ + case EC_AA32_FPTRAP: /* fp exceptions not implemented */ + case EC_AA64_FPTRAP: /* fp exceptions not implemented */ + case EC_SERROR: /* user-only does not have hw faults */ + case EC_BREAKPOINT: /* user-only does not have hw debug */ + case EC_BREAKPOINT_SAME_EL: /* user-only does not have hw debug */ + case EC_SOFTWARESTEP: /* user-only does not have hw debug */ + case EC_SOFTWARESTEP_SAME_EL: /* user-only does not have hw debug */ + case EC_WATCHPOINT: /* user-only does not have hw debug */ + case EC_WATCHPOINT_SAME_EL: /* user-only does not have hw debug */ + case EC_AA32_BKPT: /* AArch32 */ + case EC_VECTORCATCH: /* AArch32 */ + case EC_AA64_BKPT: /* generates EXCP_BKPT */ default: g_assert_not_reached(); } @@ -108,7 +181,7 @@ void cpu_loop(CPUARMState *env) /* just indicate that signals should be handled asap */ break; case EXCP_UDEF: - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc); + signal_for_exception(env, env->pc); break; case EXCP_PREFETCH_ABORT: case EXCP_DATA_ABORT: --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570484; cv=none; d=zohomail.com; s=zohoarc; b=j0zhinKHwjTNLlmupT/55/hwTL2qJ0hvfguYtF6i+Ip41YjabApblNIShINUszxJy0qJu5nHz+J51DveRJAWFb0AvPYRDnpFLoCCAi0lLLqL4ssl7z4x1tkFkFVPJaFDvBZTXzk91CV2j7OGbpSK3CrnWbq70hIPxdGguSLrnac= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570484; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=cDcksatZM68Ouj9vpX+nhU7BNGlQ6N61jHkn+W4tDM0=; b=nnyilSG2IMVbXyDPHwMAY3nkDEzrnt1yjtHxiYb1dRazj41RYgrwnSwOjX3WdtstKePtcGnmtb2II2TIdAftUbfuood3ucH291EBDM7IHJU8lBnrI5sP6q0XFwySoKTvz2C3rBc86xGjS2geoe5PPj+n+Nqx+3LU1r85OcBaT2A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175657048430233.133131499637784; Sat, 30 Aug 2025 09:14:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNus-0002rc-Mb; Sat, 30 Aug 2025 11:54:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELT-0005oM-HU for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:41:50 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELR-00042W-2e for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:41:47 -0400 Received: by mail-pj1-x102a.google.com with SMTP id 98e67ed59e1d1-323266cdf64so2364977a91.0 for ; Fri, 29 Aug 2025 22:41:44 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:41:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 03/84] linux-user/aarch64: Generate ESR signal records Date: Sat, 30 Aug 2025 15:40:07 +1000 Message-ID: <20250830054128.448363-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570485573124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/cpu_loop.c | 3 +++ linux-user/aarch64/signal.c | 34 +++++++++++++++++++++++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 7ad26316de..6060572eed 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -33,6 +33,9 @@ static void signal_for_exception(CPUARMState *env, vaddr = addr) uint32_t syn =3D env->exception.syndrome; int si_code, si_signo; =20 + /* Let signal delivery see that ESR is live. */ + env->cp15.esr_el[1] =3D syn; + switch (syn_get_ec(syn)) { case EC_DATAABORT: case EC_INSNABORT: diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 668353bbda..ef97be3ac7 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -65,6 +65,13 @@ struct target_fpsimd_context { uint64_t vregs[32 * 2]; /* really uint128_t vregs[32] */ }; =20 +#define TARGET_ESR_MAGIC 0x45535201 + +struct target_esr_context { + struct target_aarch64_ctx head; + uint64_t esr; +}; + #define TARGET_EXTRA_MAGIC 0x45585401 =20 struct target_extra_context { @@ -201,6 +208,14 @@ static void target_setup_fpsimd_record(struct target_f= psimd_context *fpsimd, } } =20 +static void target_setup_esr_record(struct target_esr_context *ctx, + CPUARMState *env) +{ + __put_user(TARGET_ESR_MAGIC, &ctx->head.magic); + __put_user(sizeof(*ctx), &ctx->head.size); + __put_user(env->cp15.esr_el[1], &ctx->esr); +} + static void target_setup_extra_record(struct target_extra_context *extra, uint64_t datap, uint32_t extra_size) { @@ -531,6 +546,9 @@ static int target_restore_sigframe(CPUARMState *env, fpsimd =3D (struct target_fpsimd_context *)ctx; break; =20 + case TARGET_ESR_MAGIC: + break; /* ignore */ + case TARGET_SVE_MAGIC: if (sve || size < sizeof(struct target_sve_context)) { goto err; @@ -683,7 +701,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, uc.tuc_mcontext.__reserved), }; int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; - int zt_ofs =3D 0; + int zt_ofs =3D 0, esr_ofs =3D 0; int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0, zt_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -693,6 +711,15 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, fpsimd_ofs =3D alloc_sigframe_space(sizeof(struct target_fpsimd_contex= t), &layout); =20 + /* + * In user mode, ESR_EL1 is only set by cpu_loop while queueing the + * signal, and it's only valid for the one sync insn. + */ + if (env->cp15.esr_el[1]) { + esr_ofs =3D alloc_sigframe_space(sizeof(struct target_esr_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -754,6 +781,11 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, =20 target_setup_general_frame(frame, env, set); target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 +++-- target/arm/ptw.c | 11 ++++++----- target/arm/tcg/m_helper.c | 4 ++-- 3 files changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index f5a1e75db3..899242e572 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1624,8 +1624,9 @@ bool get_phys_addr_with_space_nogpc(CPUARMState *env,= vaddr address, __attribute__((nonnull)); =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool is_secure, GetPhysAddrResult *result, + MMUAccessType access_type, unsigned prot_check, + ARMMMUIdx mmu_idx, bool is_secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, uint32_t *mregion); =20 void arm_log_exception(CPUState *cs); diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ed5c728eab..9652f40ff8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2561,8 +2561,9 @@ static uint32_t *regime_rlar(CPUARMState *env, ARMMMU= Idx mmu_idx, } =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - bool secure, GetPhysAddrResult *result, + MMUAccessType access_type, unsigned prot_check, + ARMMMUIdx mmu_idx, bool secure, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi, uint32_t *mregion) { /* @@ -2750,7 +2751,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, if (arm_feature(env, ARM_FEATURE_M)) { fi->level =3D 1; } - return !(result->f.prot & (1 << access_type)); + return (prot_check & ~result->f.prot) !=3D 0; } =20 static bool v8m_is_sau_exempt(CPUARMState *env, @@ -2952,8 +2953,8 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, } } =20 - ret =3D pmsav8_mpu_lookup(env, address, access_type, mmu_idx, secure, - result, fi, NULL); + ret =3D pmsav8_mpu_lookup(env, address, access_type, 1 << access_type, + mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { result->f.lg_page_size =3D 0; } diff --git a/target/arm/tcg/m_helper.c b/target/arm/tcg/m_helper.c index 28307b5615..d856e3bc8e 100644 --- a/target/arm/tcg/m_helper.c +++ b/target/arm/tcg/m_helper.c @@ -2829,8 +2829,8 @@ uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t ad= dr, uint32_t op) ARMMMUFaultInfo fi =3D {}; =20 /* We can ignore the return value as prot is always set */ - pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, mmu_idx, targetsec, - &res, &fi, &mregion); + pmsav8_mpu_lookup(env, addr, MMU_DATA_LOAD, PAGE_READ, mmu_idx, + targetsec, &res, &fi, &mregion); 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Save the trouble of modifying all helper functions by passing the new data in the control structure. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 9652f40ff8..d37c0ce0f1 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -64,6 +64,12 @@ typedef struct S1Translate { * Stage 2 is indicated by in_mmu_idx set to ARMMMUIdx_Stage2{,_S}. */ bool in_s1_is_el0; + /* + * The set of PAGE_* bits to be use in the permission check. + * This is normally directly related to the access_type, but + * may be suppressed for debug or AT insns. + */ + uint8_t in_prot_check; bool out_rw; bool out_be; ARMSecuritySpace out_space; @@ -581,6 +587,7 @@ static bool S1_ptw_translate(CPUARMState *env, S1Transl= ate *ptw, .in_ptw_idx =3D ptw_idx_for_stage_2(env, s2_mmu_idx), .in_space =3D s2_space, .in_debug =3D true, + .in_prot_check =3D PAGE_READ, }; GetPhysAddrResult s2 =3D { }; =20 @@ -1089,7 +1096,7 @@ static bool get_phys_addr_v5(CPUARMState *env, S1Tran= slate *ptw, } result->f.prot =3D ap_to_rw_prot(env, ptw->in_mmu_idx, ap, domain_prot= ); result->f.prot |=3D result->f.prot ? PAGE_EXEC : 0; - if (!(result->f.prot & (1 << access_type))) { + if (ptw->in_prot_check & ~result->f.prot) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -1243,7 +1250,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Tran= slate *ptw, =20 result->f.prot =3D get_S1prot(env, mmu_idx, false, user_rw, prot_r= w, xn, pxn, result->f.attrs.space, out_sp= ace); - if (!(result->f.prot & (1 << access_type))) { + if (ptw->in_prot_check & ~result->f.prot) { /* Access permission fault. */ fi->type =3D ARMFault_Permission; goto do_fault; @@ -2123,7 +2130,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.tlb_fill_flags =3D 0; } =20 - if (!(result->f.prot & (1 << access_type))) { + if (ptw->in_prot_check & ~result->f.prot) { fi->type =3D ARMFault_Permission; goto do_fault; } @@ -2537,7 +2544,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, =20 fi->type =3D ARMFault_Permission; fi->level =3D 1; - return !(result->f.prot & (1 << access_type)); + return (ptw->in_prot_check & ~result->f.prot) !=3D 0; } =20 static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, @@ -2953,7 +2960,7 @@ static bool get_phys_addr_pmsav8(CPUARMState *env, } } =20 - ret =3D pmsav8_mpu_lookup(env, address, access_type, 1 << access_type, + ret =3D pmsav8_mpu_lookup(env, address, access_type, ptw->in_prot_chec= k, mmu_idx, secure, result, fi, NULL); if (sattrs.subpage) { result->f.lg_page_size =3D 0; @@ -3625,6 +3632,7 @@ bool get_phys_addr(CPUARMState *env, vaddr address, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), + .in_prot_check =3D 1 << access_type, }; =20 return get_phys_addr_gpc(env, &ptw, address, access_type, @@ -3638,6 +3646,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env,= vaddr addr, .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), .in_debug =3D true, + .in_prot_check =3D PAGE_READ, }; GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756569400; cv=none; d=zohomail.com; s=zohoarc; b=D51xqsddCND80NBzDY7LmvPwu6mDMiHRD8t3yn7ciofMNOYF7ZkdjXFIIqlEzT5Y1l2zmnbyJWIblQe2GADh9qPJHGHVMv2+hPvJSGU7ZrTKRLDjYLIP0oMbtP82smZJc9h9gUsFkbXHlNVVG/y9zmRm6BYSwg7ACIjbt+aekd0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569400; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Iwhk1HGVIv53xO1tUgspGYJaTSrp9MM6iDeDwh0Ulxk=; b=OS+gEaRn297nB2W9jGnKF0ZCjt+2ScyNFGcf5SwMeqbUkv5yV52A1rauqclID/DVpaFcSNet+/6zyHFXzYkMtKoPfiw6HocOJafxL/jzMHez2JMyL4tn+iIsoiya6kQaQWEVfHklnuhuPXm2xIArftAEzQOyqQYKe9fnrrzDDC8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756569400880147.49533134708201; Sat, 30 Aug 2025 08:56:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvG-00046h-C6; Sat, 30 Aug 2025 11:55:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELa-0005qB-Vh for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:41:55 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELZ-00044h-6D for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:41:54 -0400 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-3278efed3b0so2120073a91.2 for ; Fri, 29 Aug 2025 22:41:52 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index d37c0ce0f1..5d85610de2 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3646,7 +3646,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env,= vaddr addr, .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), .in_debug =3D true, - .in_prot_check =3D PAGE_READ, + .in_prot_check =3D 0, }; GetPhysAddrResult res =3D {}; ARMMMUFaultInfo fi =3D {}; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756577805; cv=none; d=zohomail.com; s=zohoarc; b=g0gpF7dFbkRSHwvFDZy8DNM31apJRO18lyxqR+DR6e3ruJ7CgtqBWOHGxeIBW6NZ10eNWjFdyXZgm4pegLnBUaTnRVGLr2V586WAw23Af28YgaKYJGvnQWpDcT4Cg6fe9XgbeBgEzCUmI/WXztsCz14PDBOpGpFrH1deaqLJhrw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756577805; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZIUi24UCtA+WCzxRmM2e3Q9u+Kr20hlCK3lal507EEI=; b=IupK2McYTu9fdDWmGNldGOyah+yyYzYBa/PFAhl1LNy1duEd1wlY9qjTv7NvOX0ezAl/rfRZ3Ros56zjJONpZVLlqPULZMXnbD9pMGJmD1lGL5Xdf/qBsrH0Aso+BfipjuH5VNuYBRk4hbtSaYRn35K6Gou4SCSsuZuA7vNB7uw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756577805624801.5305432914025; Sat, 30 Aug 2025 11:16:45 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNtp-0008Ni-JJ; Sat, 30 Aug 2025 11:53:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELd-0005qx-Iy for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:41:58 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELb-00045N-TU for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:41:57 -0400 Received: by mail-pf1-x432.google.com with SMTP id d2e1a72fcca58-7722c8d2846so1049582b3a.3 for ; Fri, 29 Aug 2025 22:41:55 -0700 (PDT) Received: from stoup.. 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Drop the MemOp memop argument as it doesn't make sense in the new context. Replace the access_type parameter with prot_check. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 18 +++++++----------- target/arm/ptw.c | 21 ++++++++++++++------- target/arm/tcg/cpregs-at.c | 11 ++--------- 3 files changed, 23 insertions(+), 27 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 899242e572..8782594b77 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1602,25 +1602,21 @@ bool get_phys_addr(CPUARMState *env, vaddr address, __attribute__((nonnull)); =20 /** - * get_phys_addr_with_space_nogpc: get the physical address for a virtual - * address + * get_phys_addr_for_at: * @env: CPUARMState * @address: virtual address to get physical address for - * @access_type: 0 for read, 1 for write, 2 for execute - * @memop: memory operation feeding this access, or 0 for none + * @prot_check: PAGE_{READ,WRITE,EXEC}, or 0 * @mmu_idx: MMU index indicating required translation regime * @space: security space for the access * @result: set on translation success. * @fi: set to fault info if the translation fails * - * Similar to get_phys_addr, but use the given security space and don't pe= rform - * a Granule Protection Check on the resulting address. + * Similar to get_phys_addr, but for use by AccessType_AT, i.e. + * system instructions for address translation. */ -bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, MemOp memop, - ARMMMUIdx mmu_idx, ARMSecuritySpace sp= ace, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_for_at(CPUARMState *env, vaddr address, unsigned prot_c= heck, + ARMMMUIdx mmu_idx, ARMSecuritySpace space, + GetPhysAddrResult *result, ARMMMUFaultInfo *fi) __attribute__((nonnull)); =20 bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t address, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5d85610de2..8925c9a610 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -3545,18 +3545,25 @@ static bool get_phys_addr_gpc(CPUARMState *env, S1T= ranslate *ptw, return false; } =20 -bool get_phys_addr_with_space_nogpc(CPUARMState *env, vaddr address, - MMUAccessType access_type, MemOp memop, - ARMMMUIdx mmu_idx, ARMSecuritySpace sp= ace, - GetPhysAddrResult *result, - ARMMMUFaultInfo *fi) +bool get_phys_addr_for_at(CPUARMState *env, vaddr address, + unsigned prot_check, ARMMMUIdx mmu_idx, + ARMSecuritySpace space, GetPhysAddrResult *resul= t, + ARMMMUFaultInfo *fi) { S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_space =3D space, + .in_prot_check =3D prot_check, }; - return get_phys_addr_nogpc(env, &ptw, address, access_type, - memop, result, fi); + /* + * I_MXTJT: Granule protection checks are not performed on the final + * address of a successful translation. This is a translation not a + * memory reference, so MMU_DATA_LOAD is arbitrary (the exact protecti= on + * check is handled or bypassed by .in_prot_check) and "memop =3D MO_8" + * bypasses any alignment check. + */ + return get_phys_addr_nogpc(env, &ptw, address, + MMU_DATA_LOAD, MO_8, result, fi); } =20 static ARMSecuritySpace diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index 398a61d398..2ff0b3e76f 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -27,19 +27,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t= value, MMUAccessType access_type, ARMMMUIdx mmu_idx, ARMSecuritySpace ss) { - bool ret; uint64_t par64; bool format64 =3D false; ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; - - /* - * I_MXTJT: Granule protection checks are not performed on the final - * address of a successful translation. This is a translation not a - * memory reference, so "memop =3D none =3D 0". - */ - ret =3D get_phys_addr_with_space_nogpc(env, value, access_type, 0, - mmu_idx, ss, &res, &fi); + bool ret =3D get_phys_addr_for_at(env, value, 1 << access_type, + mmu_idx, ss, &res, &fi); =20 /* * ATS operations only do S1 or S1+S2 translations, so we never --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756577440; cv=none; d=zohomail.com; s=zohoarc; b=AAsZ256v+Di0uQPJJYZEbqxJbSM9nFvcZd20opioYl9l93uwoF0TPWkZRZpdO87osJzZ7v13NKckNBlaX4GoE9ZMUOL5l18UuDqGhg/g3gXBfaIj+u0k/NMraM3B9Y62Wa3wu3HlUxuo/NonTEs21P4F6ENM+iCUjmk2T1ktdU8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756577440; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9BLUtzvTW8VOTUOKS/GDDwgNmXTZirSsYLUXuCw4aI8=; b=g4EMenaz+DVOedPUY2n1t9R4HbKZvqihuZ3M1q4lIJ6W8VDryI3nHk/QDkVnQRrg3u2Toh3lFvZVfPyMuuKWyift/F0crDGafzhoF+gh0kpKFcPK0MQa0KenSrO1fLd+MOg7eir4F+oWOVddLwk+geqLTAVLwMFzwV/Q/TZ5/IU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756577440621546.3006801599922; Sat, 30 Aug 2025 11:10:40 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvp-0007Dm-Qp; Sat, 30 Aug 2025 11:55:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELg-0005ri-Fd for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:01 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELe-00045q-IO for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:00 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-b471737b347so1849890a12.1 for ; Fri, 29 Aug 2025 22:41:57 -0700 (PDT) Received: from stoup.. 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Choose to skip both. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 8925c9a610..089eeff845 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -58,6 +58,12 @@ typedef struct S1Translate { * and will not change the state of the softmmu TLBs. */ bool in_debug; + /* + * in_at: is this AccessType_AT? + * This is also set for debug, because at heart that is also + * an address translation, and simplifies a test. + */ + bool in_at; /* * If this is stage 2 of a stage 1+2 page table walk, then this must * be true if stage 1 is an EL0 access; otherwise this is ignored. @@ -1929,7 +1935,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, descaddr &=3D ~(hwaddr)(page_size - 1); descaddr |=3D (address & (page_size - 1)); =20 - if (likely(!ptw->in_debug)) { + /* + * For AccessType_AT, DB is not updated (AArch64.SetDirtyFlag), + * and it is IMPLEMENTATION DEFINED whether AF is updated + * (AArch64.SetAccessFlag; qemu chooses to not update). + */ + if (likely(!ptw->in_at)) { /* * Access flag. * If HA is enabled, prepare to update the descriptor below. @@ -3553,6 +3564,7 @@ bool get_phys_addr_for_at(CPUARMState *env, vaddr add= ress, S1Translate ptw =3D { .in_mmu_idx =3D mmu_idx, .in_space =3D space, + .in_at =3D true, .in_prot_check =3D prot_check, }; /* @@ -3653,6 +3665,7 @@ static hwaddr arm_cpu_get_phys_page(CPUARMState *env,= vaddr addr, .in_mmu_idx =3D mmu_idx, .in_space =3D arm_mmu_idx_to_security_space(env, mmu_idx), .in_debug =3D true, + .in_at =3D true, .in_prot_check =3D 0, }; GetPhysAddrResult res =3D {}; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756576253; cv=none; d=zohomail.com; s=zohoarc; b=MBePrWCZflwHivgb+sICvW3s8k/bFpI+zQbj2598i3zVYTnRS3wYLT8l1ufBxnnINUXz7a0tylPnPgceOPJjnz5QGXJJX+6CoygPW3YlGm1rLD5dmvqu1rYhQL9Q/XlZpN1TT3v0QkLfYwDZbLuJH/DC/r1FslzP/GD2t+SOaAE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756576253; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DZyOZ5ibz8YB1lWsiaU/JxXFHwk/vo9PWaKWI3jDReA=; b=K7P4UUenhjf9RnNHEl36VLoXurfb1BhsHI74qNWliGJIobIeAYRjK2YciZn3PhZLw4P8tsOlJyNblrh5UWRuNzLvEu2GrmxsTKGLiBQAA/8OpzbhN3MqxzFfwVl+kbZlCM2OmqJIPd7mYK8GBjqKoUSvrLH2yhFB8fNrMyuNJlY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756576253371389.7964492670483; Sat, 30 Aug 2025 10:50:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvN-0004yC-0c; Sat, 30 Aug 2025 11:55:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELj-0005t9-WE for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:06 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELg-00046G-Ob for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:02 -0400 Received: by mail-pg1-x530.google.com with SMTP id 41be03b00d2f7-b49cf21320aso3039782a12.1 for ; Fri, 29 Aug 2025 22:42:00 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/cpregs-at.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index 2ff0b3e76f..bebf168997 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -24,14 +24,14 @@ static int par_el1_shareability(GetPhysAddrResult *res) } =20 static uint64_t do_ats_write(CPUARMState *env, uint64_t value, - MMUAccessType access_type, ARMMMUIdx mmu_idx, + unsigned prot_check, ARMMMUIdx mmu_idx, ARMSecuritySpace ss) { uint64_t par64; bool format64 =3D false; ARMMMUFaultInfo fi =3D {}; GetPhysAddrResult res =3D {}; - bool ret =3D get_phys_addr_for_at(env, value, 1 << access_type, + bool ret =3D get_phys_addr_for_at(env, value, prot_check, mmu_idx, ss, &res, &fi); =20 /* @@ -191,7 +191,7 @@ static uint64_t do_ats_write(CPUARMState *env, uint64_t= value, =20 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + unsigned access_perm =3D ri->opc2 & 1 ? PAGE_WRITE : PAGE_READ; uint64_t par64; ARMMMUIdx mmu_idx; int el =3D arm_current_el(env); @@ -253,7 +253,7 @@ static void ats_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) g_assert_not_reached(); } =20 - par64 =3D do_ats_write(env, value, access_type, mmu_idx, ss); + par64 =3D do_ats_write(env, value, access_perm, mmu_idx, ss); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); } @@ -261,11 +261,11 @@ static void ats_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + unsigned access_perm =3D ri->opc2 & 1 ? PAGE_WRITE : PAGE_READ; uint64_t par64; =20 /* There is no SecureEL2 for AArch32. */ - par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2, + par64 =3D do_ats_write(env, value, access_perm, ARMMMUIdx_E2, ARMSS_NonSecure); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); @@ -309,7 +309,7 @@ static CPAccessResult at_s1e01_access(CPUARMState *env,= const ARMCPRegInfo *ri, static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; + unsigned access_perm =3D ri->opc2 & 1 ? PAGE_WRITE : PAGE_READ; ARMMMUIdx mmu_idx; uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | = HCR_TGE); @@ -352,7 +352,7 @@ static void ats_write64(CPUARMState *env, const ARMCPRe= gInfo *ri, } =20 ss =3D for_el3 ? arm_security_space(env) : arm_security_space_below_el= 3(env); - env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx,= ss); + env->cp15.par_el[1] =3D do_ats_write(env, value, access_perm, mmu_idx,= ss); } =20 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756572131; cv=none; d=zohomail.com; s=zohoarc; b=NnPwgGuUBWLbxT7FnqFmAS0qC0EBJCVqSqKpQMAVbcSVL1a51K7x56JzGmIZ1E+yxnxhGMqAneNh+tEMJmGu21nC8DzsSwbwh5kZTQhcozPJ9INunx5jfBhAWg67tWhGTN2crnP2iGwn8TL8fn+qArYKX4z4zJqsf9tljFXSt4c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756572131; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=kEj8duxAu1Pam82WhtcHKlYlFMg89KDGm3ClOoILo48=; b=JqGtVuBM6xGLEkkLjP2bpJxBzabhQrlg/xA/B7xojWo+Ho51RM/nJ3plmSYPTjvhpEJzH0bEy2sq7RaV1sLuiU7QpNjAIj0S+y1c+a30kn5I4JeUHeHXepoKmDzPLje4baMxOmedRxhjOvnsksBj6oTOTyt0OAZM6OU8XOXygJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756572131385864.6444482293715; Sat, 30 Aug 2025 09:42:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNtt-0000KC-J7; Sat, 30 Aug 2025 11:53:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELl-0005tK-8R for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:07 -0400 Received: from mail-pf1-x435.google.com ([2607:f8b0:4864:20::435]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELj-00046c-OK for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:05 -0400 Received: by mail-pf1-x435.google.com with SMTP id d2e1a72fcca58-772301f8a4cso1455631b3a.3 for ; Fri, 29 Aug 2025 22:42:02 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:42:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 10/84] target/arm: Fill in HFG[RWI]TR_EL2 bits for Arm v9.5 Date: Sat, 30 Aug 2025 15:40:14 +1000 Message-ID: <20250830054128.448363-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756572132610116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index c9506aa6d5..1d103b577f 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -408,10 +408,19 @@ FIELD(HFGRTR_EL2, ERXPFGCTL_EL1, 47, 1) FIELD(HFGRTR_EL2, ERXPFGCDN_EL1, 48, 1) FIELD(HFGRTR_EL2, ERXADDR_EL1, 49, 1) FIELD(HFGRTR_EL2, NACCDATA_EL1, 50, 1) -/* 51-53: RES0 */ +/* 51: RES0 */ +FIELD(HFGRTR_EL2, NGCS_EL0, 52, 1) +FIELD(HFGRTR_EL2, NGCS_EL1, 53, 1) FIELD(HFGRTR_EL2, NSMPRI_EL1, 54, 1) FIELD(HFGRTR_EL2, NTPIDR2_EL0, 55, 1) -/* 56-63: RES0 */ +FIELD(HFGRTR_EL2, NRCWMASK_EL1, 56, 1) +FIELD(HFGRTR_EL2, NPIRE0_EL1, 57, 1) +FIELD(HFGRTR_EL2, NPIR_EL1, 58, 1) +FIELD(HFGRTR_EL2, NPOR_EL0, 59, 1) +FIELD(HFGRTR_EL2, NPOR_EL1, 60, 1) +FIELD(HFGRTR_EL2, NS2POR_EL1, 61, 1) +FIELD(HFGRTR_EL2, NMAIR2_EL1, 62, 1) +FIELD(HFGRTR_EL2, NAMAIR2_EL1, 63, 1) =20 /* These match HFGRTR but bits for RO registers are RES0 */ FIELD(HFGWTR_EL2, AFSR0_EL1, 0, 1) @@ -452,8 +461,18 @@ FIELD(HFGWTR_EL2, ERXPFGCTL_EL1, 47, 1) FIELD(HFGWTR_EL2, ERXPFGCDN_EL1, 48, 1) FIELD(HFGWTR_EL2, ERXADDR_EL1, 49, 1) FIELD(HFGWTR_EL2, NACCDATA_EL1, 50, 1) +FIELD(HFGWTR_EL2, NGCS_EL0, 52, 1) +FIELD(HFGWTR_EL2, NGCS_EL1, 53, 1) FIELD(HFGWTR_EL2, NSMPRI_EL1, 54, 1) FIELD(HFGWTR_EL2, NTPIDR2_EL0, 55, 1) +FIELD(HFGWTR_EL2, NRCWMASK_EL1, 56, 1) +FIELD(HFGWTR_EL2, NPIRE0_EL1, 57, 1) +FIELD(HFGWTR_EL2, NPIR_EL1, 58, 1) +FIELD(HFGWTR_EL2, NPOR_EL0, 59, 1) +FIELD(HFGWTR_EL2, NPOR_EL1, 60, 1) +FIELD(HFGWTR_EL2, NS2POR_EL1, 61, 1) +FIELD(HFGWTR_EL2, NMAIR2_EL1, 62, 1) +FIELD(HFGWTR_EL2, NAMAIR2_EL1, 63, 1) =20 FIELD(HFGITR_EL2, ICIALLUIS, 0, 1) FIELD(HFGITR_EL2, ICIALLU, 1, 1) @@ -512,6 +531,11 @@ FIELD(HFGITR_EL2, SVC_EL1, 53, 1) FIELD(HFGITR_EL2, DCCVAC, 54, 1) FIELD(HFGITR_EL2, NBRBINJ, 55, 1) FIELD(HFGITR_EL2, NBRBIALL, 56, 1) +FIELD(HFGITR_EL2, NGCSPUSHM_EL1, 57, 1) +FIELD(HFGITR_EL2, NGCSSTR_EL1, 58, 1) +FIELD(HFGITR_EL2, NGCSEPP, 59, 1) +FIELD(HFGITR_EL2, COSPRCTX, 60, 1) +FIELD(HFGITR_EL2, ATS1E1A, 62, 1) =20 FIELD(HDFGRTR_EL2, DBGBCRN_EL1, 0, 1) FIELD(HDFGRTR_EL2, DBGBVRN_EL1, 1, 1) --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/helper.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5a219703ae..11e1c52b70 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4563,11 +4563,6 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), "CNTKCTL", "CNTHCTL_EL2", "CNTKCTL_EL12" }, =20 - /* - * Note that redirection of ZCR is mentioned in the description - * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but - * not in the summary table. - */ { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570513; cv=none; d=zohomail.com; s=zohoarc; b=ZKR9p9tRctlQKXGOgs8fEUQsHd0zrMuna/aR5DC6x2yocrVXMV05Kq2h7Bk5PG3JsiPqQ3tKga8V76SXOQZ3i04T0OX4kGaWAQkmzBL4SwOtUlODhIgEDveU/yl2MMjhdT0jWdtJ+xFxVWCbSqPorWKetxFNtXF1BfnCXOyFnVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570513; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JXa5bV+w2XJCtl1B6/zvOBxDKz3xDTsxv0W99xe/k2Q=; b=Bvsdavi9CuvjE/8Poigq0bCpwHPNaGHJa4Sv9E6a8OO/0azLaMmPAcVwTfahRVM2EqZMu6z8ZSnhBgF6DG7k8DVYXMj3YQMBHNxKukxFjhgh5TGm+CAt6gYOy3HjUSc4rmGpuA8u8ixMHRQtX7lHkyO2hM65bt2t/KUpDGvBick= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175657051321547.21602345676274; Sat, 30 Aug 2025 09:15:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNuY-0001Kz-Ki; Sat, 30 Aug 2025 11:54:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELq-0005uL-2s for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:13 -0400 Received: from mail-pf1-x42e.google.com ([2607:f8b0:4864:20::42e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELo-00047i-E1 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:09 -0400 Received: by mail-pf1-x42e.google.com with SMTP id d2e1a72fcca58-771ff6f117aso2424037b3a.2 for ; Fri, 29 Aug 2025 22:42:07 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpu-features.h | 5 ++++ target/arm/tcg/cpregs-at.c | 44 +++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu64.c | 1 + docs/system/arm/emulation.rst | 1 + 5 files changed, 52 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 1d103b577f..2a4826f5c4 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -854,6 +854,7 @@ typedef enum FGTBit { DO_BIT(HFGITR, DVPRCTX), DO_BIT(HFGITR, CPPRCTX), DO_BIT(HFGITR, DCCVAC), + DO_BIT(HFGITR, ATS1E1A), } FGTBit; =20 #undef DO_BIT diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e49e0ae3af..512eeaf551 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -619,6 +619,11 @@ static inline bool isar_feature_aa64_lut(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR2, LUT); } =20 +static inline bool isar_feature_aa64_ats1a(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ISAR2, ATS1A); +} + static inline bool isar_feature_aa64_fp_simd(const ARMISARegisters *id) { /* We always set the AdvSIMD and FP fields identically. */ diff --git a/target/arm/tcg/cpregs-at.c b/target/arm/tcg/cpregs-at.c index bebf168997..0e8f229aa7 100644 --- a/target/arm/tcg/cpregs-at.c +++ b/target/arm/tcg/cpregs-at.c @@ -488,6 +488,47 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { .writefn =3D ats_write }, }; =20 +static void ats_s1e1a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + bool regime_e20 =3D (hcr_el2 & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | = HCR_TGE); + ARMMMUIdx mmu_idx =3D regime_e20 ? ARMMMUIdx_E20_2 : ARMMMUIdx_Stage1_= E1; + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, mmu_idx, ss); +} + +static void ats_s1e2a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); + ARMMMUIdx mmu_idx =3D hcr_el2 & HCR_E2H ? ARMMMUIdx_E20_2 : ARMMMUIdx_= E2; + ARMSecuritySpace ss =3D arm_security_space_below_el3(env); + + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, mmu_idx, ss); +} + +static void ats_s1e3a(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) +{ + env->cp15.par_el[1] =3D do_ats_write(env, value, 0, ARMMMUIdx_E3, + arm_security_space(env)); +} + +static const ARMCPRegInfo ats1a_reginfo[] =3D { + { .name =3D "AT_S1E1A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .fgt =3D FGT_ATS1E1A, + .accessfn =3D at_s1e01_access, .writefn =3D ats_s1e1a }, + { .name =3D "AT_S1E2A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .accessfn =3D at_s1e2_access, .writefn =3D ats_s1e2a }, + { .name =3D "AT_S1E3A", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 6, .crn =3D 7, .crm =3D 9, .opc2 =3D 2, + .access =3D PL3_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, + .writefn =3D ats_s1e3a }, +}; + void define_at_insn_regs(ARMCPU *cpu) { CPUARMState *env =3D &cpu->env; @@ -509,4 +550,7 @@ void define_at_insn_regs(ARMCPU *cpu) if (cpu_isar_feature(aa32_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1cp_reginfo); } + if (cpu_isar_feature(aa64_ats1a, cpu)) { + define_arm_cp_regs(cpu, ats1a_reginfo); + } } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index b8b1981e70..abef6a246e 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1179,6 +1179,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR2, BC, 1); /* FEAT_HBC */ t =3D FIELD_DP64(t, ID_AA64ISAR2, WFXT, 2); /* FEAT_WFxT */ t =3D FIELD_DP64(t, ID_AA64ISAR2, CSSC, 1); /* FEAT_CSSC */ + t =3D FIELD_DP64(t, ID_AA64ISAR2, ATS1A, 1); /* FEAT_ATS1A */ SET_IDREG(isar, ID_AA64ISAR2, t); =20 t =3D GET_IDREG(isar, ID_AA64PFR0); diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 4e8aca8b5d..6b04c96c8c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -23,6 +23,7 @@ the following architecture extensions: - FEAT_AFP (Alternate floating-point behavior) - FEAT_Armv9_Crypto (Armv9 Cryptographic Extension) - FEAT_ASID16 (16 bit ASID) +- FEAT_ATS1A (Address Translation operations that ignore stage 1 permissio= ns) - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756569728; cv=none; d=zohomail.com; s=zohoarc; b=ERJbCLDQuB+NZ1ENju04ufgjNAVo9f86uOjqwHQt+uCdaLXohoOy7qkyQpKOodANR/Qv/bA5LqC0aeb3iLCcFTlnNzkLBoE/ezuX/oTtY07wmt5be3zRMdPSIJsY3CSpEq8mEg5bciCI2q++Jq6S59tbF/5zhBPgYi4kyVGvTOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569728; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PO0Xi+l8mZtLQEAvQVUzx/DN6qW1/Pe1V+/XNJEzQZI=; b=jI6ySAYvK15BzrPLksjSULgE25Y5YVez0tz5eIPNlWCWWytxF7ze2azqC7r5si6JflgK06hISEYQp7clbEm0Y0pYUxJ88iSp06sSW4GVCUar82lawHvPLbDfa0JiS6bRqfPyEEGge6Fg/oSJF3siTAKHvP7H5dlBhwdBByKdPec= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756569728169845.825963019813; Sat, 30 Aug 2025 09:02:08 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNva-0005cE-Vx; Sat, 30 Aug 2025 11:55:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usELs-0005uf-VW for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:14 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usELr-00048e-4V for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:12 -0400 Received: by mail-pj1-x1032.google.com with SMTP id 98e67ed59e1d1-32326793a85so2258263a91.1 for ; Fri, 29 Aug 2025 22:42:10 -0700 (PDT) Received: from stoup.. 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charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpu-features.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 512eeaf551..30226814bb 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -929,6 +929,16 @@ static inline bool isar_feature_aa64_sctlr2(const ARMI= SARegisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; } =20 +static inline bool isar_feature_aa64_s1pie(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, S1PIE) !=3D 0; +} + +static inline bool isar_feature_aa64_s2pie(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, S2PIE) !=3D 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 22:42:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 14/84] target/arm: Enable TCR2_ELx.PIE Date: Sat, 30 Aug 2025 15:40:18 +1000 Message-ID: <20250830054128.448363-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756572532423124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 11e1c52b70..167362e32c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6106,8 +6106,12 @@ static CPAccessResult tcr2_el1_access(CPUARMState *e= nv, const ARMCPRegInfo *ri, static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_s1pie, cpu)) { + valid_mask |=3D TCR2_PIE; + } value &=3D valid_mask; raw_write(env, ri, value); } @@ -6115,8 +6119,12 @@ static void tcr2_el1_write(CPUARMState *env, const A= RMCPRegInfo *ri, static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { + ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D 0; =20 + if (cpu_isar_feature(aa64_s1pie, cpu)) { + valid_mask |=3D TCR2_PIE; + } value &=3D valid_mask; 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Fri, 29 Aug 2025 22:42:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 15/84] target/arm: Implement PIR_ELx, PIRE0_ELx, S2PIR_EL2 registers Date: Sat, 30 Aug 2025 15:40:19 +1000 Message-ID: <20250830054128.448363-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756576677339116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 2 ++ target/arm/cpu.h | 4 +++ target/arm/cpu.c | 4 +++ target/arm/helper.c | 70 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 80 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2a4826f5c4..9efe9238c1 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -776,6 +776,8 @@ typedef enum FGTBit { DO_BIT(HFGRTR, ERRIDR_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), + DO_REV_BIT(HFGRTR, NPIRE0_EL1), + DO_REV_BIT(HFGRTR, NPIR_EL1), =20 /* Trap bits in HDFGRTR_EL2 / HDFGWTR_EL2, starting from bit 0. */ DO_BIT(HDFGRTR, DBGBCRN_EL1), diff --git a/target/arm/cpu.h b/target/arm/cpu.h index c15d79a106..9eeecd45a3 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -369,6 +369,9 @@ typedef struct CPUArchState { uint64_t tcr2_el[3]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ + uint64_t pir_el[4]; /* PIRE0_EL1, PIR_EL1, PIR_EL2, PIR_EL3 */ + uint64_t pire0_el2; + uint64_t s2pir_el2; uint32_t c2_data; /* MPU data cacheable bits. */ uint32_t c2_insn; /* MPU instruction cacheable bits. */ union { /* MMU domain access control register @@ -1729,6 +1732,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_ENTP2 (1ULL << 41) #define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) +#define SCR_PIEN (1ULL << 45) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 27a4610da5..bf4bb04d95 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -650,6 +650,10 @@ void arm_emulate_firmware_reset(CPUState *cpustate, in= t target_el) if (cpu_isar_feature(aa64_sctlr2, cpu)) { env->cp15.scr_el3 |=3D SCR_SCTLR2EN; } + if (cpu_isar_feature(aa64_s1pie, cpu) || + cpu_isar_feature(aa64_s2pie, cpu)) { + env->cp15.scr_el3 |=3D SCR_PIEN; + } } =20 if (target_el =3D=3D 2) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 167362e32c..638d32fd80 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -747,6 +747,10 @@ static void scr_write(CPUARMState *env, const ARMCPReg= Info *ri, uint64_t value) if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D SCR_SCTLR2EN; } + if (cpu_isar_feature(aa64_s1pie, cpu) || + cpu_isar_feature(aa64_s2pie, cpu)) { + valid_mask |=3D SCR_PIEN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -4575,6 +4579,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", isar_feature_aa64_scxtnum }, =20 + { K(3, 0, 10, 2, 3), K(3, 4, 10, 2, 3), K(3, 5, 10, 2, 3), + "PIR_EL1", "PIR_EL2", "PIR_EL12", isar_feature_aa64_s1pie }, + { K(3, 0, 10, 2, 2), K(3, 4, 10, 2, 2), K(3, 5, 10, 2, 2), + "PIRE0_EL1", "PIRE0_EL2", "PIRE0_EL12", isar_feature_aa64_s1pie = }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -6143,6 +6152,60 @@ static const ARMCPRegInfo tcr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[2]) }, }; =20 +static CPAccessResult pien_access(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_PIEN) + && arm_current_el(env) < 3) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult pien_el1_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret =3D=3D CP_ACCESS_OK) { + ret =3D pien_access(env, ri, isread); + } + return ret; +} + +static const ARMCPRegInfo s1pie_reginfo[] =3D { + { .name =3D "PIR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, + .access =3D PL1_RW, .accessfn =3D pien_el1_access, + .fgt =3D FGT_NPIR_EL1, .nv2_redirect_offset =3D 0x2a0 | NV2_REDIR_NV= 1, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[1]) }, + { .name =3D "PIR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D pien_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[2]) }, + { .name =3D "PIR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 10, .crm =3D 2, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[3]) }, + { .name =3D "PIRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 2, .crn =3D 10, .crm =3D 2, + .access =3D PL1_RW, .accessfn =3D pien_el1_access, + .fgt =3D FGT_NPIRE0_EL1, .nv2_redirect_offset =3D 0x290 | NV2_REDIR_= NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.pir_el[0]) }, + { .name =3D "PIRE0_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 2, .crn =3D 10, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D pien_access, + .fieldoffset =3D offsetof(CPUARMState, cp15.pire0_el2) }, +}; + +static const ARMCPRegInfo s2pie_reginfo[] =3D { + { .name =3D "S2PIR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 5, .crn =3D 10, .crm =3D 2, + .access =3D PL2_RW, .accessfn =3D pien_access, + .nv2_redirect_offset =3D 0x2b0, + .fieldoffset =3D offsetof(CPUARMState, cp15.s2pir_el2) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7380,6 +7443,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, tcr2_reginfo); } =20 + if (cpu_isar_feature(aa64_s1pie, cpu)) { + define_arm_cp_regs(cpu, s1pie_reginfo); + } + if (cpu_isar_feature(aa64_s2pie, cpu)) { + define_arm_cp_regs(cpu, s2pie_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[122.150.204.48]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4d96829a66sm2435905a12.6.2025.08.29.22.42.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:42:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756532541; x=1757137341; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=pjcBOO95mytUtWdUeUAW/OzBEgf7hTTRCWzAcQNMZLI=; b=QooSYAGnsdPYLXabdhoRqueRjE1GXurl3HomlF96lUxymHGW3NbzJAfaoPMQXNKyWC pZ73bVDO94EmWRruzwotlFieeNsJjzipur2yiBGdZvD5c0Ou7irmPnvIw2aHXmhXsgpG aeLhTE5hpNaKMRDel5WAVqWdrVduJXCNqa0vmTylzr96cSPy9XZJjTVVv1wl7mrmS+hB UoltEiYeW6ZsdwlJ5w4vUboOrBqe8U0civDs64o+xZ92NJZXYvTvVxMtfQcZu1TdOnWM vzU7EqM/wAKD5RSLpumJcrEOpI5Kqcp3bj6dtMwcuj6/AdClSpBt+yxPt6Ay33ZHYXOR jkwQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756532541; x=1757137341; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pjcBOO95mytUtWdUeUAW/OzBEgf7hTTRCWzAcQNMZLI=; b=fJbIWiWZNKrr63+FonUgwHR5tL6LH2T1sRY2jhj15W+PIxMCBZE6HOuxiLCQnQ0zi/ UQIgpFGo+2gcxpTPuVsvHgUJVTnJKF/sG1/yDTizmrZ7a+m/XtFKOEvFJ46DhHIpfqqW 56y43NS/JBZhh2Snja9xPoa8z2jA67dUUER9/RIXLO1xAKLWGqPOau7RgtcVUoAyIBes OcK177hdiHJG+wk9HT9KODZBwWkaZYIn5nosV2UnHEsJB0+GuIpguc7Va8LURDfgNJ3H LZZ/KG4mBBTfZ9peoHdoqGe5yq8w0yyUIMrEKf+AaLMDzgvqVPRWfdB8ALyeIB9jikyK ghxQ== X-Gm-Message-State: AOJu0Yzes220rrsflZrx4HKih6s4sFvhrXNkFBGMKfwfJZycxY++tueS B/t9L5AgN6X3uIAmyoK60CV1h2DVo7ysyx12f6E5zEP/NFQ07LlAyAhSGBQzEAAzVMxLL3ZKvgg 4eXQxFpg= X-Gm-Gg: ASbGnctxJxRzgncc6oZvZYHLGKuts/GevRaddVM+EI1Uq4gnZGAN80MbZ2EH+G3KvVJ X49GzCkgrjOXWFNCmMcT6xofWxFzUPWP1U1j99/QvC31h6nySKkz8A7fh3aCf3nigDB6J/soPpS IdzpDLHsa86v2r+coGurUKQ793Hsx9SsDh7bL3U+w/e75mGmeN6ssBq/3lOi8MOYs6Wr8AttV7E k38nsXJeVGCMHRyoCXhmC6WPGvNaPJ6yHHLNWhMlRUihNoGTRkjkaDGi5muZPrl/anlI/o/5z8m THBL9uOGKnijultCwCILNjHtA6fUOHXlR2MV8LVz8OMvB6AcO38RcowtQABhbkgoeer+yJTq73W kO/3f34legMwyWYx8uSCaAUyASAu2tcgf3Fa9P7znwo1Vg4ExTa7HwputHuZ/UkN3OFSymLU= X-Google-Smtp-Source: AGHT+IHb7e1gPOtyanmDcRTBgQsHlJNOg1omy5Mn2kZPoWtdN3jmqpydOcFbw+8d+D6/mChceFR98g== X-Received: by 2002:a05:6a20:4324:b0:243:c91d:9472 with SMTP id adf61e73a8af0-243d6dd02d9mr1587353637.7.1756532540690; Fri, 29 Aug 2025 22:42:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 16/84] target/arm: Force HPD for stage2 translations Date: Sat, 30 Aug 2025 15:40:20 +1000 Message-ID: <20250830054128.448363-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570210214116600 Content-Type: text/plain; charset="utf-8" Stage2 translations do not have hierarchial permissions. Setting HPD means we can eliminate an extra check against regime_is_stage2. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/helper.c | 7 +++++-- target/arm/ptw.c | 24 +++++++++++++----------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 638d32fd80..91d6a7a5ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9533,8 +9533,11 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,= uint64_t va, tsz =3D extract32(tcr, 0, 6); gran =3D tg0_to_gran_size(extract32(tcr, 14, 2)); if (stage2) { - /* VTCR_EL2 */ - hpd =3D false; + /* + * Stage2 does not have hierarchical permissions. + * Thus disabling them makes things easier during ptw. + */ + hpd =3D true; } else { hpd =3D extract32(tcr, 24, 1); } diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 089eeff845..aecac27c54 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1472,8 +1472,12 @@ static ARMVAParameters aa32_va_parameters(CPUARMStat= e *env, uint32_t va, } tsz =3D sextract32(tcr, 0, 4) + 8; select =3D 0; - hpd =3D false; epd =3D false; + /* + * Stage2 does not have hierarchical permissions. + * Thus disabling them makes things easier during ptw. + */ + hpd =3D true; } else if (el =3D=3D 2) { /* HTCR */ tsz =3D extract32(tcr, 0, 3); @@ -1979,16 +1983,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, * except NSTable (which we have already handled). */ attrs =3D new_descriptor & (MAKE_64BIT_MASK(2, 10) | MAKE_64BIT_MASK(5= 0, 14)); - if (!regime_is_stage2(mmu_idx)) { - if (!param.hpd) { - attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ - /* - * The sense of AP[1] vs APTable[0] is reversed, as APTable[0]= =3D=3D 1 - * means "force PL1 access only", which means forcing AP[1] to= 0. - */ - attrs &=3D ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] =3D= > AP[1] */ - attrs |=3D extract32(tableattrs, 3, 1) << 7; /* APT[1] =3D>= AP[2] */ - } + if (!param.hpd) { + attrs |=3D extract64(tableattrs, 0, 2) << 53; /* XN, PXN */ + /* + * The sense of AP[1] vs APTable[0] is reversed, as APTable[0] =3D= =3D 1 + * means "force PL1 access only", which means forcing AP[1] to 0. + */ + attrs &=3D ~(extract64(tableattrs, 2, 1) << 6); /* !APT[0] =3D> AP= [1] */ + attrs |=3D extract32(tableattrs, 3, 1) << 7; /* APT[1] =3D> AP[= 2] */ } =20 ap =3D extract32(attrs, 6, 2); --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756572531; cv=none; d=zohomail.com; s=zohoarc; b=E0ZblKRSHrzeR3lSuhNmh2HLQnRcUiqe4BFoAf63yheoNYdVkHwuaFYybxRRMz/rWyLcyxBmYlCwSXOGAhHZJksItm6jY2VfoPItmHpbpEeDje9QwuKputOUYq4cAkg8MKRb4Ra09CB9ElSwq0P71ZBMVaVt6YFF1ThLhqGdV9Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756572531; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pPlzqMTyUH1o75eqZe6kHnvlek/VG80/rmWxffANEJg=; b=YkpEyj8js+rBH2NumYcqNmlIogRolzOGQuwCRGOhQqZmdaHshlGjQk210llxzk5wjMT2WwJllqwGs1AdQGwkkVvQxdv6b87Wxy9EyLSOODloJHnvQyknXNH8Xro3vG59N0Kup8M+a4Zc8sDM+8wTUmC2aPJ3wkM+imUoJt8mbmI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756572531760784.9269144000872; Sat, 30 Aug 2025 09:48:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNw8-0008Ti-ED; Sat, 30 Aug 2025 11:56:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEM6-0005y2-4P for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:26 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEM4-0004AW-IC for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:25 -0400 Received: by mail-pf1-x42c.google.com with SMTP id d2e1a72fcca58-77238cb3cbbso727114b3a.0 for ; Fri, 29 Aug 2025 22:42:24 -0700 (PDT) Received: from stoup.. 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Cache it early, as we will shortly need it elsewhere as well. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index aecac27c54..214279ffeb 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -76,6 +76,8 @@ typedef struct S1Translate { * may be suppressed for debug or AT insns. */ uint8_t in_prot_check; + /* Cached EffectiveHCR_EL2_NVx() bit */ + bool in_nv1; bool out_rw; bool out_be; ARMSecuritySpace out_space; @@ -1642,12 +1644,6 @@ static bool lpae_block_desc_valid(ARMCPU *cpu, bool = ds, } } =20 -static bool nv_nv1_enabled(CPUARMState *env, S1Translate *ptw) -{ - uint64_t hcr =3D arm_hcr_el2_eff_secstate(env, ptw->in_space); - return (hcr & (HCR_NV | HCR_NV1)) =3D=3D (HCR_NV | HCR_NV1); -} - /** * get_phys_addr_lpae: perform one stage of page table walk, LPAE format * @@ -1699,6 +1695,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, !arm_el_is_aa64(env, 1)); level =3D 0; =20 + /* Cache NV1 before we adjust ptw->in_space for NSTable. */ + ptw->in_nv1 =3D (arm_hcr_el2_eff_secstate(env, ptw->in_space) + & (HCR_NV | HCR_NV1)) =3D=3D (HCR_NV | HCR_NV1); + /* * If TxSZ is programmed to a value larger than the maximum, * or smaller than the effective minimum, it is IMPLEMENTATION @@ -2074,7 +2074,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, xn =3D extract64(attrs, 54, 1); pxn =3D extract64(attrs, 53, 1); =20 - if (el =3D=3D 1 && nv_nv1_enabled(env, ptw)) { + if (el =3D=3D 1 && ptw->in_nv1) { /* * With FEAT_NV, when HCR_EL2.{NV,NV1} =3D=3D {1,1}, the block= /page * descriptor bit 54 holds PXN, 53 is RES0, and the effective = value --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756576117; cv=none; d=zohomail.com; s=zohoarc; b=NbA9XGgrFgmePAtkkmJIFiDQPEPMGQdIYmBdsfsWN4vkoSkO2lXeHSIpNrLIP4jsyPRy+X6+3IyfijBuj7fxqpwWWcFB5A9AMKfXssjkluNhKIMtSFACx1KOsM3uHAEBsz6OF08KuYHrDeKAXy31CB9wPw9gi7EfuTbyBO8JhIM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756576117; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=nj96dS+M8kKPovZfBVhDgSl+RUPXB/i0J54XfFQ1BNQ=; b=hyqzGjSr4NhU99dxPgm/9KHFc0tR+Zlio7bw2Rur5Vhhazes5KADMN/dREfCvfYRb8Wqe2y/2U4YcHbAlJi4QPqMYxHRHaKkMo98cFUNy+1Wc0w6w0HHB1eV4pP2KquyvneoGt9YixUsvUcjwsAhZAy70jwZFO/vYSPJchYtMNM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756576117124605.9289287688607; Sat, 30 Aug 2025 10:48:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvp-0007Dn-R5; Sat, 30 Aug 2025 11:55:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEM9-0005yZ-82 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:30 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEM7-0004B8-7r for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:29 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-770530175b2so2181824b3a.3 for ; Fri, 29 Aug 2025 22:42:26 -0700 (PDT) Received: from stoup.. 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With PIE, the PTE layout changes, forcing HPD. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 ++- target/arm/helper.c | 19 ++++++++++++++++++- 2 files changed, 20 insertions(+), 2 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 8782594b77..e1f0ec2b7f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1486,7 +1486,7 @@ static inline int arm_granule_bits(ARMGranuleSize gra= n) =20 /* * Parameters of a given virtual address, as extracted from the - * translation control register (TCR) for a given regime. + * translation controls for a given regime. */ typedef struct ARMVAParameters { unsigned tsz : 8; @@ -1501,6 +1501,7 @@ typedef struct ARMVAParameters { bool ha : 1; bool hd : 1; ARMGranuleSize gran : 2; + bool pie : 1; } ARMVAParameters; =20 /** diff --git a/target/arm/helper.c b/target/arm/helper.c index 91d6a7a5ae..ab801e2704 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9522,11 +9522,12 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env= , uint64_t va, bool el1_is_aa32) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - bool epd, hpd, tsz_oob, ds, ha, hd; + bool epd, hpd, tsz_oob, ds, ha, hd, pie =3D false; int select, tsz, tbi, max_tsz, min_tsz, ps, sh; ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); bool stage2 =3D regime_is_stage2(mmu_idx); + int r_el =3D regime_el(env, mmu_idx); =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; @@ -9538,8 +9539,17 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,= uint64_t va, * Thus disabling them makes things easier during ptw. */ hpd =3D true; + pie =3D extract64(tcr, 36, 1) && cpu_isar_feature(aa64_s2pie, = cpu); } else { hpd =3D extract32(tcr, 24, 1); + if (r_el =3D=3D 3) { + pie =3D (extract64(tcr, 35, 1) + && cpu_isar_feature(aa64_s1pie, cpu)); + } else { + pie =3D ((env->cp15.tcr2_el[2] & TCR2_PIE) + && (!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN))); + } } epd =3D false; sh =3D extract32(tcr, 12, 2); @@ -9579,7 +9589,13 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env,= uint64_t va, regime_is_user(env, mmu_idx)) { epd =3D true; } + + pie =3D ((env->cp15.tcr2_el[r_el] & TCR2_PIE) + && (!arm_feature(env, ARM_FEATURE_EL3) + || (env->cp15.scr_el3 & SCR_TCR2EN)) + && (r_el =3D=3D 2 || (arm_hcrx_el2_eff(env) & HCRX_TCR2EN))= ); } + hpd |=3D pie; =20 gran =3D sanitize_gran_size(cpu, gran, stage2); =20 @@ -9658,6 +9674,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, .ha =3D ha, .hd =3D ha && hd, .gran =3D gran, + .pie =3D pie, }; } =20 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756574503; cv=none; d=zohomail.com; s=zohoarc; b=Syr1apP5InLrNr4wFD69WR3gCLGh4gefG8T318wkyHjvws8HKFEesHiJilIeqLhCdie7JpZVTWlQPUSk5DdQvH0p6AAo3EdZx+VRCvaffRRyyebLZaiML6tNoGBMuwz6/V6p1e848ktVclXIcHUMxhcuCcS2Qgf/417/9hP5DM0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756574503; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=U5cP/uHC4aNVP8kzqeh90Hr2U8wb3GLeLhhXB3LBCnw=; b=VZ+HKzFN037HkS2636aPYj3l4mSsEmBIPBaCLgO3O41cWFD4V6+CL7+UTIWo6qJqtgWbvvWnta+xR/44DWyH5O90sSUxB528ixqCEd0XV/Wsn3FmSf5jtAGPmxme+BX7SkDGlEY5crUAhCBbg/kwiP0XixDxNfAeWc1F5qja5i8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756574503174700.7097450594092; Sat, 30 Aug 2025 10:21:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNwL-0000IJ-49; Sat, 30 Aug 2025 11:56:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMC-00060e-6Q for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:34 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEM9-0004BR-PI for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:31 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-b475dfb4f42so1925402a12.0 for ; Fri, 29 Aug 2025 22:42:29 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 169 +++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 143 insertions(+), 26 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 214279ffeb..0432fdeed9 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1449,6 +1449,106 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx m= mu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } =20 +/* Extra page permission bits, during get_S1prot_indirect only. */ +#define PAGE_GCS (1 << 3) +#define PAGE_WXN (1 << 4) +#define PAGE_OVERLAY (1 << 5) +QEMU_BUILD_BUG_ON(PAGE_RWX & (PAGE_GCS | PAGE_WXN | PAGE_OVERLAY)); + +static int get_S1prot_indirect(CPUARMState *env, S1Translate *ptw, + ARMMMUIdx mmu_idx, int pi_index, int po_ind= ex, + ARMSecuritySpace in_pa, ARMSecuritySpace ou= t_pa) +{ + static const uint8_t perm_table[16] =3D { + /* 0 */ PAGE_OVERLAY, /* no access */ + /* 1 */ PAGE_OVERLAY | PAGE_READ, + /* 2 */ PAGE_OVERLAY | PAGE_EXEC, + /* 3 */ PAGE_OVERLAY | PAGE_READ | PAGE_EXEC, + /* 4 */ PAGE_OVERLAY, /* reserved */ + /* 5 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE, + /* 6 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE | PAGE_EXEC | PAGE_W= XN, + /* 7 */ PAGE_OVERLAY | PAGE_READ | PAGE_WRITE | PAGE_EXEC, + /* 8 */ PAGE_READ, + /* 9 */ PAGE_READ | PAGE_GCS, + /* A */ PAGE_READ | PAGE_EXEC, + /* B */ 0, /* reserved */ + /* C */ PAGE_READ | PAGE_WRITE, + /* D */ 0, /* reserved */ + /* E */ PAGE_READ | PAGE_WRITE | PAGE_EXEC, + /* F */ 0, /* reserved */ + }; + + uint32_t el =3D regime_el(env, mmu_idx); + uint64_t pir =3D env->cp15.pir_el[el]; + uint64_t pire0 =3D 0; + int perm; + + if (el < 3) { + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_PIEN)) { + pir =3D 0; + } else if (el =3D=3D 2) { + pire0 =3D env->cp15.pire0_el2; + } else if (!ptw->in_nv1) { + pire0 =3D env->cp15.pir_el[0]; + } + } + perm =3D perm_table[extract64(pir, pi_index * 4, 4)]; + + if (regime_has_2_ranges(mmu_idx)) { + int p_perm =3D perm; + int u_perm =3D perm_table[extract64(pire0, pi_index * 4, 4)]; + + if ((p_perm & (PAGE_EXEC | PAGE_GCS)) && + (u_perm & (PAGE_WRITE | PAGE_GCS))) { + p_perm &=3D ~(PAGE_RWX | PAGE_GCS); + u_perm &=3D ~(PAGE_RWX | PAGE_GCS); + } + if ((u_perm & (PAGE_RWX | PAGE_GCS)) && regime_is_pan(env, mmu_idx= )) { + p_perm &=3D ~(PAGE_READ | PAGE_WRITE); + } + perm =3D regime_is_user(env, mmu_idx) ? u_perm : p_perm; + } + + if (in_pa !=3D out_pa) { + switch (in_pa) { + case ARMSS_Root: + /* + * R_ZWRVD: permission fault for insn fetched from non-Root, + * I_WWBFB: SIF has no effect in EL3. + */ + perm &=3D ~(PAGE_EXEC | PAGE_GCS); + break; + case ARMSS_Realm: + /* + * R_PKTDS: permission fault for insn fetched from non-Realm, + * for Realm EL2 or EL2&0. The corresponding fault for EL1&0 + * happens during any stage2 translation. + */ + if (el =3D=3D 2) { + perm &=3D ~(PAGE_EXEC | PAGE_GCS); + } + break; + case ARMSS_Secure: + if (env->cp15.scr_el3 & SCR_SIF) { + perm &=3D ~(PAGE_EXEC | PAGE_GCS); + } + break; + default: + /* Input NonSecure must have output NonSecure. */ + g_assert_not_reached(); + } + } + + if (perm & PAGE_WXN) { + perm &=3D ~PAGE_EXEC; + } + + /* TODO: FEAT_GCS */ + + return perm & PAGE_RWX; +} + static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va, ARMMMUIdx mmu_idx) { @@ -1678,7 +1778,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap, xn, pxn; + int ap; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); @@ -2006,7 +2106,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, out_space =3D ARMSS_NonSecure; result->f.prot =3D get_S2prot_noexecute(ap); } else { - xn =3D extract64(attrs, 53, 2); + int xn =3D extract64(attrs, 53, 2); result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); } =20 @@ -2022,7 +2122,6 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int nse, ns =3D extract32(attrs, 5, 1); uint8_t attrindx; uint64_t mair; - int user_rw, prot_rw; =20 switch (out_space) { case ARMSS_Root: @@ -2071,33 +2170,51 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, default: g_assert_not_reached(); } - xn =3D extract64(attrs, 54, 1); - pxn =3D extract64(attrs, 53, 1); =20 - if (el =3D=3D 1 && ptw->in_nv1) { + if (param.pie) { + int pi =3D extract64(attrs, 6, 1) + | (extract64(attrs, 51, 1) << 1) + | (extract64(attrs, 53, 2) << 2); + int po =3D extract64(attrs, 60, 3); /* - * With FEAT_NV, when HCR_EL2.{NV,NV1} =3D=3D {1,1}, the block= /page - * descriptor bit 54 holds PXN, 53 is RES0, and the effective = value - * of UXN is 0. Similarly for bits 59 and 60 in table descript= ors - * (which we have already folded into bits 53 and 54 of attrs). - * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. - * Similarly, APTable[0] from the table descriptor is treated = as 0; - * we already folded this into AP[1] and squashing that to 0 d= oes - * the right thing. + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security spa= ce. */ - pxn =3D xn; - xn =3D 0; - ap &=3D ~1; - } + result->f.prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, = po, + result->f.attrs.space, + out_space); + } else { + int xn =3D extract64(attrs, 54, 1); + int pxn =3D extract64(attrs, 53, 1); + int user_rw, prot_rw; =20 - user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); - prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); - /* - * Note that we modified ptw->in_space earlier for NSTable, but - * result->f.attrs retains a copy of the original security space. - */ - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, user_rw, prot= _rw, - xn, pxn, result->f.attrs.space, out_sp= ace); + if (el =3D=3D 1 && ptw->in_nv1) { + /* + * With FEAT_NV, when HCR_EL2.{NV,NV1} =3D=3D {1,1}, + * the block/page descriptor bit 54 holds PXN, + * 53 is RES0, and the effective value of UXN is 0. + * Similarly for bits 59 and 60 in table descriptors + * (which we have already folded into bits 53 and 54 of at= trs). + * AP[1] (descriptor bit 6, our ap bit 0) is treated as 0. + * Similarly, APTable[0] from the table descriptor is trea= ted + * as 0; we already folded this into AP[1] and squashing + * that to 0 does the right thing. + */ + pxn =3D xn; + xn =3D 0; + ap &=3D ~1; + } + + user_rw =3D simple_ap_to_rw_prot_is_user(ap, true); + prot_rw =3D simple_ap_to_rw_prot_is_user(ap, false); + /* + * Note that we modified ptw->in_space earlier for NSTable, but + * result->f.attrs retains a copy of the original security spa= ce. + */ + result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, + user_rw, prot_rw, xn, pxn, + result->f.attrs.space, out_space); + } =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570381; cv=none; d=zohomail.com; s=zohoarc; b=joD1rhiVpedv+SHoIaQ0cves/BQ70YB3P5l6Xwh8YFiMhGcK2eUKVLut/P+hXwH6V+iiAAlBvni1Xa7zq9Lb+K/25iQp64gpf2bi/4f04QZeUVZJ4hBfFfx1D2AunB+1zMl1NwsY7F41HgWZz1Qf4/eXQnqpZKrmUwZrrL/pVHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570381; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=u2GmE67o8C4YSTNg11rlje/tEkSO2hH3WtNNVV3Iovw=; b=bnvQXY4p2ugSYGCMwdxRX3EOwaJ11JxHUllpcrNAttNPOUj2EAbYIa0YuGscQU/yEovuZ6CIIn02WzyvqyRmqFyehwe8Azje0JaUo3RN1Sn8wHGKlLxCdHXmoR8XG/C1/7ktf52/J2lATmXNknhHf+VdCn5NW+TjCNYpkUh93Q4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756570381360691.8555368401429; Sat, 30 Aug 2025 09:13:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvs-0007SW-Ap; Sat, 30 Aug 2025 11:56:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEME-000611-Qs for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:35 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMC-0004Br-JZ for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:34 -0400 Received: by mail-pj1-x102d.google.com with SMTP id 98e67ed59e1d1-323267bc2eeso2083006a91.1 for ; Fri, 29 Aug 2025 22:42:31 -0700 (PDT) Received: from stoup.. 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Put the stage2 permissions for page table walking in CPUTLBEntryFull.prot. This allows the permission checks in S1_ptw_translate and arm_casq_ptw to see the right permission. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 7 ++++ target/arm/ptw.c | 81 +++++++++++++++++++++++++++++++----------- 2 files changed, 68 insertions(+), 20 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e1f0ec2b7f..285b338aeb 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1572,6 +1572,13 @@ typedef struct ARMCacheAttrs { typedef struct GetPhysAddrResult { CPUTLBEntryFull f; ARMCacheAttrs cacheattrs; + /* + * For ARMMMUIdx_Stage2*, the protection installed into f.prot + * is the result for AccessType_TTW, i.e. the page table walk itself. + * The protection installed info s2prot is the one to be merged + * with the stage1 protection. + */ + int s2prot; } GetPhysAddrResult; =20 /** diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 0432fdeed9..7ddae90f69 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1281,7 +1281,7 @@ do_fault: * @xn: XN (execute-never) bits * @s1_is_el0: true if this is S2 of an S1+2 walk for EL0 */ -static int get_S2prot_noexecute(int s2ap) +static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) { int prot =3D 0; =20 @@ -1291,12 +1291,6 @@ static int get_S2prot_noexecute(int s2ap) if (s2ap & 2) { prot |=3D PAGE_WRITE; } - return prot; -} - -static int get_S2prot(CPUARMState *env, int s2ap, int xn, bool s1_is_el0) -{ - int prot =3D get_S2prot_noexecute(s2ap); =20 if (cpu_isar_feature(any_tts2uxn, env_archcpu(env))) { switch (xn) { @@ -1328,6 +1322,44 @@ static int get_S2prot(CPUARMState *env, int s2ap, in= t xn, bool s1_is_el0) return prot; } =20 +static int get_S2prot_indirect(CPUARMState *env, GetPhysAddrResult *result, + int pi_index, int po_index, bool s1_is_el0) +{ + /* Last index is (priv, unpriv, ttw) */ + static const uint8_t perm_table[16][3] =3D { + /* 0 */ { 0, 0, 0 }, /* no access */ + /* 1 */ { 0, 0, 0 }, /* reserved */ + /* 2 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 3 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 4 */ { PAGE_WRITE, PAGE_WRITE, 0 }, + /* 5 */ { 0, 0, 0 }, /* reserved */ + /* 6 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 7 */ { PAGE_READ, PAGE_READ, PAGE_READ | PAGE_WRITE }, + /* 8 */ { PAGE_READ, PAGE_READ, PAGE_READ }, + /* 9 */ { PAGE_READ, PAGE_READ | PAGE_EXEC, PAGE_READ }, + /* A */ { PAGE_READ | PAGE_EXEC, PAGE_READ, PAGE_READ }, + /* B */ { PAGE_READ | PAGE_EXEC, PAGE_READ | PAGE_EXEC, PAGE_READ = }, + /* C */ { PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE }, + /* D */ { PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE }, + /* E */ { PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE, + PAGE_READ | PAGE_WRITE }, + /* F */ { PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE | PAGE_EXEC, + PAGE_READ | PAGE_WRITE }, + }; + + uint64_t pir =3D (env->cp15.scr_el3 & SCR_PIEN ? env->cp15.s2pir_el2 := 0); + int s2pi =3D extract64(pir, pi_index * 4, 4); + + result->f.prot =3D perm_table[s2pi][2]; + return perm_table[s2pi][s1_is_el0]; +} + /* * Translate section/page access permissions to protection flags * @env: CPUARMState @@ -1778,7 +1810,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int32_t stride; int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); - int ap; + int ap, prot; uint32_t el =3D regime_el(env, mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); @@ -2096,6 +2128,18 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, ap =3D extract32(attrs, 6, 2); out_space =3D ptw->in_space; if (regime_is_stage2(mmu_idx)) { + if (param.pie) { + int pi =3D extract64(attrs, 6, 1) + | (extract64(attrs, 51, 1) << 1) + | (extract64(attrs, 53, 2) << 2); + int po =3D extract64(attrs, 60, 3); + prot =3D get_S2prot_indirect(env, result, pi, po, ptw->in_s1_i= s_el0); + } else { + int xn =3D extract64(attrs, 53, 2); + prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); + /* Install TTW permissions in f.prot. */ + result->f.prot =3D prot & (PAGE_READ | PAGE_WRITE); + } /* * R_GYNXY: For stage2 in Realm security state, bit 55 is NS. * The bit remains ignored for other security states. @@ -2104,11 +2148,9 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, */ if (out_space =3D=3D ARMSS_Realm && extract64(attrs, 55, 1)) { out_space =3D ARMSS_NonSecure; - result->f.prot =3D get_S2prot_noexecute(ap); - } else { - int xn =3D extract64(attrs, 53, 2); - result->f.prot =3D get_S2prot(env, ap, xn, ptw->in_s1_is_el0); + prot &=3D ~PAGE_EXEC; } + result->s2prot =3D prot; =20 result->cacheattrs.is_s2_format =3D true; result->cacheattrs.attrs =3D extract32(attrs, 2, 4); @@ -2180,9 +2222,8 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security spa= ce. */ - result->f.prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, = po, - result->f.attrs.space, - out_space); + prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, po, + result->f.attrs.space, out_space); } else { int xn =3D extract64(attrs, 54, 1); int pxn =3D extract64(attrs, 53, 1); @@ -2211,10 +2252,10 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1= Translate *ptw, * Note that we modified ptw->in_space earlier for NSTable, but * result->f.attrs retains a copy of the original security spa= ce. */ - result->f.prot =3D get_S1prot(env, mmu_idx, aarch64, - user_rw, prot_rw, xn, pxn, - result->f.attrs.space, out_space); + prot =3D get_S1prot(env, mmu_idx, aarch64, user_rw, prot_rw, x= n, pxn, + result->f.attrs.space, out_space); } + result->f.prot =3D prot; =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); @@ -2260,7 +2301,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, result->f.tlb_fill_flags =3D 0; } =20 - if (ptw->in_prot_check & ~result->f.prot) { + if (ptw->in_prot_check & ~prot) { fi->type =3D ARMFault_Permission; goto do_fault; } @@ -3458,7 +3499,7 @@ static bool get_phys_addr_twostage(CPUARMState *env, = S1Translate *ptw, fi->s2addr =3D ipa; =20 /* Combine the S1 and S2 perms. */ - result->f.prot &=3D s1_prot; + result->f.prot =3D s1_prot & result->s2prot; =20 /* If S2 fails, return early. */ if (ret) { --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756569401; cv=none; d=zohomail.com; s=zohoarc; b=kj1b+GvI3T0CQ6tVZMpxB/QhDo1TUIhCE6Q8Vqh273Gu5Xg5uMbg4yToNCBK5Bmcl1DhdZyLnewaFxt9m+Ry0qyWHzPTw+oRGn6KkLscyLJuaq5hUsMyf/2dhLHzJXN5oEkT2KO7hHDCuToKUBzMcF0FBQxrec71oVUA5OHTwYg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569401; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/machine.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 6986915bee..8dbeca2867 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -1085,9 +1085,9 @@ const VMStateDescription vmstate_arm_cpu =3D { VMSTATE_UINT64(env.exclusive_val, ARMCPU), VMSTATE_UINT64(env.exclusive_high, ARMCPU), VMSTATE_UNUSED(sizeof(uint64_t)), - VMSTATE_UINT32(env.exception.syndrome, ARMCPU), - VMSTATE_UINT32(env.exception.fsr, ARMCPU), - VMSTATE_UINT64(env.exception.vaddress, ARMCPU), + VMSTATE_UNUSED(sizeof(uint32_t)), + VMSTATE_UNUSED(sizeof(uint32_t)), + VMSTATE_UNUSED(sizeof(uint64_t)), VMSTATE_TIMER_PTR(gt_timer[GTIMER_PHYS], ARMCPU), VMSTATE_TIMER_PTR(gt_timer[GTIMER_VIRT], ARMCPU), { --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756578387; cv=none; d=zohomail.com; s=zohoarc; b=lGQIgTU4u5Nwurh+9W0RgDZVIvcGw3MUxeTB0HR0smYIr9DKwDZGMc0gGIgEg1V70KB7s9/2XXqUsB9W4c3+sQLAHLEBp4/mAVHYy6utXUslOeuncyW4vRI1SEpCr6tztOohmG+85SgX1h5qHc4DgUYoQW3UTnr8BOzvVRftygk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756578387; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=9qdzdzmqkJ1XgfZtAa367u2Lrhe3gNI4FuUAtbTsqDg=; b=eU3D/C/Ok83cgtwkP9Kl3zGClXoJJl9TG9+jcXBpphiNAqoPBg5bmczIK0TUQs+1LDDzb2dFHyUh++06HsEhfYjueuNQGqafGHeJZw3V65yqyfJTnpQUeE4G1wb2P5AF+xflnnm7qCrUpN7D7p7vEi0ezQ2o1D38xn355x7HJKE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756578387693167.9217130180533; Sat, 30 Aug 2025 11:26:27 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNwR-0000fY-0j; Sat, 30 Aug 2025 11:56:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMJ-00063F-PJ for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:40 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMI-0004Ct-7m for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:39 -0400 Received: by mail-pf1-x42f.google.com with SMTP id d2e1a72fcca58-7704f3c46ceso2460127b3a.2 for ; Fri, 29 Aug 2025 22:42:37 -0700 (PDT) Received: from stoup.. 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Re-order the fsr member to eliminate two structure holes. Drop the comment about "if we implement EL2" since we have already done so. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpu.h | 7 ++----- target/arm/helper.c | 2 +- 2 files changed, 3 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9eeecd45a3..fff2195138 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -635,13 +635,10 @@ typedef struct CPUArchState { * entry process. */ struct { - uint32_t syndrome; /* AArch64 format syndrome register */ - uint32_t fsr; /* AArch32 format fault status register info */ + uint64_t syndrome; /* AArch64 format syndrome register */ uint64_t vaddress; /* virtual addr associated with exception, if a= ny */ + uint32_t fsr; /* AArch32 format fault status register info */ uint32_t target_el; /* EL the exception should be targeted for */ - /* If we implement EL2 we will also need to store information - * about the intermediate physical address for stage 2 faults. - */ } exception; =20 /* Information associated with an SError */ diff --git a/target/arm/helper.c b/target/arm/helper.c index ab801e2704..fc95010727 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9332,7 +9332,7 @@ void arm_cpu_do_interrupt(CPUState *cs) new_el); if (qemu_loglevel_mask(CPU_LOG_INT) && !excp_is_internal(cs->exception_index)) { - qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx32 "\n", + qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%x/0x%" PRIx64 "\n", syn_get_ec(env->exception.syndrome), env->exception.syndrome); } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756577460; cv=none; d=zohomail.com; s=zohoarc; b=jkqQl4PkPyYVt3QWW1mvyGyu1GIisDvbg/NWBeplTxnyktOiC64QMbH4q1BV2RiVBh9VMWNYWQqSxFjKVTs2MG772bOXMCbF+E1L50JZ7EYV0HNIRSpPoDWBMFvoixqW4DyzTzuZ4x+52jo7CUgMSilhphdYj7fsmvnT5yyhesA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756577460; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Xz6K6b/NcWzA9krG2jmDsuQPjPRc6na7yx50YdzA0DA=; b=PFRKFa19AsspkONtmQhf2+G/960j3QBsgAugfQh3M2zXRJxLuybnpJuhWdF+tAtirQXnfJ4IXXhuoxo0xZCI7bvibUeFf0/YEh05gVpKITSD+JUda8XBXtto45lpnqbLSGrkGzbpZy/hTVuzYCrzGiCAVsTN6RoDGB5KzFgHhhU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756577460425663.6070535043635; Sat, 30 Aug 2025 11:11:00 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNwU-0000uG-IV; Sat, 30 Aug 2025 11:56:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMO-00064P-8Y for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:44 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEML-0004DS-2q for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:43 -0400 Received: by mail-pj1-x1034.google.com with SMTP id 98e67ed59e1d1-32753ef4e33so2086672a91.0 for ; Fri, 29 Aug 2025 22:42:40 -0700 (PDT) Received: from stoup.. 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[122.150.204.48]) by smtp.gmail.com with ESMTPSA id 41be03b00d2f7-b4d96829a66sm2435905a12.6.2025.08.29.22.42.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:42:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756532559; x=1757137359; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Xz6K6b/NcWzA9krG2jmDsuQPjPRc6na7yx50YdzA0DA=; b=y5DFKxF34yNCy9+vhF0ESHnd1b9RSHknGMjYd9Rp1Hlw7Yp2TFLYYwzOvLKMIQrrrF S9iPvduUCb4yst0YPm6FaHa74le2rB/6HgI+V9VRhVq63wHifT6meHwxlgE2q+59z/i/ uoGJF7rk3QpUIUrtMpvthV+gLF7l7c8PweK5yLzp3feyMcRGdoMqBJ4f0OR6cvDwISCW 8xP6lhKVcuuMJrJP1W8JwpYJUuR1Nt12GAu9JwBKR8Spg2KpYmvQ5slvca0QHqPTu1x3 bSi5KyLq/Ox1y60o0IdWMlDRW4EY8XPeJiHQJv60w1VTE3mDchNCaBIjpAGUqvKAJwzO IhUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756532559; x=1757137359; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Xz6K6b/NcWzA9krG2jmDsuQPjPRc6na7yx50YdzA0DA=; b=K6bA8KiQ/jVEGXLiCCzKIb4/fLWYUJrJOZHebGnhOnJwW09At7iyytOwyeVg3tzVMZ YGohs5cFm1N41f0lZcXJRqcr2JVeUHQPBg8r3zQ5qc84Mc/UA1IXruWUnhpLkpOG+BMv F1JnZWAGLzgk/qrLC28t7hEtIYRK4ngCs623n1u76wV5Gl1UeCUvbPh/P2kC85QvnQiO rCJ5nepJvDWTc7YHX2MlPwhSl6ENU9e/M5kOu7xk8t0uImkByFZbaZwiXUJ7cHKMLoRh StEtnTF3/MCxtB2qm8BUVxSK0DhGwazARMTT1jXoyH65IOYu6L7PTJKswRAlon3bTK7K VrVA== X-Gm-Message-State: AOJu0YwhoxygOalcAm3JXLX48o3UGrMcPULBTsN8OfCQ0GZdlEtnoMw5 8kGjQ2bS4b+e+tqIDNiCUNnosKos/Ucwd/GbwDc2lzbsb6I1gP6GWGMukUwF62ZLXkI9lp8DoJn vcSFhONM= X-Gm-Gg: ASbGncuq1oJvfqKj3TyuKzZNfZF4rEVCujqriVaqbnijLo3Qs8qsJlIy0KjK7p1XRaA om9/t4mDD6085CcZ/mbsODyKhBsknsujCh9Y0CneNSbTPJJLcasI2eiPXj0c7MJ223oMQ/BkRy7 oxn2tgK2UBirBzieJUBVwPwJp6S27t6XuZ/W2f6i8qguOWot3Eh98XPy7i9GrC+XASM6NsoDrmx 7fT4xpU/fZX8v1jfB1Ty2DDw1AqxTfWETZbEtiyScrwfEpNS62mbgbF8vsigpvBSyuHgQJlqj1C iQTijT9KcZIlsvKqmtQd68y9O2PdN0tPEpAT+sR5TRPO4uYETkkeRk3AvuiWTMZnpnsRwGUJI9U aqLE9j/RpYht+RRJjqXOJVw/e5APKI0+ABru1xlBG2nYwKwoRhGLvgFnOg4DD X-Google-Smtp-Source: AGHT+IGp1d6tKuN68ik3Wq98bpIlgM+VF7udjIuvf5QfIvYOgn/sSV4Axha9PfYLjXuK0ITh0YoBgw== X-Received: by 2002:a17:90b:4e88:b0:327:e9f4:4dd8 with SMTP id 98e67ed59e1d1-3281543831dmr1902032a91.10.1756532559244; Fri, 29 Aug 2025 22:42:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 23/84] target/arm: Expand syndrome parameter to raise_exception* Date: Sat, 30 Aug 2025 15:40:27 +1000 Message-ID: <20250830054128.448363-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756577462143124100 Content-Type: text/plain; charset="utf-8" Prepare for raising exceptions with 64-bit syndromes. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 6 +++--- target/arm/tcg-stubs.c | 2 +- target/arm/tcg/op_helper.c | 4 ++-- 3 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 285b338aeb..1d60a4ff7d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -304,14 +304,14 @@ FIELD(CNTHCTL, CNTPMASK, 19, 1) * and never returns because we will longjump back up to the CPU main loop. */ G_NORETURN void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el); + uint64_t syndrome, uint32_t target_el); =20 /* * Similarly, but also use unwinding to restore cpu state. */ G_NORETURN void raise_exception_ra(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_e= l, - uintptr_t ra); + uint64_t syndrome, uint32_t target_el, + uintptr_t ra); =20 /* * For AArch64, map a given EL to an index in the banked_spsr array. diff --git a/target/arm/tcg-stubs.c b/target/arm/tcg-stubs.c index aac99b2672..aeeede8066 100644 --- a/target/arm/tcg-stubs.c +++ b/target/arm/tcg-stubs.c @@ -16,7 +16,7 @@ void write_v7m_exception(CPUARMState *env, uint32_t new_e= xc) g_assert_not_reached(); } =20 -void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, +void raise_exception_ra(CPUARMState *env, uint32_t excp, uint64_t syndrome, uint32_t target_el, uintptr_t ra) { g_assert_not_reached(); diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 575e566280..46a3b911ec 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -46,7 +46,7 @@ int exception_target_el(CPUARMState *env) } =20 void raise_exception(CPUARMState *env, uint32_t excp, - uint32_t syndrome, uint32_t target_el) + uint64_t syndrome, uint32_t target_el) { CPUState *cs =3D env_cpu(env); =20 @@ -70,7 +70,7 @@ void raise_exception(CPUARMState *env, uint32_t excp, cpu_loop_exit(cs); } =20 -void raise_exception_ra(CPUARMState *env, uint32_t excp, uint32_t syndrome, +void raise_exception_ra(CPUARMState *env, uint32_t excp, uint64_t syndrome, uint32_t target_el, uintptr_t ra) { CPUState *cs =3D env_cpu(env); --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756569943; cv=none; d=zohomail.com; s=zohoarc; b=B8R3fY9q/dKAVOXjL4WsDmZcfZISCaecBmVcBhlORBbX/ZFmGfOMaTha1TW4IKC+9sK9zhoESQjeEl9bVKJKkbhayeZFiNdNn0l/fCyx52w12jkdk3Rt9Bw+nETbg2RWw/A80vkmwPRbX+Azt74jKZ7upBIct7iC4de220JHJwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569943; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RkmMxKsmWKq3Irpj/N+FmNwynILAG2P025dwAc8eVWU=; b=KeNhGGvNo9+NqPbvxwiRhSbjN6aqg7IjV+gk8eqSILOVvVlZ5QXxb9hmEvFuJGxLOi3f5sulCtGqI4JCy24P+b1bhiT9YI1AktqIIeUz2WFy22i+XvP+6n7v0jd/1DX2oQ+syKVSX7Od1RLW3A2GK1Zncgkq201Dk89w4hjA5ZQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756569943777444.523134350498; Sat, 30 Aug 2025 09:05:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvH-0004Em-Lo; Sat, 30 Aug 2025 11:55:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMP-00065y-Js for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:45 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMN-0004Dw-7h for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:45 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-b482fd89b0eso2394029a12.2 for ; Fri, 29 Aug 2025 22:42:42 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 1 + target/arm/ptw.c | 16 ++++++++++++++++ target/arm/tcg/tlb_helper.c | 12 +++++++++--- 3 files changed, 26 insertions(+), 3 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1d60a4ff7d..889669c67c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -752,6 +752,7 @@ struct ARMMMUFaultInfo { bool s1ptw; bool s1ns; bool ea; + bool dirtybit; /* FEAT_S1PIE, FEAT_S2PIE */ }; =20 /** diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 7ddae90f69..2b753b1319 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -2306,6 +2306,22 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, goto do_fault; } =20 + /* S1PIE and S2PIE both have a bit for software dirty page tracking. */ + if (access_type =3D=3D MMU_DATA_STORE && param.pie) { + /* + * For S1PIE, bit 7 is nDirty and both HA and HD are checked. + * For S2PIE, bit 7 is Dirty and only HD is checked. + */ + bool bit7 =3D extract64(attrs, 7, 1); + if (regime_is_stage2(mmu_idx) + ? !bit7 && !param.hd + : bit7 && !(param.ha && param.hd)) { + fi->type =3D ARMFault_Permission; + fi->dirtybit =3D true; + goto do_fault; + } + } + /* If FEAT_HAFDBS has made changes, update the PTE. */ if (new_descriptor !=3D descriptor) { new_descriptor =3D arm_casq_ptw(env, descriptor, new_descriptor, p= tw, fi); diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index 23c72a99f5..ae2acd6727 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -24,13 +24,13 @@ bool arm_s1_regime_using_lpae_format(CPUARMState *env, = ARMMMUIdx mmu_idx) return regime_using_lpae_format(env, mmu_idx); } =20 -static inline uint32_t merge_syn_data_abort(uint32_t template_syn, +static inline uint64_t merge_syn_data_abort(uint32_t template_syn, ARMMMUFaultInfo *fi, unsigned int target_el, bool same_el, bool is_write, int fsc) { - uint32_t syn; + uint64_t syn; =20 /* * ISV is only set for stage-2 data aborts routed to EL2 and @@ -75,6 +75,10 @@ static inline uint32_t merge_syn_data_abort(uint32_t tem= plate_syn, /* Merge the runtime syndrome with the template syndrome. */ syn |=3D template_syn; } + + /* Form ISS2 at the top of the syndrome. */ + syn |=3D (uint64_t)fi->dirtybit << 37; + return syn; } =20 @@ -176,7 +180,9 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, int target_el =3D exception_target_el(env); int current_el =3D arm_current_el(env); bool same_el; - uint32_t syn, exc, fsr, fsc; + uint32_t exc, fsr, fsc; + uint64_t syn; + /* * We know this must be a data or insn abort, and that * env->exception.syndrome contains the template syndrome set --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756574450; cv=none; d=zohomail.com; s=zohoarc; b=ZbDru3+bO8tRXrUbyFmOSMfzFqDLwn6hCM6KudoVgom1VeIEbX6qvqTDy7tki8+LD9eldYcUFIH53acvoj8sOK/nizVt2xmx2Qo3qJ0ijaLsb9anLPeTuFZjzzGQfvzqVqJYW7WBOfCSflkJItgqvhIIW8b8OMsp1h1hXJWpfIg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756574450; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=pjDdAknr01k7YxkbZX1BtFHr9eMT0hUzaWlnonFMe1U=; b=ApVER7I4Iz7OOK1EA+FqVnRmqUXQsoFdT91H3RIB+Qp2SI3hwy95b3er1QjxGga6Mkb1HgiqoX2vdyaay9x0cgjn9xteRRycnU1Fa30Js7wbN6XsoWN33a4k6kaOnc0mEOB3aH4720f0HXBMbzW7ZyPBenqUDeNjMMW0Z79y95o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756574450380813.399950895903; Sat, 30 Aug 2025 10:20:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNwf-0001QA-3g; Sat, 30 Aug 2025 11:56:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMT-00067a-Lk for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:50 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMQ-0004Eb-AC for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:48 -0400 Received: by mail-pj1-x102f.google.com with SMTP id 98e67ed59e1d1-327705d0a9bso2506632a91.0 for ; Fri, 29 Aug 2025 22:42:45 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:42:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 25/84] target/arm: Enable FEAT_S1PIE and FEAT_S2PIE on -cpu max Date: Sat, 30 Aug 2025 15:40:29 +1000 Message-ID: <20250830054128.448363-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756574452529116601 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 2 ++ docs/system/arm/emulation.rst | 2 ++ 2 files changed, 4 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index abef6a246e..76193826ce 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1253,6 +1253,8 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S1PIE, 1); /* FEAT_S1PIE */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, S2PIE, 1); /* FEAT_S2PIE */ SET_IDREG(isar, ID_AA64MMFR3, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 6b04c96c8c..94a6192fa9 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -122,6 +122,8 @@ the following architecture extensions: - FEAT_RME (Realm Management Extension) (NB: support status in QEMU is exp= erimental) - FEAT_RNG (Random number generator) - FEAT_RPRES (Increased precision of FRECPE and FRSQRTE) +- FEAT_S1PIE (Stage 1 permission indirections) +- FEAT_S2PIE (Stage 2 permission indirections) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) - FEAT_SCTLR2 (Extension to SCTLR_ELx) --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/cputlb.h | 32 ++++++++++++++++---------------- include/hw/core/cpu.h | 6 +++--- accel/tcg/cputlb.c | 30 +++++++++++++++--------------- 3 files changed, 34 insertions(+), 34 deletions(-) diff --git a/include/exec/cputlb.h b/include/exec/cputlb.h index 03ed7e2165..9bec0e7890 100644 --- a/include/exec/cputlb.h +++ b/include/exec/cputlb.h @@ -150,7 +150,7 @@ void tlb_flush_all_cpus_synced(CPUState *src_cpu); * MMU indexes. */ void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap); + MMUIdxMap idxmap); =20 /** * tlb_flush_page_by_mmuidx_all_cpus_synced: @@ -165,7 +165,7 @@ void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, * translations using the flushed TLBs. */ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap); + MMUIdxMap idxmap); =20 /** * tlb_flush_by_mmuidx: @@ -176,7 +176,7 @@ void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState = *cpu, vaddr addr, * Flush all entries from the TLB of the specified CPU, for the specified * MMU indexes. */ -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap); +void tlb_flush_by_mmuidx(CPUState *cpu, MMUIdxMap idxmap); =20 /** * tlb_flush_by_mmuidx_all_cpus_synced: @@ -189,7 +189,7 @@ void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap= ); * When this function returns, no CPUs will subsequently perform * translations using the flushed TLBs. */ -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, uint16_t idxmap); +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, MMUIdxMap idxmap); =20 /** * tlb_flush_page_bits_by_mmuidx @@ -201,11 +201,11 @@ void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cp= u, uint16_t idxmap); * Similar to tlb_flush_page_mask, but with a bitmap of indexes. */ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits); + MMUIdxMap idxmap, unsigned bits); =20 /* Similarly, with broadcast and syncing. */ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr ad= dr, - uint16_t idxmap, + MMUIdxMap idxmap, unsigned bits); =20 /** @@ -220,14 +220,14 @@ void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CP= UState *cpu, vaddr addr, * comparing only the low @bits worth of each virtual page. */ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, + vaddr len, MMUIdxMap idxmap, unsigned bits); =20 /* Similarly, with broadcast and syncing. */ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, vaddr len, - uint16_t idxmap, + MMUIdxMap idxmap, unsigned bits); #else static inline void tlb_flush_page(CPUState *cpu, vaddr addr) @@ -243,42 +243,42 @@ static inline void tlb_flush_all_cpus_synced(CPUState= *src_cpu) { } static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, - vaddr addr, uint16_t idxmap) + vaddr addr, MMUIdxMap idxmap) { } =20 -static inline void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +static inline void tlb_flush_by_mmuidx(CPUState *cpu, MMUIdxMap idxmap) { } static inline void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxma= p) + MMUIdxMap idxm= ap) { } static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu, - uint16_t idxmap) + MMUIdxMap idxmap) { } static inline void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, + MMUIdxMap idxmap, unsigned bits) { } static inline void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bi= ts) + MMUIdxMap idxmap, unsigned b= its) { } static inline void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, + vaddr len, MMUIdxMap idxmap, unsigned bits) { } static inline void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *cpu, vaddr addr, vaddr len, - uint16_t idxm= ap, + MMUIdxMap idx= map, unsigned bits) { } diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5eaf41a566..1153cadb70 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -198,10 +198,10 @@ struct CPUClass { }; =20 /* - * Fix the number of mmu modes to 16, which is also the maximum - * supported by the softmmu tlb api. + * Fix the number of mmu modes to 16. */ #define NB_MMU_MODES 16 +typedef uint16_t MMUIdxMap; =20 /* Use a fully associative victim tlb of 8 entries. */ #define CPU_VTLB_SIZE 8 @@ -306,7 +306,7 @@ typedef struct CPUTLBCommon { * mmu_idx N since the last time that mmu_idx was flushed. * Protected by tlb_c.lock. */ - uint16_t dirty; + MMUIdxMap dirty; /* * Statistics. These are not lock protected, but are read and * written atomically. This allows the monitor to print a snapshot diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 87e14bde4f..d324f33339 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -370,8 +370,8 @@ static void flush_all_helper(CPUState *src, run_on_cpu_= func fn, =20 static void tlb_flush_by_mmuidx_async_work(CPUState *cpu, run_on_cpu_data = data) { - uint16_t asked =3D data.host_int; - uint16_t all_dirty, work, to_clean; + MMUIdxMap asked =3D data.host_int; + MMUIdxMap all_dirty, work, to_clean; int64_t now =3D get_clock_realtime(); =20 assert_cpu_is_self(cpu); @@ -408,7 +408,7 @@ static void tlb_flush_by_mmuidx_async_work(CPUState *cp= u, run_on_cpu_data data) } } =20 -void tlb_flush_by_mmuidx(CPUState *cpu, uint16_t idxmap) +void tlb_flush_by_mmuidx(CPUState *cpu, MMUIdxMap idxmap) { tlb_debug("mmu_idx: 0x%" PRIx16 "\n", idxmap); =20 @@ -422,7 +422,7 @@ void tlb_flush(CPUState *cpu) tlb_flush_by_mmuidx(cpu, ALL_MMUIDX_BITS); } =20 -void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, uint16_t idxma= p) +void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *src_cpu, MMUIdxMap idxm= ap) { const run_on_cpu_func fn =3D tlb_flush_by_mmuidx_async_work; =20 @@ -531,7 +531,7 @@ static void tlb_flush_page_locked(CPUState *cpu, int mi= dx, vaddr page) */ static void tlb_flush_page_by_mmuidx_async_0(CPUState *cpu, vaddr addr, - uint16_t idxmap) + MMUIdxMap idxmap) { int mmu_idx; =20 @@ -570,14 +570,14 @@ static void tlb_flush_page_by_mmuidx_async_1(CPUState= *cpu, { vaddr addr_and_idxmap =3D data.target_ptr; vaddr addr =3D addr_and_idxmap & TARGET_PAGE_MASK; - uint16_t idxmap =3D addr_and_idxmap & ~TARGET_PAGE_MASK; + MMUIdxMap idxmap =3D addr_and_idxmap & ~TARGET_PAGE_MASK; =20 tlb_flush_page_by_mmuidx_async_0(cpu, addr, idxmap); } =20 typedef struct { vaddr addr; - uint16_t idxmap; + MMUIdxMap idxmap; } TLBFlushPageByMMUIdxData; =20 /** @@ -599,7 +599,7 @@ static void tlb_flush_page_by_mmuidx_async_2(CPUState *= cpu, g_free(d); } =20 -void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, uint16_t idxmap) +void tlb_flush_page_by_mmuidx(CPUState *cpu, vaddr addr, MMUIdxMap idxmap) { tlb_debug("addr: %016" VADDR_PRIx " mmu_idx:%" PRIx16 "\n", addr, idxm= ap); =20 @@ -618,7 +618,7 @@ void tlb_flush_page(CPUState *cpu, vaddr addr) =20 void tlb_flush_page_by_mmuidx_all_cpus_synced(CPUState *src_cpu, vaddr addr, - uint16_t idxmap) + MMUIdxMap idxmap) { tlb_debug("addr: %016" VADDR_PRIx " mmu_idx:%"PRIx16"\n", addr, idxmap= ); =20 @@ -715,8 +715,8 @@ static void tlb_flush_range_locked(CPUState *cpu, int m= idx, typedef struct { vaddr addr; vaddr len; - uint16_t idxmap; - uint16_t bits; + MMUIdxMap idxmap; + unsigned bits; } TLBFlushRangeData; =20 static void tlb_flush_range_by_mmuidx_async_0(CPUState *cpu, @@ -766,7 +766,7 @@ static void tlb_flush_range_by_mmuidx_async_1(CPUState = *cpu, } =20 void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr addr, - vaddr len, uint16_t idxmap, + vaddr len, MMUIdxMap idxmap, unsigned bits) { TLBFlushRangeData d; @@ -797,7 +797,7 @@ void tlb_flush_range_by_mmuidx(CPUState *cpu, vaddr add= r, } =20 void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr addr, - uint16_t idxmap, unsigned bits) + MMUIdxMap idxmap, unsigned bits) { tlb_flush_range_by_mmuidx(cpu, addr, TARGET_PAGE_SIZE, idxmap, bits); } @@ -805,7 +805,7 @@ void tlb_flush_page_bits_by_mmuidx(CPUState *cpu, vaddr= addr, void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState *src_cpu, vaddr addr, vaddr len, - uint16_t idxmap, + MMUIdxMap idxmap, unsigned bits) { TLBFlushRangeData d, *p; @@ -847,7 +847,7 @@ void tlb_flush_range_by_mmuidx_all_cpus_synced(CPUState= *src_cpu, =20 void tlb_flush_page_bits_by_mmuidx_all_cpus_synced(CPUState *src_cpu, vaddr addr, - uint16_t idxmap, + MMUIdxMap idxmap, unsigned bits) { tlb_flush_range_by_mmuidx_all_cpus_synced(src_cpu, addr, TARGET_PAGE_S= IZE, --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756578160; cv=none; d=zohomail.com; s=zohoarc; b=aiIMeREmi+srOzW9EEdxW/bMdBGxKo0dOkUOVLvQLZftVatcpaE8iFKODab1RgFccKuLiFqPIqakg6UsPsxHB8hWih45xL2g4H4ZtS2FCnCbbPVpj5iXhYqTBJzQS8cz1ShwTYRwj1Tf3DbMteZ0Pm/KKJQ8UncKTaoYB5KE6Ng= ARC-Message-Signature: i=1; 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Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 7 +++++++ accel/tcg/cputlb.c | 16 ++++++++-------- tcg/aarch64/tcg-target.c.inc | 2 +- tcg/arm/tcg-target.c.inc | 2 +- 4 files changed, 17 insertions(+), 10 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 1153cadb70..bd835b07d5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -593,6 +593,13 @@ static inline CPUArchState *cpu_env(CPUState *cpu) return (CPUArchState *)(cpu + 1); } =20 +#ifdef CONFIG_TCG +static inline CPUTLBDescFast *cpu_tlb_fast(CPUState *cpu, int mmu_idx) +{ + return &cpu->neg.tlb.f[mmu_idx]; +} +#endif + typedef QTAILQ_HEAD(CPUTailQ, CPUState) CPUTailQ; extern CPUTailQ cpus_queue; =20 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index d324f33339..2a6aa01c57 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -129,7 +129,7 @@ static inline uint64_t tlb_addr_write(const CPUTLBEntry= *entry) static inline uintptr_t tlb_index(CPUState *cpu, uintptr_t mmu_idx, vaddr addr) { - uintptr_t size_mask =3D cpu->neg.tlb.f[mmu_idx].mask >> CPU_TLB_ENTRY_= BITS; + uintptr_t size_mask =3D cpu_tlb_fast(cpu, mmu_idx)->mask >> CPU_TLB_EN= TRY_BITS; =20 return (addr >> TARGET_PAGE_BITS) & size_mask; } @@ -138,7 +138,7 @@ static inline uintptr_t tlb_index(CPUState *cpu, uintpt= r_t mmu_idx, static inline CPUTLBEntry *tlb_entry(CPUState *cpu, uintptr_t mmu_idx, vaddr addr) { - return &cpu->neg.tlb.f[mmu_idx].table[tlb_index(cpu, mmu_idx, addr)]; + return &cpu_tlb_fast(cpu, mmu_idx)->table[tlb_index(cpu, mmu_idx, addr= )]; } =20 static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, @@ -292,7 +292,7 @@ static void tlb_flush_one_mmuidx_locked(CPUState *cpu, = int mmu_idx, int64_t now) { CPUTLBDesc *desc =3D &cpu->neg.tlb.d[mmu_idx]; - CPUTLBDescFast *fast =3D &cpu->neg.tlb.f[mmu_idx]; + CPUTLBDescFast *fast =3D cpu_tlb_fast(cpu, mmu_idx); =20 tlb_mmu_resize_locked(desc, fast, now); tlb_mmu_flush_locked(desc, fast); @@ -331,7 +331,7 @@ void tlb_init(CPUState *cpu) cpu->neg.tlb.c.dirty =3D 0; =20 for (i =3D 0; i < NB_MMU_MODES; i++) { - tlb_mmu_init(&cpu->neg.tlb.d[i], &cpu->neg.tlb.f[i], now); + tlb_mmu_init(&cpu->neg.tlb.d[i], cpu_tlb_fast(cpu, i), now); } } =20 @@ -342,7 +342,7 @@ void tlb_destroy(CPUState *cpu) qemu_spin_destroy(&cpu->neg.tlb.c.lock); for (i =3D 0; i < NB_MMU_MODES; i++) { CPUTLBDesc *desc =3D &cpu->neg.tlb.d[i]; - CPUTLBDescFast *fast =3D &cpu->neg.tlb.f[i]; + CPUTLBDescFast *fast =3D cpu_tlb_fast(cpu, i); =20 g_free(fast->table); g_free(desc->fulltlb); @@ -667,7 +667,7 @@ static void tlb_flush_range_locked(CPUState *cpu, int m= idx, unsigned bits) { CPUTLBDesc *d =3D &cpu->neg.tlb.d[midx]; - CPUTLBDescFast *f =3D &cpu->neg.tlb.f[midx]; + CPUTLBDescFast *f =3D cpu_tlb_fast(cpu, midx); vaddr mask =3D MAKE_64BIT_MASK(0, bits); =20 /* @@ -923,7 +923,7 @@ void tlb_reset_dirty(CPUState *cpu, uintptr_t start, ui= ntptr_t length) qemu_spin_lock(&cpu->neg.tlb.c.lock); for (mmu_idx =3D 0; mmu_idx < NB_MMU_MODES; mmu_idx++) { CPUTLBDesc *desc =3D &cpu->neg.tlb.d[mmu_idx]; - CPUTLBDescFast *fast =3D &cpu->neg.tlb.f[mmu_idx]; + CPUTLBDescFast *fast =3D cpu_tlb_fast(cpu, mmu_idx); unsigned int n =3D tlb_n_entries(fast); unsigned int i; =20 @@ -1316,7 +1316,7 @@ static bool victim_tlb_hit(CPUState *cpu, size_t mmu_= idx, size_t index, =20 if (cmp =3D=3D page) { /* Found entry in victim tlb, swap tlb and iotlb. */ - CPUTLBEntry tmptlb, *tlb =3D &cpu->neg.tlb.f[mmu_idx].table[in= dex]; + CPUTLBEntry tmptlb, *tlb =3D &cpu_tlb_fast(cpu, mmu_idx)->tabl= e[index]; =20 qemu_spin_lock(&cpu->neg.tlb.c.lock); copy_tlb_helper_locked(&tmptlb, tlb); diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 3b088b7bd9..caf79c742d 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1668,7 +1668,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->oi =3D oi; ldst->addr_reg =3D addr_reg; =20 - /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {tmp0,tmp1}. */ + /* Load CPUTLBDescFast.{mask,table} into {tmp0,tmp1}. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 8); tcg_out_insn(s, 3314, LDP, TCG_REG_TMP0, TCG_REG_TMP1, TCG_AREG0, diff --git a/tcg/arm/tcg-target.c.inc b/tcg/arm/tcg-target.c.inc index 836894b16a..4069508272 100644 --- a/tcg/arm/tcg-target.c.inc +++ b/tcg/arm/tcg-target.c.inc @@ -1420,7 +1420,7 @@ static TCGLabelQemuLdst *prepare_host_addr(TCGContext= *s, HostAddress *h, ldst->oi =3D oi; ldst->addr_reg =3D addr; =20 - /* Load cpu->neg.tlb.f[mmu_idx].{mask,table} into {r0,r1}. */ + /* Load CPUTLBDescFast.{mask,table} into {r0,r1}. */ QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, mask) !=3D 0); QEMU_BUILD_BUG_ON(offsetof(CPUTLBDescFast, table) !=3D 4); tcg_out_ldrd_8(s, COND_AL, TCG_REG_R0, TCG_AREG0, fast_off); --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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This can be encoded into fewer bits when generating TCG fast path memory references. When we changed the NB_MMU_MODES to be a global constant, rather than a per-target value, we pessimized the code generated for targets which use only a few mmu indexes. By inverting the array index, we counteract that. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 11 ++++++++++- tcg/tcg.c | 3 ++- 2 files changed, 12 insertions(+), 2 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index bd835b07d5..23eb849a9b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -594,9 +594,18 @@ static inline CPUArchState *cpu_env(CPUState *cpu) } =20 #ifdef CONFIG_TCG +/* + * Invert the index order of the CPUTLBDescFast array so that lower + * mmu_idx have offsets from env with smaller magnitude. + */ +static inline int mmuidx_to_fast_index(int mmu_idx) +{ + return NB_MMU_MODES - 1 - mmu_idx; +} + static inline CPUTLBDescFast *cpu_tlb_fast(CPUState *cpu, int mmu_idx) { - return &cpu->neg.tlb.f[mmu_idx]; + return &cpu->neg.tlb.f[mmuidx_to_fast_index(mmu_idx)]; } #endif =20 diff --git a/tcg/tcg.c b/tcg/tcg.c index afac55a203..294762c283 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -425,7 +425,8 @@ static uintptr_t G_GNUC_UNUSED get_jmp_target_addr(TCGC= ontext *s, int which) static int __attribute__((unused)) tlb_mask_table_ofs(TCGContext *s, int which) { - return (offsetof(CPUNegativeOffsetState, tlb.f[which]) - + int fi =3D mmuidx_to_fast_index(which); + return (offsetof(CPUNegativeOffsetState, tlb.f[fi]) - sizeof(CPUNegativeOffsetState)); } =20 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756577358; cv=none; d=zohomail.com; s=zohoarc; b=J8OTi9oILfkATA5YC6TZB9vhozfanq8bwSBJcirUCKfwDVMP12QaehV4ww4QHTtgDafcIhinD/Zm+zgibaMjpMajwXpxeixNN5r5/Ra4P6h6h7cZGf9upHOwp2X7BHonrkAX4PrCF6s1sY0eWurdmHreSB3wjY+f9OTu8zu8hi0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756577358; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=UkNyZZYFhHeil9ygYrAE1UXkAwT1+GtqIOD2Xj8zAVs=; b=CLwYvVYrwwR6QCmmZJLQVO/V51IsCibYPgv70YrLYfPA/Zrp7sPgsaNNbjLON2d8jWagH01JSIdsTUV/G0EEcA77zD9cHnXNNGbN/IpaTQyr1dmWNUHXViFOa47R/t92/r+jEsbU0YOGWdlAP4vaMW7AUDElWPLWLDynbT/h3wU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756577358307584.4837120138814; Sat, 30 Aug 2025 11:09:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvU-0005Fj-B3; Sat, 30 Aug 2025 11:55:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMd-0006BG-BV for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:59 -0400 Received: from mail-pf1-x42b.google.com ([2607:f8b0:4864:20::42b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMb-0004Hl-PT for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:42:59 -0400 Received: by mail-pf1-x42b.google.com with SMTP id d2e1a72fcca58-77201f3d389so3022545b3a.2 for ; Fri, 29 Aug 2025 22:42:56 -0700 (PDT) Received: from stoup.. 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The impetus to that original patch, "9-15 will use shorter assembler instructions when run on a x86-64 host" is now handled generically. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/hppa/cpu.h | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 11d59d11ca..672ab3750c 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -29,21 +29,21 @@ #include "qemu/interval-tree.h" #include "hw/registerfields.h" =20 -#define MMU_ABS_W_IDX 6 -#define MMU_ABS_IDX 7 -#define MMU_KERNEL_IDX 8 -#define MMU_KERNEL_P_IDX 9 -#define MMU_PL1_IDX 10 -#define MMU_PL1_P_IDX 11 -#define MMU_PL2_IDX 12 -#define MMU_PL2_P_IDX 13 -#define MMU_USER_IDX 14 -#define MMU_USER_P_IDX 15 +#define MMU_KERNEL_IDX 0 +#define MMU_KERNEL_P_IDX 1 +#define MMU_PL1_IDX 2 +#define MMU_PL1_P_IDX 3 +#define MMU_PL2_IDX 4 +#define MMU_PL2_P_IDX 5 +#define MMU_USER_IDX 6 +#define MMU_USER_P_IDX 7 +#define MMU_ABS_IDX 8 +#define MMU_ABS_W_IDX 9 =20 -#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) < MMU_KERNEL_IDX) -#define MMU_IDX_TO_PRIV(MIDX) (((MIDX) - MMU_KERNEL_IDX) / 2) -#define MMU_IDX_TO_P(MIDX) (((MIDX) - MMU_KERNEL_IDX) & 1) -#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P) + MMU_KERNEL_IDX) +#define MMU_IDX_MMU_DISABLED(MIDX) ((MIDX) >=3D MMU_ABS_IDX) +#define MMU_IDX_TO_PRIV(MIDX) ((MIDX) / 2) +#define MMU_IDX_TO_P(MIDX) ((MIDX) & 1) +#define PRIV_P_TO_MMU_IDX(PRIV, P) ((PRIV) * 2 + !!(P)) =20 #define PRIV_KERNEL 0 #define PRIV_USER 3 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570364; cv=none; d=zohomail.com; s=zohoarc; b=Wz6OCKR4pVW/pglIB8SdCBMPPbDvj+1n7i4JrMlZ7WBOUiujG/d1tn6DfCjUBCV5l5VpicRw2TZ02kJGL0cSITVXUZiLWKDD4s1+xoRKd8CxYu7ImRAcGZUiQ0nYlu03vWOuTzyO6fcDyrwK4dsIfFs5lOs+sNMBzUGsMbqxSeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570364; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=jHDom8RqSvFBhHj/9Q/rXAoVV+sGpC/X8GRYrjCGKNI=; b=Yi/LuLJJ4ua4Sh5NQgKf5s4FDQ45+/4pjEc6fyLpdaEICHGA1YQu7gWDr8SiOyNWb2N4XtIu/hI+Ao6q0hX6rycjxTZWLbMpres2n0We/BEeBkxjrglhsnw/BJuyRTvG5Ghs3o83razLOq1l1mP5phQef1/Gxqq0WPNrypVnZKc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756570364546614.1266156517573; Sat, 30 Aug 2025 09:12:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNva-0005Wq-73; Sat, 30 Aug 2025 11:55:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMe-0006Bv-R6 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:05 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMd-0004Ip-CI for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:00 -0400 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-b4cf40cd0d1so1186770a12.0 for ; Fri, 29 Aug 2025 22:42:58 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:42:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 30/84] include/exec/memopidx: Adjust for 32 mmu indexes Date: Sat, 30 Aug 2025 15:40:34 +1000 Message-ID: <20250830054128.448363-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570366308124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/exec/memopidx.h | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/include/exec/memopidx.h b/include/exec/memopidx.h index eb7f1591a3..66d9c58b3a 100644 --- a/include/exec/memopidx.h +++ b/include/exec/memopidx.h @@ -25,9 +25,10 @@ typedef uint32_t MemOpIdx; static inline MemOpIdx make_memop_idx(MemOp op, unsigned idx) { #ifdef CONFIG_DEBUG_TCG - assert(idx <=3D 15); + assert(idx <=3D 31); + assert(clz32(op) >=3D 5); #endif - return (op << 4) | idx; + return (op << 5) | idx; } =20 /** @@ -38,7 +39,7 @@ static inline MemOpIdx make_memop_idx(MemOp op, unsigned = idx) */ static inline MemOp get_memop(MemOpIdx oi) { - return oi >> 4; + return oi >> 5; } =20 /** @@ -49,7 +50,7 @@ static inline MemOp get_memop(MemOpIdx oi) */ static inline unsigned get_mmuidx(MemOpIdx oi) { - return oi & 15; + return oi & 31; } =20 #endif --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Do not yet expand NB_MMU_MODES, but widen the map type in preparation. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 2 +- accel/tcg/cputlb.c | 3 --- 2 files changed, 1 insertion(+), 4 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 23eb849a9b..fc9a2291d5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -201,7 +201,7 @@ struct CPUClass { * Fix the number of mmu modes to 16. */ #define NB_MMU_MODES 16 -typedef uint16_t MMUIdxMap; +typedef uint32_t MMUIdxMap; =20 /* Use a fully associative victim tlb of 8 entries. */ #define CPU_VTLB_SIZE 8 diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 2a6aa01c57..416aaa1040 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -89,9 +89,6 @@ */ QEMU_BUILD_BUG_ON(sizeof(vaddr) > sizeof(run_on_cpu_data)); =20 -/* We currently can't handle more than 16 bits in the MMUIDX bitmask. - */ -QEMU_BUILD_BUG_ON(NB_MMU_MODES > 16); #define ALL_MMUIDX_BITS ((1 << NB_MMU_MODES) - 1) =20 static inline size_t tlb_n_entries(CPUTLBDescFast *fast) --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570481; cv=none; d=zohomail.com; s=zohoarc; b=XvjW4nbiYpgqeI0cfiHGMQFtidQ9HVkzFs2+vdbS7eA4j/hIXiwnZLFR+VB6oHNP9oRsBq0VxgIyNP9EjK3/gr+cq06KjSh70j17u284sGGx2DaE0y0CXB7PBBP/7IAYuGfWLLTlmKEo4Df/blgidh9GUQxI7L6JhpoPLLXzYaw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570481; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qovqzRdEnWmwWpu7gmXpNFgcc0fRolQB4M5vKpVvG0g=; b=E7vHkWeyJP+IticKj+px4Wedd9x1p1L6/wMiFr02EMafzeWfAMXDd2V+kJ6b8PsCfA7SGHgtuNt48I/YGS54dLp6KK11TGCVHx1JkwNORwKx+TT9LsrAlJgRixTiER7aSYWxXtKCZ6KaI/89allkID7nFFckT/ZnwN07yBaudjE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756570481392116.59380033467221; Sat, 30 Aug 2025 09:14:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvl-0006bN-45; Sat, 30 Aug 2025 11:55:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMm-0006D6-3O for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:12 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMj-0004Jx-0Y for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:07 -0400 Received: by mail-pg1-x52f.google.com with SMTP id 41be03b00d2f7-b4e84a61055so70404a12.0 for ; Fri, 29 Aug 2025 22:43:04 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:43:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v4 32/84] target/arm: Split out mmuidx.h from cpu.h Date: Sat, 30 Aug 2025 15:40:36 +1000 Message-ID: <20250830054128.448363-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570483630124100 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpu.h | 207 +----------------------------------------- target/arm/mmuidx.h | 216 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 217 insertions(+), 206 deletions(-) create mode 100644 target/arm/mmuidx.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fff2195138..8905798c8f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -33,6 +33,7 @@ #include "target/arm/multiprocessing.h" #include "target/arm/gtimer.h" #include "target/arm/cpu-sysregs.h" +#include "target/arm/mmuidx.h" =20 #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ @@ -2726,212 +2727,6 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_s= ync); =20 #define TYPE_ARM_HOST_CPU "host-" TYPE_ARM_CPU =20 -/* ARM has the following "translation regimes" (as the ARM ARM calls them): - * - * If EL3 is 64-bit: - * + NonSecure EL1 & 0 stage 1 - * + NonSecure EL1 & 0 stage 2 - * + NonSecure EL2 - * + NonSecure EL2 & 0 (ARMv8.1-VHE) - * + Secure EL1 & 0 stage 1 - * + Secure EL1 & 0 stage 2 (FEAT_SEL2) - * + Secure EL2 (FEAT_SEL2) - * + Secure EL2 & 0 (FEAT_SEL2) - * + Realm EL1 & 0 stage 1 (FEAT_RME) - * + Realm EL1 & 0 stage 2 (FEAT_RME) - * + Realm EL2 (FEAT_RME) - * + EL3 - * If EL3 is 32-bit: - * + NonSecure PL1 & 0 stage 1 - * + NonSecure PL1 & 0 stage 2 - * + NonSecure PL2 - * + Secure PL1 & 0 - * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) - * - * For QEMU, an mmu_idx is not quite the same as a translation regime beca= use: - * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_i= dxes, - * because they may differ in access permissions even if the VA->PA ma= p is - * the same - * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage= 1+2 - * translation, which means that we have one mmu_idx that deals with t= wo - * concatenated translation regimes [this sort of combined s1+2 TLB is - * architecturally permitted] - * 3. we don't need to allocate an mmu_idx to translations that we won't = be - * handling via the TLB. The only way to do a stage 1 translation with= out - * the immediate stage 2 translation is via the ATS or AT system insns, - * which can be slow-pathed and always do a page table walk. - * The only use of stage 2 translations is either as part of an s1+2 - * lookup or when loading the descriptors during a stage 1 page table = walk, - * and in both those cases we don't use the TLB. - * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" - * translation regimes, because they map reasonably well to each other - * and they can't both be active at the same time. - * 5. we want to be able to use the TLB for accesses done as part of a - * stage1 page table walk, rather than having to walk the stage2 page - * table over and over. - * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access - * Never (PAN) bit within PSTATE. - * 7. we fold together most secure and non-secure regimes for A-profile, - * because there are no banked system registers for aarch64, so the - * process of switching between secure and non-secure is - * already heavyweight. - * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, - * because both are in use simultaneously for Secure EL2. - * - * This gives us the following list of cases: - * - * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) - * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) - * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) - * EL0 EL2&0 - * EL2 EL2&0 - * EL2 EL2&0 +PAN - * EL2 (aka NS PL2) - * EL3 (aka AArch32 S PL1 PL1&0) - * AArch32 S PL0 PL1&0 (we call this EL30_0) - * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) - * Stage2 Secure - * Stage2 NonSecure - * plus one TLB per Physical address space: S, NS, Realm, Root - * - * for a total of 16 different mmu_idx. - * - * R profile CPUs have an MPU, but can use the same set of MMU indexes - * as A profile. They only need to distinguish EL0 and EL1 (and - * EL2 for cores like the Cortex-R52). - * - * M profile CPUs are rather different as they do not have a true MMU. - * They have the following different MMU indexes: - * User - * Privileged - * User, execution priority negative (ie the MPU HFNMIENA bit may apply) - * Privileged, execution priority negative (ditto) - * If the CPU supports the v8M Security Extension then there are also: - * Secure User - * Secure Privileged - * Secure User, execution priority negative - * Secure Privileged, execution priority negative - * - * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code - * are not quite the same -- different CPU types (most notably M profile - * vs A/R profile) would like to use MMU indexes with different semantics, - * but since we don't ever need to use all of those in a single CPU we - * can avoid having to set NB_MMU_MODES to "total number of A profile MMU - * modes + total number of M profile MMU modes". The lower bits of - * ARMMMUIdx are the core TLB mmu index, and the higher bits are always - * the same for any particular CPU. - * Variables of type ARMMUIdx are always full values, and the core - * index values are in variables of type 'int'. - * - * Our enumeration includes at the end some entries which are not "true" - * mmu_idx values in that they don't have corresponding TLBs and are only - * valid for doing slow path page table walks. - * - * The constant names here are patterned after the general style of the na= mes - * of the AT/ATS operations. - * The values used are carefully arranged to make mmu_idx =3D> EL lookup e= asy. - * For M profile we arrange them to have a bit for priv, a bit for negpri - * and a bit for secure. - */ -#define ARM_MMU_IDX_A 0x10 /* A profile */ -#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ -#define ARM_MMU_IDX_M 0x40 /* M profile */ - -/* Meanings of the bits for M profile mmu idx values */ -#define ARM_MMU_IDX_M_PRIV 0x1 -#define ARM_MMU_IDX_M_NEGPRI 0x2 -#define ARM_MMU_IDX_M_S 0x4 /* Secure */ - -#define ARM_MMU_IDX_TYPE_MASK \ - (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) -#define ARM_MMU_IDX_COREIDX_MASK 0xf - -typedef enum ARMMMUIdx { - /* - * A-profile. - */ - ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1_PAN =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2_PAN =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, - ARMMMUIdx_E30_0 =3D 8 | ARM_MMU_IDX_A, - ARMMMUIdx_E30_3_PAN =3D 9 | ARM_MMU_IDX_A, - - /* - * Used for second stage of an S12 page table walk, or for descriptor - * loads during first stage of an S1 page table walk. Note that both - * are in use simultaneously for SecureEL2: the security state for - * the S2 ptw is selected by the NS bit from the S1 ptw. - */ - ARMMMUIdx_Stage2_S =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 =3D 11 | ARM_MMU_IDX_A, - - /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S =3D 12 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS =3D 13 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_Root =3D 14 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_Realm =3D 15 | ARM_MMU_IDX_A, - - /* - * These are not allocated TLBs and are used only for AT system - * instructions or for the first stage of an S12 page table walk. - */ - ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, - ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, - - /* - * M-profile. - */ - ARMMMUIdx_MUser =3D ARM_MMU_IDX_M, - ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, - ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, - ARMMMUIdx_MPrivNegPri =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, - ARMMMUIdx_MSUser =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, - ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, - ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, - ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, -} ARMMMUIdx; - -/* - * Bit macros for the core-mmu-index values for each index, - * for use when calling tlb_flush_by_mmuidx() and friends. - */ -#define TO_CORE_BIT(NAME) \ - ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) - -typedef enum ARMMMUIdxBit { - TO_CORE_BIT(E10_0), - TO_CORE_BIT(E20_0), - TO_CORE_BIT(E10_1), - TO_CORE_BIT(E10_1_PAN), - TO_CORE_BIT(E2), - TO_CORE_BIT(E20_2), - TO_CORE_BIT(E20_2_PAN), - TO_CORE_BIT(E3), - TO_CORE_BIT(E30_0), - TO_CORE_BIT(E30_3_PAN), - TO_CORE_BIT(Stage2), - TO_CORE_BIT(Stage2_S), - - TO_CORE_BIT(MUser), - TO_CORE_BIT(MPriv), - TO_CORE_BIT(MUserNegPri), - TO_CORE_BIT(MPrivNegPri), - TO_CORE_BIT(MSUser), - TO_CORE_BIT(MSPriv), - TO_CORE_BIT(MSUserNegPri), - TO_CORE_BIT(MSPrivNegPri), -} ARMMMUIdxBit; - -#undef TO_CORE_BIT - -#define MMU_USER_IDX 0 - /* Indexes used when registering address spaces with cpu_address_space_ini= t */ typedef enum ARMASIdx { ARMASIdx_NS =3D 0, diff --git a/target/arm/mmuidx.h b/target/arm/mmuidx.h new file mode 100644 index 0000000000..5b9b4bc84f --- /dev/null +++ b/target/arm/mmuidx.h @@ -0,0 +1,216 @@ +/* + * QEMU Arm software mmu index definitions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_ARM_MMUIDX_H +#define TARGET_ARM_MMUIDX_H + +/* + * Arm has the following "translation regimes" (as the Arm ARM calls them): + * + * If EL3 is 64-bit: + * + NonSecure EL1 & 0 stage 1 + * + NonSecure EL1 & 0 stage 2 + * + NonSecure EL2 + * + NonSecure EL2 & 0 (ARMv8.1-VHE) + * + Secure EL1 & 0 stage 1 + * + Secure EL1 & 0 stage 2 (FEAT_SEL2) + * + Secure EL2 (FEAT_SEL2) + * + Secure EL2 & 0 (FEAT_SEL2) + * + Realm EL1 & 0 stage 1 (FEAT_RME) + * + Realm EL1 & 0 stage 2 (FEAT_RME) + * + Realm EL2 (FEAT_RME) + * + EL3 + * If EL3 is 32-bit: + * + NonSecure PL1 & 0 stage 1 + * + NonSecure PL1 & 0 stage 2 + * + NonSecure PL2 + * + Secure PL1 & 0 + * (reminder: for 32 bit EL3, Secure PL1 is *EL3*, not EL1.) + * + * For QEMU, an mmu_idx is not quite the same as a translation regime beca= use: + * 1. we need to split the "EL1 & 0" and "EL2 & 0" regimes into two mmu_i= dxes, + * because they may differ in access permissions even if the VA->PA ma= p is + * the same + * 2. we want to cache in our TLB the full VA->IPA->PA lookup for a stage= 1+2 + * translation, which means that we have one mmu_idx that deals with t= wo + * concatenated translation regimes [this sort of combined s1+2 TLB is + * architecturally permitted] + * 3. we don't need to allocate an mmu_idx to translations that we won't = be + * handling via the TLB. The only way to do a stage 1 translation with= out + * the immediate stage 2 translation is via the ATS or AT system insns, + * which can be slow-pathed and always do a page table walk. + * The only use of stage 2 translations is either as part of an s1+2 + * lookup or when loading the descriptors during a stage 1 page table = walk, + * and in both those cases we don't use the TLB. + * 4. we can also safely fold together the "32 bit EL3" and "64 bit EL3" + * translation regimes, because they map reasonably well to each other + * and they can't both be active at the same time. + * 5. we want to be able to use the TLB for accesses done as part of a + * stage1 page table walk, rather than having to walk the stage2 page + * table over and over. + * 6. we need separate EL1/EL2 mmu_idx for handling the Privileged Access + * Never (PAN) bit within PSTATE. + * 7. we fold together most secure and non-secure regimes for A-profile, + * because there are no banked system registers for aarch64, so the + * process of switching between secure and non-secure is + * already heavyweight. + * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, + * because both are in use simultaneously for Secure EL2. + * + * This gives us the following list of cases: + * + * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) + * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) + * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) + * EL0 EL2&0 + * EL2 EL2&0 + * EL2 EL2&0 +PAN + * EL2 (aka NS PL2) + * EL3 (aka AArch32 S PL1 PL1&0) + * AArch32 S PL0 PL1&0 (we call this EL30_0) + * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) + * Stage2 Secure + * Stage2 NonSecure + * plus one TLB per Physical address space: S, NS, Realm, Root + * + * for a total of 16 different mmu_idx. + * + * R profile CPUs have an MPU, but can use the same set of MMU indexes + * as A profile. They only need to distinguish EL0 and EL1 (and + * EL2 for cores like the Cortex-R52). + * + * M profile CPUs are rather different as they do not have a true MMU. + * They have the following different MMU indexes: + * User + * Privileged + * User, execution priority negative (ie the MPU HFNMIENA bit may apply) + * Privileged, execution priority negative (ditto) + * If the CPU supports the v8M Security Extension then there are also: + * Secure User + * Secure Privileged + * Secure User, execution priority negative + * Secure Privileged, execution priority negative + * + * The ARMMMUIdx and the mmu index value used by the core QEMU TLB code + * are not quite the same -- different CPU types (most notably M profile + * vs A/R profile) would like to use MMU indexes with different semantics, + * but since we don't ever need to use all of those in a single CPU we + * can avoid having to set NB_MMU_MODES to "total number of A profile MMU + * modes + total number of M profile MMU modes". The lower bits of + * ARMMMUIdx are the core TLB mmu index, and the higher bits are always + * the same for any particular CPU. + * Variables of type ARMMUIdx are always full values, and the core + * index values are in variables of type 'int'. + * + * Our enumeration includes at the end some entries which are not "true" + * mmu_idx values in that they don't have corresponding TLBs and are only + * valid for doing slow path page table walks. + * + * The constant names here are patterned after the general style of the na= mes + * of the AT/ATS operations. + * The values used are carefully arranged to make mmu_idx =3D> EL lookup e= asy. + * For M profile we arrange them to have a bit for priv, a bit for negpri + * and a bit for secure. + */ +#define ARM_MMU_IDX_A 0x10 /* A profile */ +#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ +#define ARM_MMU_IDX_M 0x40 /* M profile */ + +/* Meanings of the bits for M profile mmu idx values */ +#define ARM_MMU_IDX_M_PRIV 0x1 +#define ARM_MMU_IDX_M_NEGPRI 0x2 +#define ARM_MMU_IDX_M_S 0x4 /* Secure */ + +#define ARM_MMU_IDX_TYPE_MASK \ + (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) +#define ARM_MMU_IDX_COREIDX_MASK 0xf + +typedef enum ARMMMUIdx { + /* + * A-profile. + */ + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN =3D 4 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, + ARMMMUIdx_E30_0 =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_E30_3_PAN =3D 9 | ARM_MMU_IDX_A, + + /* + * Used for second stage of an S12 page table walk, or for descriptor + * loads during first stage of an S1 page table walk. Note that both + * are in use simultaneously for SecureEL2: the security state for + * the S2 ptw is selected by the NS bit from the S1 ptw. + */ + ARMMMUIdx_Stage2_S =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 11 | ARM_MMU_IDX_A, + + /* TLBs with 1-1 mapping to the physical address spaces. */ + ARMMMUIdx_Phys_S =3D 12 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 13 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root =3D 14 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm =3D 15 | ARM_MMU_IDX_A, + + /* + * These are not allocated TLBs and are used only for AT system + * instructions or for the first stage of an S12 page table walk. + */ + ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, + + /* + * M-profile. + */ + ARMMMUIdx_MUser =3D ARM_MMU_IDX_M, + ARMMMUIdx_MPriv =3D ARM_MMU_IDX_M | ARM_MMU_IDX_M_PRIV, + ARMMMUIdx_MUserNegPri =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_NEGPRI, + ARMMMUIdx_MPrivNegPri =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_NEGPRI, + ARMMMUIdx_MSUser =3D ARMMMUIdx_MUser | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSPriv =3D ARMMMUIdx_MPriv | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSUserNegPri =3D ARMMMUIdx_MUserNegPri | ARM_MMU_IDX_M_S, + ARMMMUIdx_MSPrivNegPri =3D ARMMMUIdx_MPrivNegPri | ARM_MMU_IDX_M_S, +} ARMMMUIdx; + +/* + * Bit macros for the core-mmu-index values for each index, + * for use when calling tlb_flush_by_mmuidx() and friends. + */ +#define TO_CORE_BIT(NAME) \ + ARMMMUIdxBit_##NAME =3D 1 << (ARMMMUIdx_##NAME & ARM_MMU_IDX_COREIDX_M= ASK) + +typedef enum ARMMMUIdxBit { + TO_CORE_BIT(E10_0), + TO_CORE_BIT(E20_0), + TO_CORE_BIT(E10_1), + TO_CORE_BIT(E10_1_PAN), + TO_CORE_BIT(E2), + TO_CORE_BIT(E20_2), + TO_CORE_BIT(E20_2_PAN), + TO_CORE_BIT(E3), + TO_CORE_BIT(E30_0), + TO_CORE_BIT(E30_3_PAN), + TO_CORE_BIT(Stage2), + TO_CORE_BIT(Stage2_S), + + TO_CORE_BIT(MUser), + TO_CORE_BIT(MPriv), + TO_CORE_BIT(MUserNegPri), + TO_CORE_BIT(MPrivNegPri), + TO_CORE_BIT(MSUser), + TO_CORE_BIT(MSPriv), + TO_CORE_BIT(MSUserNegPri), + TO_CORE_BIT(MSPrivNegPri), +} ARMMMUIdxBit; + +#undef TO_CORE_BIT + +#define MMU_USER_IDX 0 + +#endif /* TARGET_ARM_MMUIDX_H */ --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570544; cv=none; d=zohomail.com; s=zohoarc; b=g3UGP9cUDP3hNm9uIxMyBaO45BF8yFGp7Caf8LbUPtFPoJy1/E+nM3Ek3/VPViMt2bEwhKI82A352ianci7vQ7pSnpBhI85B+V6PCar6h0nIirWH3ygMYHXBZZlE7WalD4vaDx3dGQxkbyvFZ7X9Sc+cVVaUIh9+2zHgY9geb08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570544; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=YPGwh6o6SvhA1KuYokTgQ6cJwOxJqF2whfCubD5N/CU=; b=OOlYKFSjLRW8zkCKYeEjfn1/UIrp8kXjyncPfAIIVzYlDX02/gXhsOdFi2Rv96AJ9CM516CrQPHtbc2O73swxbuS4ojEbdnCsmjqx7sWRjAuiLJ/8dwAcTfM4XD18Qmj3zGx67M2ecZF+e6SfimnKZCLnFkEg48HhFHyw3oi3jU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756570544301925.6148317644706; Sat, 30 Aug 2025 09:15:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNvo-00071T-Ta; Sat, 30 Aug 2025 11:55:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMo-0006D9-05 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:12 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMl-0004KS-Rw for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:09 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d9443c01a7336-2487a60d649so31765905ad.2 for ; Fri, 29 Aug 2025 22:43:07 -0700 (PDT) Received: from stoup.. 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Begin with the access EL. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 3 +-- target/arm/mmuidx-internal.h | 29 +++++++++++++++++++++++++ target/arm/helper.c | 27 ------------------------ target/arm/mmuidx.c | 41 ++++++++++++++++++++++++++++++++++++ target/arm/meson.build | 7 +++++- 5 files changed, 77 insertions(+), 30 deletions(-) create mode 100644 target/arm/mmuidx-internal.h create mode 100644 target/arm/mmuidx.c diff --git a/target/arm/internals.h b/target/arm/internals.h index 889669c67c..4e0c057a8c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -34,6 +34,7 @@ #include "system/memory.h" #include "syndrome.h" #include "cpu-features.h" +#include "mmuidx-internal.h" =20 /* register banks for CPU modes */ #define BANK_USRSYS 0 @@ -984,8 +985,6 @@ static inline ARMMMUIdx core_to_aa64_mmu_idx(int mmu_id= x) return mmu_idx | ARM_MMU_IDX_A; } =20 -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx); - /* Return the MMU index for a v7M CPU in the specified security state */ ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate); =20 diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h new file mode 100644 index 0000000000..29bba4ecb5 --- /dev/null +++ b/target/arm/mmuidx-internal.h @@ -0,0 +1,29 @@ +/* + * QEMU Arm software mmu index internal definitions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef TARGET_ARM_MMUIDX_INTERNAL_H +#define TARGET_ARM_MMUIDX_INTERNAL_H + +#include "mmuidx.h" +#include "tcg/debug-assert.h" +#include "hw/registerfields.h" + + +FIELD(MMUIDXINFO, EL, 0, 2) +FIELD(MMUIDXINFO, ELVALID, 2, 1) + +extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; + +#define arm_mmuidx_is_valid(x) ((unsigned)(x) < ARRAY_SIZE(arm_mmuidx_tab= le)) + +/* Return the exception level associated with this mmu index. */ +static inline int arm_mmu_idx_to_el(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + tcg_debug_assert(FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, ELVALID= )); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, EL); +} + +#endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/helper.c b/target/arm/helper.c index fc95010727..eaa6766a36 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9789,33 +9789,6 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 0; } =20 -/* Return the exception level we're running at if this is our mmu_idx */ -int arm_mmu_idx_to_el(ARMMMUIdx mmu_idx) -{ - if (mmu_idx & ARM_MMU_IDX_M) { - return mmu_idx & ARM_MMU_IDX_M_PRIV; - } - - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E30_0: - return 0; - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - return 1; - case ARMMMUIdx_E2: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - return 2; - case ARMMMUIdx_E3: - case ARMMMUIdx_E30_3_PAN: - return 3; - default: - g_assert_not_reached(); - } -} - #ifndef CONFIG_TCG ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) { diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c new file mode 100644 index 0000000000..309b1d68df --- /dev/null +++ b/target/arm/mmuidx.c @@ -0,0 +1,41 @@ +/* + * QEMU Arm software mmu index definitions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "mmuidx-internal.h" + + +#define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) + +const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { + /* + * A-profile. + */ + [ARMMMUIdx_E10_0] =3D EL(0), + [ARMMMUIdx_E10_1] =3D EL(1), + [ARMMMUIdx_E10_1_PAN] =3D EL(1), + + [ARMMMUIdx_E20_0] =3D EL(0), + [ARMMMUIdx_E20_2] =3D EL(2), + [ARMMMUIdx_E20_2_PAN] =3D EL(2), + + [ARMMMUIdx_E2] =3D EL(2), + + [ARMMMUIdx_E3] =3D EL(3), + [ARMMMUIdx_E30_0] =3D EL(0), + [ARMMMUIdx_E30_3_PAN] =3D EL(3), + + /* + * M-profile. + */ + [ARMMMUIdx_MUser] =3D EL(0), + [ARMMMUIdx_MPriv] =3D EL(1), + [ARMMMUIdx_MUserNegPri] =3D EL(0), + [ARMMMUIdx_MPrivNegPri] =3D EL(1), + [ARMMMUIdx_MSUser] =3D EL(0), + [ARMMMUIdx_MSPriv] =3D EL(1), + [ARMMMUIdx_MSUserNegPri] =3D EL(0), + [ARMMMUIdx_MSPrivNegPri] =3D EL(1), +}; diff --git a/target/arm/meson.build b/target/arm/meson.build index 07d9271aa4..91630a1f72 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -6,7 +6,12 @@ arm_ss.add(files( =20 arm_ss.add(when: 'TARGET_AARCH64', if_true: files( 'cpu64.c', - 'gdbstub64.c')) + 'gdbstub64.c' +)) + +arm_common_ss.add(files( + 'mmuidx.c', +)) =20 arm_system_ss =3D ss.source_set() arm_common_system_ss =3D ss.source_set() --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570002; cv=none; d=zohomail.com; s=zohoarc; b=ZpNI2ePgklt0aBt/j88BQddGeUVjnDFrM3qQhS1f06OWegsCTP+E9kz1v33mDFOY2Jo2sH8/nGpufYiXVe1QfSptPlWXGyI3RRNca7ss6zz86lm3ttpjn9WByQ7mxw10hg92GeqLxFWBuZ7zag7lyCWvGnV8ktYDe+2bthfPAoM= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 22:43:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v4 34/84] target/arm: Remove unused env argument from regime_el Date: Sat, 30 Aug 2025 15:40:38 +1000 Message-ID: <20250830054128.448363-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570003790116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 8 ++++---- target/arm/helper.c | 2 +- target/arm/ptw.c | 34 +++++++++++++++++----------------- target/arm/tcg/mte_helper.c | 2 +- 4 files changed, 23 insertions(+), 23 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4e0c057a8c..c3bce6c09b 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1074,7 +1074,7 @@ static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) } =20 /* Return the exception level which controls this address translation regi= me */ -static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline uint32_t regime_el(ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_E20_0: @@ -1128,7 +1128,7 @@ static inline bool regime_is_user(CPUARMState *env, A= RMMMUIdx mmu_idx) /* Return the SCTLR value which controls this address translation regime */ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { - return env->cp15.sctlr_el[regime_el(env, mmu_idx)]; + return env->cp15.sctlr_el[regime_el(mmu_idx)]; } =20 /* @@ -1160,13 +1160,13 @@ static inline uint64_t regime_tcr(CPUARMState *env,= ARMMMUIdx mmu_idx) v |=3D env->cp15.vtcr_el2 & VTCR_SHARED_FIELD_MASK; return v; } - return env->cp15.tcr_el[regime_el(env, mmu_idx)]; + return env->cp15.tcr_el[regime_el(mmu_idx)]; } =20 /* Return true if the translation regime is using LPAE format page tables = */ static inline bool regime_using_lpae_format(CPUARMState *env, ARMMMUIdx mm= u_idx) { - int el =3D regime_el(env, mmu_idx); + int el =3D regime_el(mmu_idx); if (el =3D=3D 2 || arm_el_is_aa64(env, el)) { return true; } diff --git a/target/arm/helper.c b/target/arm/helper.c index eaa6766a36..b88d1573ae 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9527,7 +9527,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, ARMGranuleSize gran; ARMCPU *cpu =3D env_archcpu(env); bool stage2 =3D regime_is_stage2(mmu_idx); - int r_el =3D regime_el(env, mmu_idx); + int r_el =3D regime_el(mmu_idx); =20 if (!regime_has_2_ranges(mmu_idx)) { select =3D 0; diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 2b753b1319..5adea5cd65 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -232,9 +232,9 @@ static uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx= mmu_idx, int ttbrn) return env->cp15.vsttbr_el2; } if (ttbrn =3D=3D 0) { - return env->cp15.ttbr0_el[regime_el(env, mmu_idx)]; + return env->cp15.ttbr0_el[regime_el(mmu_idx)]; } else { - return env->cp15.ttbr1_el[regime_el(env, mmu_idx)]; + return env->cp15.ttbr1_el[regime_el(mmu_idx)]; } } =20 @@ -1023,7 +1023,7 @@ static bool get_phys_addr_v5(CPUARMState *env, S1Tran= slate *ptw, } type =3D (desc & 3); domain =3D (desc >> 5) & 0x0f; - if (regime_el(env, ptw->in_mmu_idx) =3D=3D 1) { + if (regime_el(ptw->in_mmu_idx) =3D=3D 1) { dacr =3D env->cp15.dacr_ns; } else { dacr =3D env->cp15.dacr_s; @@ -1163,7 +1163,7 @@ static bool get_phys_addr_v6(CPUARMState *env, S1Tran= slate *ptw, /* Page or Section. */ domain =3D (desc >> 5) & 0x0f; } - if (regime_el(env, mmu_idx) =3D=3D 1) { + if (regime_el(mmu_idx) =3D=3D 1) { dacr =3D env->cp15.dacr_ns; } else { dacr =3D env->cp15.dacr_s; @@ -1454,7 +1454,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, xn =3D pxn || (user_rw & PAGE_WRITE); } } else if (arm_feature(env, ARM_FEATURE_V7)) { - switch (regime_el(env, mmu_idx)) { + switch (regime_el(mmu_idx)) { case 1: case 3: if (is_user) { @@ -1510,7 +1510,7 @@ static int get_S1prot_indirect(CPUARMState *env, S1Tr= anslate *ptw, /* F */ 0, /* reserved */ }; =20 - uint32_t el =3D regime_el(env, mmu_idx); + uint32_t el =3D regime_el(mmu_idx); uint64_t pir =3D env->cp15.pir_el[el]; uint64_t pire0 =3D 0; int perm; @@ -1585,7 +1585,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState= *env, uint32_t va, ARMMMUIdx mmu_idx) { uint64_t tcr =3D regime_tcr(env, mmu_idx); - uint32_t el =3D regime_el(env, mmu_idx); + uint32_t el =3D regime_el(mmu_idx); int select, tsz; bool epd, hpd; =20 @@ -1811,7 +1811,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, int addrsize, inputsize, outputsize; uint64_t tcr =3D regime_tcr(env, mmu_idx); int ap, prot; - uint32_t el =3D regime_el(env, mmu_idx); + uint32_t el =3D regime_el(mmu_idx); uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); uint64_t descriptor, new_descriptor; @@ -2259,7 +2259,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1Tr= anslate *ptw, =20 /* Index into MAIR registers for cache attributes */ attrindx =3D extract32(attrs, 2, 3); - mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + mair =3D env->cp15.mair_el[regime_el(mmu_idx)]; assert(attrindx <=3D 7); result->cacheattrs.is_s2_format =3D false; result->cacheattrs.attrs =3D extract64(mair, attrindx * 8, 8); @@ -2737,7 +2737,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, static uint32_t *regime_rbar(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t secure) { - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { return env->pmsav8.hprbar; } else { return env->pmsav8.rbar[secure]; @@ -2747,7 +2747,7 @@ static uint32_t *regime_rbar(CPUARMState *env, ARMMMU= Idx mmu_idx, static uint32_t *regime_rlar(CPUARMState *env, ARMMMUIdx mmu_idx, uint32_t secure) { - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { return env->pmsav8.hprlar; } else { return env->pmsav8.rlar[secure]; @@ -2779,7 +2779,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, uint32_t addr_page_limit =3D addr_page_base + (TARGET_PAGE_SIZE - 1); int region_counter; =20 - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { region_counter =3D cpu->pmsav8r_hdregion; } else { region_counter =3D cpu->pmsav7_dregion; @@ -2905,7 +2905,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 1; } =20 - if (regime_el(env, mmu_idx) =3D=3D 2) { + if (regime_el(mmu_idx) =3D=3D 2) { result->f.prot =3D simple_ap_to_rw_prot_is_user(ap, mmu_idx !=3D ARMMMUIdx_E2); } else { @@ -2914,7 +2914,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, =20 if (!arm_feature(env, ARM_FEATURE_M)) { uint8_t attrindx =3D extract32(matched_rlar, 1, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; + uint64_t mair =3D env->cp15.mair_el[regime_el(mmu_idx)]; uint8_t sh =3D extract32(matched_rlar, 3, 2); =20 if (regime_sctlr(env, mmu_idx) & SCTLR_WXN && @@ -2922,7 +2922,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, xn =3D 0x1; } =20 - if ((regime_el(env, mmu_idx) =3D=3D 1) && + if ((regime_el(mmu_idx) =3D=3D 1) && regime_sctlr(env, mmu_idx) & SCTLR_UWXN && ap =3D=3D 0x1) { pxn =3D 0x1; } @@ -3407,7 +3407,7 @@ static bool get_phys_addr_disabled(CPUARMState *env, break; =20 default: - r_el =3D regime_el(env, mmu_idx); + r_el =3D regime_el(mmu_idx); if (arm_el_is_aa64(env, r_el)) { int pamax =3D arm_pamax(env_archcpu(env)); uint64_t tcr =3D env->cp15.tcr_el[r_el]; @@ -3659,7 +3659,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, */ if (address < 0x02000000 && mmu_idx !=3D ARMMMUIdx_Stage2 && !arm_feature(env, ARM_FEATURE_V8)) { - if (regime_el(env, mmu_idx) =3D=3D 3) { + if (regime_el(mmu_idx) =3D=3D 3) { address +=3D env->cp15.fcseidr_s; } else { address +=3D env->cp15.fcseidr_ns; diff --git a/target/arm/tcg/mte_helper.c b/target/arm/tcg/mte_helper.c index 0efc18a181..ed30026b7d 100644 --- a/target/arm/tcg/mte_helper.c +++ b/target/arm/tcg/mte_helper.c @@ -604,7 +604,7 @@ void mte_check_fail(CPUARMState *env, uint32_t desc, int el, reg_el, tcf; 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Fri, 29 Aug 2025 22:43:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 35/84] target/arm: Convert regime_el from switch to table Date: Sat, 30 Aug 2025 15:40:39 +1000 Message-ID: <20250830054128.448363-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756572499141116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 35 ---------------------------- target/arm/mmuidx-internal.h | 13 +++++++++++ target/arm/mmuidx.c | 44 +++++++++++++++++++++--------------- 3 files changed, 39 insertions(+), 53 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index c3bce6c09b..13fc5a2ca0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1073,41 +1073,6 @@ static inline bool regime_is_stage2(ARMMMUIdx mmu_id= x) return mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Sta= ge2_S; } =20 -/* Return the exception level which controls this address translation regi= me */ -static inline uint32_t regime_el(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_Stage2: - case ARMMMUIdx_Stage2_S: - case ARMMMUIdx_E2: - return 2; - case ARMMMUIdx_E3: - case ARMMMUIdx_E30_0: - case ARMMMUIdx_E30_3_PAN: - return 3; - case ARMMMUIdx_E10_0: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_MPrivNegPri: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MPriv: - case ARMMMUIdx_MUser: - case ARMMMUIdx_MSPrivNegPri: - case ARMMMUIdx_MSUserNegPri: - case ARMMMUIdx_MSPriv: - case ARMMMUIdx_MSUser: - return 1; - default: - g_assert_not_reached(); - } -} - static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index 29bba4ecb5..d8d64a14d6 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -13,6 +13,8 @@ =20 FIELD(MMUIDXINFO, EL, 0, 2) FIELD(MMUIDXINFO, ELVALID, 2, 1) +FIELD(MMUIDXINFO, REL, 3, 2) +FIELD(MMUIDXINFO, RELVALID, 5, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -26,4 +28,15 @@ static inline int arm_mmu_idx_to_el(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, EL); } =20 +/* + * Return the exception level for the address translation regime + * associated with this mmu index. + */ +static inline uint32_t regime_el(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + tcg_debug_assert(FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, RELVALI= D)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, REL); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 309b1d68df..6dfefa56c2 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -8,34 +8,42 @@ =20 =20 #define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) +#define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* * A-profile. */ - [ARMMMUIdx_E10_0] =3D EL(0), - [ARMMMUIdx_E10_1] =3D EL(1), - [ARMMMUIdx_E10_1_PAN] =3D EL(1), + [ARMMMUIdx_E10_0] =3D EL(0) | REL(1), + [ARMMMUIdx_E10_1] =3D EL(1) | REL(1), + [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1), =20 - [ARMMMUIdx_E20_0] =3D EL(0), - [ARMMMUIdx_E20_2] =3D EL(2), - [ARMMMUIdx_E20_2_PAN] =3D EL(2), + [ARMMMUIdx_E20_0] =3D EL(0) | REL(2), + [ARMMMUIdx_E20_2] =3D EL(2) | REL(2), + [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2), =20 - [ARMMMUIdx_E2] =3D EL(2), + [ARMMMUIdx_E2] =3D EL(2) | REL(2), =20 - [ARMMMUIdx_E3] =3D EL(3), - [ARMMMUIdx_E30_0] =3D EL(0), - [ARMMMUIdx_E30_3_PAN] =3D EL(3), + [ARMMMUIdx_E3] =3D EL(3) | REL(3), + [ARMMMUIdx_E30_0] =3D EL(0) | REL(3), + [ARMMMUIdx_E30_3_PAN] =3D EL(3) | REL(3), + + [ARMMMUIdx_Stage2_S] =3D REL(2), + [ARMMMUIdx_Stage2] =3D REL(2), + + [ARMMMUIdx_Stage1_E0] =3D REL(1), + [ARMMMUIdx_Stage1_E1] =3D REL(1), + [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1), =20 /* * M-profile. */ - [ARMMMUIdx_MUser] =3D EL(0), - [ARMMMUIdx_MPriv] =3D EL(1), - [ARMMMUIdx_MUserNegPri] =3D EL(0), - [ARMMMUIdx_MPrivNegPri] =3D EL(1), - [ARMMMUIdx_MSUser] =3D EL(0), - [ARMMMUIdx_MSPriv] =3D EL(1), - [ARMMMUIdx_MSUserNegPri] =3D EL(0), - [ARMMMUIdx_MSPrivNegPri] =3D EL(1), + [ARMMMUIdx_MUser] =3D EL(0) | REL(1), + [ARMMMUIdx_MPriv] =3D EL(1) | REL(1), + [ARMMMUIdx_MUserNegPri] =3D EL(0) | REL(1), + [ARMMMUIdx_MPrivNegPri] =3D EL(1) | REL(1), + [ARMMMUIdx_MSUser] =3D EL(0) | REL(1), + [ARMMMUIdx_MSPriv] =3D EL(1) | REL(1), + [ARMMMUIdx_MSUserNegPri] =3D EL(0) | REL(1), + [ARMMMUIdx_MSPrivNegPri] =3D EL(1) | REL(1), }; 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(The - * correct return value for ARMMMUIdx_E3 would be different for - * that case, so we can't just make the function return the - * correct value anyway; we would need an extra "bool e3_is_aarch32" - * argument which all the current callsites would pass as 'false'.) - */ -static inline bool regime_has_2_ranges(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E10_1: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E20_2: - case ARMMMUIdx_E20_2_PAN: - return true; - default: - return false; - } -} - static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) { switch (mmu_idx) { diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index d8d64a14d6..f03a2ab94c 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -15,6 +15,7 @@ FIELD(MMUIDXINFO, EL, 0, 2) FIELD(MMUIDXINFO, ELVALID, 2, 1) FIELD(MMUIDXINFO, REL, 3, 2) FIELD(MMUIDXINFO, RELVALID, 5, 1) +FIELD(MMUIDXINFO, 2RANGES, 6, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -39,4 +40,20 @@ static inline uint32_t regime_el(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, REL); } =20 +/* + * Return true if this address translation regime has two ranges. + * Note that this will not return the correct answer for AArch32 + * Secure PL1&0 (i.e. mmu indexes E3, E30_0, E30_3_PAN), but it is + * never called from a context where EL3 can be AArch32. (The + * correct return value for ARMMMUIdx_E3 would be different for + * that case, so we can't just make the function return the + * correct value anyway; we would need an extra "bool e3_is_aarch32" + * argument which all the current callsites would pass as 'false'.) + */ +static inline bool regime_has_2_ranges(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, 2RANGES); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 6dfefa56c2..f880d21606 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -9,18 +9,19 @@ =20 #define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) #define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) +#define R2 R_MMUIDXINFO_2RANGES_MASK =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* * A-profile. */ - [ARMMMUIdx_E10_0] =3D EL(0) | REL(1), - [ARMMMUIdx_E10_1] =3D EL(1) | REL(1), - [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1), + [ARMMMUIdx_E10_0] =3D EL(0) | REL(1) | R2, + [ARMMMUIdx_E10_1] =3D EL(1) | REL(1) | R2, + [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1) | R2, =20 - [ARMMMUIdx_E20_0] =3D EL(0) | REL(2), - [ARMMMUIdx_E20_2] =3D EL(2) | REL(2), - [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2), + [ARMMMUIdx_E20_0] =3D EL(0) | REL(2) | R2, + [ARMMMUIdx_E20_2] =3D EL(2) | REL(2) | R2, + [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2) | R2, =20 [ARMMMUIdx_E2] =3D EL(2) | REL(2), =20 @@ -31,9 +32,9 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { [ARMMMUIdx_Stage2_S] =3D REL(2), [ARMMMUIdx_Stage2] =3D REL(2), =20 - [ARMMMUIdx_Stage1_E0] =3D REL(1), - [ARMMMUIdx_Stage1_E1] =3D REL(1), - [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1), + [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2, + [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2, + [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2, =20 /* * M-profile. --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756573201; cv=none; d=zohomail.com; s=zohoarc; b=lLKMnKZMnIdvP2fEQ98fm2A4yl3FVaH2UFrxJWWqHxSvdl5F5Rxo9c1uyL0vdN1cb4bThuoX3JH3iqPz2D9WBu2BUmWOKCd4t4M6c7wVbA9DcjbjYvS5lNuZzJYDmTKlsAM6REf+k1Z8pgiYiRGUikbUr7KZB/4BFTszVXsiX/I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756573201; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=WyUpmSL2n3VZMAxXx348SkKtQF1BK17TOs08zG5lW3A=; b=ggEzd180v0gGHbrTLaWetNtu4keqHRfN2YSbnkWYgQukrjIHqY9oGV/khKRzCSwWwQl97ahrGtuP8PKHQwTkWcKQCuPEhJQaZq2cj6qE3XAUYBy5UFevb4w1jA6cattPL8MFIMgbwGH/cjqOfqJmT/T7pWkY0T+dwDQg5snbzjI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756573201351248.94776872689386; Sat, 30 Aug 2025 10:00:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNwe-0001L0-HP; Sat, 30 Aug 2025 11:56:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEMy-0006Gt-Gl for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:20 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEMw-0004Mk-HW for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:43:19 -0400 Received: by mail-pf1-x430.google.com with SMTP id d2e1a72fcca58-772301f8a4cso1456366b3a.3 for ; Fri, 29 Aug 2025 22:43:18 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:43:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v4 37/84] target/arm: Remove unused env argument from regime_is_pan Date: Sat, 30 Aug 2025 15:40:41 +1000 Message-ID: <20250830054128.448363-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756573202150116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/ptw.c | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a9f44a23cd..2ef81a00ab 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1027,7 +1027,7 @@ static inline void arm_call_el_change_hook(ARMCPU *cp= u) } } =20 -static inline bool regime_is_pan(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline bool regime_is_pan(ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_Stage1_E1_PAN: diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 5adea5cd65..a8c450d28b 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1394,10 +1394,10 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx m= mu_idx, bool is_aa64, * We make the IMPDEF choices that SCR_EL3.SIF and Realm EL2&0 * do not affect EPAN. */ - if (user_rw && regime_is_pan(env, mmu_idx)) { + if (user_rw && regime_is_pan(mmu_idx)) { prot_rw =3D 0; } else if (cpu_isar_feature(aa64_pan3, cpu) && is_aa64 && - regime_is_pan(env, mmu_idx) && + regime_is_pan(mmu_idx) && (regime_sctlr(env, mmu_idx) & SCTLR_EPAN) && !xn) { prot_rw =3D 0; } @@ -1536,7 +1536,7 @@ static int get_S1prot_indirect(CPUARMState *env, S1Tr= anslate *ptw, p_perm &=3D ~(PAGE_RWX | PAGE_GCS); u_perm &=3D ~(PAGE_RWX | PAGE_GCS); } - if ((u_perm & (PAGE_RWX | PAGE_GCS)) && regime_is_pan(env, mmu_idx= )) { + if ((u_perm & (PAGE_RWX | PAGE_GCS)) && regime_is_pan(mmu_idx)) { p_perm &=3D ~(PAGE_READ | PAGE_WRITE); } perm =3D regime_is_user(env, mmu_idx) ? u_perm : p_perm; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570552; cv=none; d=zohomail.com; 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Fri, 29 Aug 2025 22:43:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 38/84] target/arm: Convert regime_is_pan from switch to table Date: Sat, 30 Aug 2025 15:40:42 +1000 Message-ID: <20250830054128.448363-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570554339124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 13 ------------- target/arm/mmuidx-internal.h | 8 ++++++++ target/arm/mmuidx.c | 9 +++++---- 3 files changed, 13 insertions(+), 17 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2ef81a00ab..2148814835 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1027,19 +1027,6 @@ static inline void arm_call_el_change_hook(ARMCPU *c= pu) } } =20 -static inline bool regime_is_pan(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_Stage1_E1_PAN: - case ARMMMUIdx_E10_1_PAN: - case ARMMMUIdx_E20_2_PAN: - case ARMMMUIdx_E30_3_PAN: - return true; - default: - return false; - } -} - static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) { return mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Sta= ge2_S; diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index f03a2ab94c..41baf1a003 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -16,6 +16,7 @@ FIELD(MMUIDXINFO, ELVALID, 2, 1) FIELD(MMUIDXINFO, REL, 3, 2) FIELD(MMUIDXINFO, RELVALID, 5, 1) FIELD(MMUIDXINFO, 2RANGES, 6, 1) +FIELD(MMUIDXINFO, PAN, 7, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -56,4 +57,11 @@ static inline bool regime_has_2_ranges(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, 2RANGES); } =20 +/* Return true if Privileged Access Never is enabled for this mmu index. */ +static inline bool regime_is_pan(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, PAN); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index f880d21606..98db02b8e5 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -10,6 +10,7 @@ #define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) #define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) #define R2 R_MMUIDXINFO_2RANGES_MASK +#define PAN R_MMUIDXINFO_PAN_MASK =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* @@ -17,24 +18,24 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { */ [ARMMMUIdx_E10_0] =3D EL(0) | REL(1) | R2, [ARMMMUIdx_E10_1] =3D EL(1) | REL(1) | R2, - [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1) | R2, + [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1) | R2 | PAN, =20 [ARMMMUIdx_E20_0] =3D EL(0) | REL(2) | R2, [ARMMMUIdx_E20_2] =3D EL(2) | REL(2) | R2, - [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2) | R2, + [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2) | R2 | PAN, =20 [ARMMMUIdx_E2] =3D EL(2) | REL(2), =20 [ARMMMUIdx_E3] =3D EL(3) | REL(3), [ARMMMUIdx_E30_0] =3D EL(0) | REL(3), - [ARMMMUIdx_E30_3_PAN] =3D EL(3) | REL(3), + [ARMMMUIdx_E30_3_PAN] =3D EL(3) | REL(3) | PAN, =20 [ARMMMUIdx_Stage2_S] =3D REL(2), [ARMMMUIdx_Stage2] =3D REL(2), =20 [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2, [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2, - [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2, + [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2 | PAN, =20 /* * M-profile. --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 22:43:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v4 39/84] target/arm: Remove unused env argument from regime_is_user Date: Sat, 30 Aug 2025 15:40:43 +1000 Message-ID: <20250830054128.448363-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756574537763116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 +- target/arm/helper.c | 2 +- target/arm/ptw.c | 16 ++++++++-------- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 2148814835..1704ee8dbb 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1032,7 +1032,7 @@ static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) return mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Sta= ge2_S; } =20 -static inline bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx) +static inline bool regime_is_user(ARMMMUIdx mmu_idx) { switch (mmu_idx) { case ARMMMUIdx_E10_0: diff --git a/target/arm/helper.c b/target/arm/helper.c index b88d1573ae..4901fd5388 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9586,7 +9586,7 @@ ARMVAParameters aa64_va_parameters(CPUARMState *env, = uint64_t va, ds =3D extract64(tcr, 59, 1); =20 if (e0pd && cpu_isar_feature(aa64_e0pd, cpu) && - regime_is_user(env, mmu_idx)) { + regime_is_user(mmu_idx)) { epd =3D true; } =20 diff --git a/target/arm/ptw.c b/target/arm/ptw.c index a8c450d28b..23307b2760 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -964,7 +964,7 @@ static int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mm= u_idx, int ap, int domain_prot) { return ap_to_rw_prot_is_user(env, mmu_idx, ap, domain_prot, - regime_is_user(env, mmu_idx)); + regime_is_user(mmu_idx)); } =20 /* @@ -990,7 +990,7 @@ static int simple_ap_to_rw_prot_is_user(int ap, bool is= _user) =20 static int simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int a= p) { - return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); + return simple_ap_to_rw_prot_is_user(ap, regime_is_user(mmu_idx)); } =20 static bool get_phys_addr_v5(CPUARMState *env, S1Translate *ptw, @@ -1377,7 +1377,7 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx mmu= _idx, bool is_aa64, ARMSecuritySpace in_pa, ARMSecuritySpace out_pa) { ARMCPU *cpu =3D env_archcpu(env); - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); bool have_wxn; int wxn =3D 0; =20 @@ -1539,7 +1539,7 @@ static int get_S1prot_indirect(CPUARMState *env, S1Tr= anslate *ptw, if ((u_perm & (PAGE_RWX | PAGE_GCS)) && regime_is_pan(mmu_idx)) { p_perm &=3D ~(PAGE_READ | PAGE_WRITE); } - perm =3D regime_is_user(env, mmu_idx) ? u_perm : p_perm; + perm =3D regime_is_user(mmu_idx) ? u_perm : p_perm; } =20 if (in_pa !=3D out_pa) { @@ -2384,7 +2384,7 @@ static bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t mask; uint32_t base; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); =20 if (regime_translation_disabled(env, mmu_idx, ptw->in_space)) { /* MPU disabled. */ @@ -2551,7 +2551,7 @@ static bool get_phys_addr_pmsav7(CPUARMState *env, ARMCPU *cpu =3D env_archcpu(env); int n; ARMMMUIdx mmu_idx =3D ptw->in_mmu_idx; - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); bool secure =3D arm_space_is_secure(ptw->in_space); =20 result->f.phys_addr =3D address; @@ -2771,7 +2771,7 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t add= ress, * memory system to use a subpage. */ ARMCPU *cpu =3D env_archcpu(env); - bool is_user =3D regime_is_user(env, mmu_idx); + bool is_user =3D regime_is_user(mmu_idx); int n; int matchregion =3D -1; bool hit =3D false; @@ -3651,7 +3651,7 @@ static bool get_phys_addr_nogpc(CPUARMState *env, S1T= ranslate *ptw, break; } =20 - result->f.attrs.user =3D regime_is_user(env, mmu_idx); + result->f.attrs.user =3D regime_is_user(mmu_idx); =20 /* * Fast Context Switch Extension. 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Fri, 29 Aug 2025 22:46:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v4 40/84] target/arm: Convert regime_is_user from switch to table Date: Sat, 30 Aug 2025 15:40:44 +1000 Message-ID: <20250830054128.448363-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756575311474116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 17 ----------------- target/arm/mmuidx-internal.h | 12 ++++++++++++ target/arm/mmuidx.c | 6 ++++-- 3 files changed, 16 insertions(+), 19 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 1704ee8dbb..a2e5ae42a3 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1032,23 +1032,6 @@ static inline bool regime_is_stage2(ARMMMUIdx mmu_id= x) return mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Sta= ge2_S; } =20 -static inline bool regime_is_user(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_E10_0: - case ARMMMUIdx_E20_0: - case ARMMMUIdx_E30_0: - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_MUser: - case ARMMMUIdx_MSUser: - case ARMMMUIdx_MUserNegPri: - case ARMMMUIdx_MSUserNegPri: - return true; - default: - return false; - } -} - /* Return the SCTLR value which controls this address translation regime */ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index 41baf1a003..3e51c0f579 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -17,6 +17,7 @@ FIELD(MMUIDXINFO, REL, 3, 2) FIELD(MMUIDXINFO, RELVALID, 5, 1) FIELD(MMUIDXINFO, 2RANGES, 6, 1) FIELD(MMUIDXINFO, PAN, 7, 1) +FIELD(MMUIDXINFO, USER, 8, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -64,4 +65,15 @@ static inline bool regime_is_pan(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, PAN); } =20 +/* + * Return true if the exception level associated with this mmu index is 0. + * Differs from arm_mmu_idx_to_el(idx) =3D=3D 0 in that this allows queryi= ng + * Stage1 and Stage2 mmu indexes. + */ +static inline bool regime_is_user(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, USER); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 98db02b8e5..1c1e062bfe 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -7,10 +7,12 @@ #include "mmuidx-internal.h" =20 =20 -#define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK) +#define EL(X) ((X << R_MMUIDXINFO_EL_SHIFT) | R_MMUIDXINFO_ELVALID_MASK |= \ + ((X =3D=3D 0) << R_MMUIDXINFO_USER_SHIFT)) #define REL(X) ((X << R_MMUIDXINFO_REL_SHIFT) | R_MMUIDXINFO_RELVALID_MASK) #define R2 R_MMUIDXINFO_2RANGES_MASK #define PAN R_MMUIDXINFO_PAN_MASK +#define USER R_MMUIDXINFO_USER_MASK =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* @@ -33,7 +35,7 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { [ARMMMUIdx_Stage2_S] =3D REL(2), [ARMMMUIdx_Stage2] =3D REL(2), =20 - [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2, + [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2 | USER, [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2, [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2 | PAN, =20 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 22:46:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Pierrick Bouvier Subject: [PATCH v4 41/84] target/arm: Convert arm_mmu_idx_is_stage1_of_2 from switch to table Date: Sat, 30 Aug 2025 15:40:45 +1000 Message-ID: <20250830054128.448363-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756572280426116600 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 19 ------------------- target/arm/mmuidx-internal.h | 8 ++++++++ target/arm/mmuidx.c | 7 ++++--- 3 files changed, 12 insertions(+), 22 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index a2e5ae42a3..68db7559b0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1280,25 +1280,6 @@ ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx); ARMMMUIdx arm_stage1_mmu_idx(CPUARMState *env); #endif =20 -/** - * arm_mmu_idx_is_stage1_of_2: - * @mmu_idx: The ARMMMUIdx to test - * - * Return true if @mmu_idx is a NOTLB mmu_idx that is the - * first stage of a two stage regime. - */ -static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx) -{ - switch (mmu_idx) { - case ARMMMUIdx_Stage1_E0: - case ARMMMUIdx_Stage1_E1: - case ARMMMUIdx_Stage1_E1_PAN: - return true; - default: - return false; - } -} - static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, const ARMISARegisters *id) { diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index 3e51c0f579..55fba4aae2 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -18,6 +18,7 @@ FIELD(MMUIDXINFO, RELVALID, 5, 1) FIELD(MMUIDXINFO, 2RANGES, 6, 1) FIELD(MMUIDXINFO, PAN, 7, 1) FIELD(MMUIDXINFO, USER, 8, 1) +FIELD(MMUIDXINFO, STAGE1, 9, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -76,4 +77,11 @@ static inline bool regime_is_user(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, USER); } =20 +/* Return true if this mmu index is stage 1 of a 2-stage translation. */ +static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, STAGE1); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 1c1e062bfe..c5b43a5932 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -13,6 +13,7 @@ #define R2 R_MMUIDXINFO_2RANGES_MASK #define PAN R_MMUIDXINFO_PAN_MASK #define USER R_MMUIDXINFO_USER_MASK +#define S1 R_MMUIDXINFO_STAGE1_MASK =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* @@ -35,9 +36,9 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { [ARMMMUIdx_Stage2_S] =3D REL(2), [ARMMMUIdx_Stage2] =3D REL(2), =20 - [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2 | USER, - [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2, - [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2 | PAN, + [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2 | S1 | USER, + [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2 | S1, + [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2 | S1 | PAN, =20 /* * M-profile. --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Convert it to arm_mmuidx_table for consistency. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 ----- target/arm/mmuidx-internal.h | 8 ++++++++ target/arm/mmuidx.c | 5 +++-- 3 files changed, 11 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 68db7559b0..eb11389720 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1027,11 +1027,6 @@ static inline void arm_call_el_change_hook(ARMCPU *c= pu) } } =20 -static inline bool regime_is_stage2(ARMMMUIdx mmu_idx) -{ - return mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Sta= ge2_S; -} - /* Return the SCTLR value which controls this address translation regime */ static inline uint64_t regime_sctlr(CPUARMState *env, ARMMMUIdx mmu_idx) { diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index 55fba4aae2..1d948aa6f4 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -19,6 +19,7 @@ FIELD(MMUIDXINFO, 2RANGES, 6, 1) FIELD(MMUIDXINFO, PAN, 7, 1) FIELD(MMUIDXINFO, USER, 8, 1) FIELD(MMUIDXINFO, STAGE1, 9, 1) +FIELD(MMUIDXINFO, STAGE2, 10, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -84,4 +85,11 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx = idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, STAGE1); } =20 +/* Return true if this mmu index is stage 2 of a 2-stage translation. */ +static inline bool regime_is_stage2(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, STAGE2); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index c5b43a5932..61a682e655 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -14,6 +14,7 @@ #define PAN R_MMUIDXINFO_PAN_MASK #define USER R_MMUIDXINFO_USER_MASK #define S1 R_MMUIDXINFO_STAGE1_MASK +#define S2 R_MMUIDXINFO_STAGE2_MASK =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* @@ -33,8 +34,8 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { [ARMMMUIdx_E30_0] =3D EL(0) | REL(3), [ARMMMUIdx_E30_3_PAN] =3D EL(3) | REL(3) | PAN, =20 - [ARMMMUIdx_Stage2_S] =3D REL(2), - [ARMMMUIdx_Stage2] =3D REL(2), + [ARMMMUIdx_Stage2_S] =3D REL(2) | S2, + [ARMMMUIdx_Stage2] =3D REL(2) | S2, =20 [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2 | S1 | USER, [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2 | S1, --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756573903; cv=none; d=zohomail.com; s=zohoarc; b=mbq9SeBWu1wv19a5SUXjSIfFTscBuXk11S3gjPAQ2iXYTGaVoDrR8YpOPIBbJrrZdI/a5YiirnwPw5iF4qmxRjwLZod2yTkx1Jm9M5GQkQeO4PXf1hHFoBdUc3rOoBYwR1O9AkU0fq/J4obg1RDAt+aDRVqRQGDyYpOgxtM/mBo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756573903; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=IFBxZh+1HwniGEdeDDe31vYX1uAIGDH5PT40d1IKpIM=; b=ZCzBEwydSXOJjDr+wl3o+5I9oszCPPXXIoOsFfytGc1ERRbVdPx7QhEwmHDNWeOltCgoXOwiSIgZH0xuAy61UNq+wmtgEt810CGinFIyBoMlusn8OHWL7rmAK+8D+x2M8ttaJ0RW7aTmgETOZuXE2B0vTwCT+amTw8Ni239hG0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756573903482505.1795391013736; Sat, 30 Aug 2025 10:11:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usOCO-0001fw-TX; Sat, 30 Aug 2025 12:13:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEQE-00079A-9P for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:46:45 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEQB-0004o2-OE for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:46:42 -0400 Received: by mail-pj1-x102b.google.com with SMTP id 98e67ed59e1d1-327f95f750eso1006640a91.2 for ; Fri, 29 Aug 2025 22:46:39 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:46:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 43/84] target/arm: Introduce mmu indexes for GCS Date: Sat, 30 Aug 2025 15:40:47 +1000 Message-ID: <20250830054128.448363-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756573904598124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- include/hw/core/cpu.h | 5 ++- target/arm/mmuidx-internal.h | 8 ++++ target/arm/mmuidx.h | 71 ++++++++++++++++++++++++------------ target/arm/helper.c | 15 ++++++-- target/arm/mmuidx.c | 9 +++++ target/arm/ptw.c | 20 ++++++++++ target/arm/tcg/tlb-insns.c | 47 ++++++++++++++++-------- 7 files changed, 132 insertions(+), 43 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fc9a2291d5..671c4bc6bb 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -198,9 +198,10 @@ struct CPUClass { }; =20 /* - * Fix the number of mmu modes to 16. + * Fix the number of mmu modes across all targets. + * Current maximum is target/arm/. */ -#define NB_MMU_MODES 16 +#define NB_MMU_MODES 22 typedef uint32_t MMUIdxMap; =20 /* Use a fully associative victim tlb of 8 entries. */ diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index 1d948aa6f4..f494ec348d 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -20,6 +20,7 @@ FIELD(MMUIDXINFO, PAN, 7, 1) FIELD(MMUIDXINFO, USER, 8, 1) FIELD(MMUIDXINFO, STAGE1, 9, 1) FIELD(MMUIDXINFO, STAGE2, 10, 1) +FIELD(MMUIDXINFO, GCS, 11, 1) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -92,4 +93,11 @@ static inline bool regime_is_stage2(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, STAGE2); } =20 +/* Return true if this mmu index implies AccessType_GCS. */ +static inline bool regime_is_gcs(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, GCS); +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.h b/target/arm/mmuidx.h index 5b9b4bc84f..8d8d27337e 100644 --- a/target/arm/mmuidx.h +++ b/target/arm/mmuidx.h @@ -58,24 +58,31 @@ * already heavyweight. * 8. we cannot fold together Stage 2 Secure and Stage 2 NonSecure, * because both are in use simultaneously for Secure EL2. + * 9. we need separate indexes for handling AccessType_GCS. * * This gives us the following list of cases: * * EL0 EL1&0 stage 1+2 (aka NS PL0 PL1&0 stage 1+2) + * EL0 EL1&0 stage 1+2 +GCS * EL1 EL1&0 stage 1+2 (aka NS PL1 PL1&0 stage 1+2) * EL1 EL1&0 stage 1+2 +PAN (aka NS PL1 P1&0 stage 1+2 +PAN) + * EL1 EL1&0 stage 1+2 +GCS * EL0 EL2&0 + * EL0 EL2&0 +GCS * EL2 EL2&0 * EL2 EL2&0 +PAN + * EL2 EL2&0 +GCS * EL2 (aka NS PL2) + * EL2 +GCS * EL3 (aka AArch32 S PL1 PL1&0) + * EL3 +GCS * AArch32 S PL0 PL1&0 (we call this EL30_0) * AArch32 S PL1 PL1&0 +PAN (we call this EL30_3_PAN) * Stage2 Secure * Stage2 NonSecure * plus one TLB per Physical address space: S, NS, Realm, Root * - * for a total of 16 different mmu_idx. + * for a total of 22 different mmu_idx. * * R profile CPUs have an MPU, but can use the same set of MMU indexes * as A profile. They only need to distinguish EL0 and EL1 (and @@ -114,9 +121,9 @@ * For M profile we arrange them to have a bit for priv, a bit for negpri * and a bit for secure. */ -#define ARM_MMU_IDX_A 0x10 /* A profile */ -#define ARM_MMU_IDX_NOTLB 0x20 /* does not have a TLB */ -#define ARM_MMU_IDX_M 0x40 /* M profile */ +#define ARM_MMU_IDX_A 0x20 /* A profile */ +#define ARM_MMU_IDX_NOTLB 0x40 /* does not have a TLB */ +#define ARM_MMU_IDX_M 0x80 /* M profile */ =20 /* Meanings of the bits for M profile mmu idx values */ #define ARM_MMU_IDX_M_PRIV 0x1 @@ -125,22 +132,32 @@ =20 #define ARM_MMU_IDX_TYPE_MASK \ (ARM_MMU_IDX_A | ARM_MMU_IDX_M | ARM_MMU_IDX_NOTLB) -#define ARM_MMU_IDX_COREIDX_MASK 0xf +#define ARM_MMU_IDX_COREIDX_MASK 0x1f =20 typedef enum ARMMMUIdx { /* * A-profile. */ - ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_0 =3D 1 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2 =3D 3 | ARM_MMU_IDX_A, - ARMMMUIdx_E10_1_PAN =3D 4 | ARM_MMU_IDX_A, - ARMMMUIdx_E20_2_PAN =3D 5 | ARM_MMU_IDX_A, - ARMMMUIdx_E2 =3D 6 | ARM_MMU_IDX_A, - ARMMMUIdx_E3 =3D 7 | ARM_MMU_IDX_A, - ARMMMUIdx_E30_0 =3D 8 | ARM_MMU_IDX_A, - ARMMMUIdx_E30_3_PAN =3D 9 | ARM_MMU_IDX_A, + + ARMMMUIdx_E10_0 =3D 0 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_0_GCS =3D 1 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1 =3D 2 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_PAN =3D 3 | ARM_MMU_IDX_A, + ARMMMUIdx_E10_1_GCS =3D 4 | ARM_MMU_IDX_A, + + ARMMMUIdx_E20_0 =3D 5 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_0_GCS =3D 6 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2 =3D 7 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_PAN =3D 8 | ARM_MMU_IDX_A, + ARMMMUIdx_E20_2_GCS =3D 9 | ARM_MMU_IDX_A, + + ARMMMUIdx_E2 =3D 10 | ARM_MMU_IDX_A, + ARMMMUIdx_E2_GCS =3D 11 | ARM_MMU_IDX_A, + + ARMMMUIdx_E3 =3D 12 | ARM_MMU_IDX_A, + ARMMMUIdx_E3_GCS =3D 13 | ARM_MMU_IDX_A, + ARMMMUIdx_E30_0 =3D 14 | ARM_MMU_IDX_A, + ARMMMUIdx_E30_3_PAN =3D 15 | ARM_MMU_IDX_A, =20 /* * Used for second stage of an S12 page table walk, or for descriptor @@ -148,14 +165,14 @@ typedef enum ARMMMUIdx { * are in use simultaneously for SecureEL2: the security state for * the S2 ptw is selected by the NS bit from the S1 ptw. */ - ARMMMUIdx_Stage2_S =3D 10 | ARM_MMU_IDX_A, - ARMMMUIdx_Stage2 =3D 11 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2_S =3D 16 | ARM_MMU_IDX_A, + ARMMMUIdx_Stage2 =3D 17 | ARM_MMU_IDX_A, =20 /* TLBs with 1-1 mapping to the physical address spaces. */ - ARMMMUIdx_Phys_S =3D 12 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_NS =3D 13 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_Root =3D 14 | ARM_MMU_IDX_A, - ARMMMUIdx_Phys_Realm =3D 15 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_S =3D 18 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_NS =3D 19 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Root =3D 20 | ARM_MMU_IDX_A, + ARMMMUIdx_Phys_Realm =3D 21 | ARM_MMU_IDX_A, =20 /* * These are not allocated TLBs and are used only for AT system @@ -164,6 +181,8 @@ typedef enum ARMMMUIdx { ARMMMUIdx_Stage1_E0 =3D 0 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1 =3D 1 | ARM_MMU_IDX_NOTLB, ARMMMUIdx_Stage1_E1_PAN =3D 2 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E0_GCS =3D 3 | ARM_MMU_IDX_NOTLB, + ARMMMUIdx_Stage1_E1_GCS =3D 4 | ARM_MMU_IDX_NOTLB, =20 /* * M-profile. @@ -187,13 +206,19 @@ typedef enum ARMMMUIdx { =20 typedef enum ARMMMUIdxBit { TO_CORE_BIT(E10_0), - TO_CORE_BIT(E20_0), + TO_CORE_BIT(E10_0_GCS), TO_CORE_BIT(E10_1), TO_CORE_BIT(E10_1_PAN), - TO_CORE_BIT(E2), + TO_CORE_BIT(E10_1_GCS), + TO_CORE_BIT(E20_0), + TO_CORE_BIT(E20_0_GCS), TO_CORE_BIT(E20_2), TO_CORE_BIT(E20_2_PAN), + TO_CORE_BIT(E20_2_GCS), + TO_CORE_BIT(E2), + TO_CORE_BIT(E2_GCS), TO_CORE_BIT(E3), + TO_CORE_BIT(E3_GCS), TO_CORE_BIT(E30_0), TO_CORE_BIT(E30_3_PAN), TO_CORE_BIT(Stage2), diff --git a/target/arm/helper.c b/target/arm/helper.c index 4901fd5388..5e5d1499f1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -401,7 +401,9 @@ int alle1_tlbmask(CPUARMState *env) */ return (ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_1_GCS | ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_E10_0_GCS | ARMMMUIdxBit_Stage2 | ARMMMUIdxBit_Stage2_S); } @@ -785,12 +787,17 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) */ if (changed & (SCR_NS | SCR_NSE)) { tlb_flush_by_mmuidx(env_cpu(env), (ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_E10_0_GCS | ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_0_GCS | ARMMMUIdxBit_E10_1 | - ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E10_1_PAN | + ARMMMUIdxBit_E10_1_GCS | + ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2)); + ARMMMUIdxBit_E20_2_GCS | + ARMMMUIdxBit_E2 | + ARMMMUIdxBit_E2_GCS)); } } =20 @@ -2756,7 +2763,9 @@ static void vmsa_tcr_ttbr_el2_write(CPUARMState *env,= const ARMCPRegInfo *ri, (arm_hcr_el2_eff(env) & HCR_E2H)) { uint16_t mask =3D ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; + ARMMMUIdxBit_E20_2_GCS | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_0_GCS; tlb_flush_by_mmuidx(env_cpu(env), mask); } raw_write(env, ri, value); diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 61a682e655..42b003db9c 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -15,22 +15,29 @@ #define USER R_MMUIDXINFO_USER_MASK #define S1 R_MMUIDXINFO_STAGE1_MASK #define S2 R_MMUIDXINFO_STAGE2_MASK +#define GCS R_MMUIDXINFO_GCS_MASK =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* * A-profile. */ [ARMMMUIdx_E10_0] =3D EL(0) | REL(1) | R2, + [ARMMMUIdx_E10_0_GCS] =3D EL(0) | REL(1) | R2 | GCS, [ARMMMUIdx_E10_1] =3D EL(1) | REL(1) | R2, [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1) | R2 | PAN, + [ARMMMUIdx_E10_1_GCS] =3D EL(1) | REL(1) | R2 | GCS, =20 [ARMMMUIdx_E20_0] =3D EL(0) | REL(2) | R2, + [ARMMMUIdx_E20_0_GCS] =3D EL(0) | REL(2) | R2 | GCS, [ARMMMUIdx_E20_2] =3D EL(2) | REL(2) | R2, [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2) | R2 | PAN, + [ARMMMUIdx_E20_2_GCS] =3D EL(2) | REL(2) | R2 | GCS, =20 [ARMMMUIdx_E2] =3D EL(2) | REL(2), + [ARMMMUIdx_E2_GCS] =3D EL(2) | REL(2) | GCS, =20 [ARMMMUIdx_E3] =3D EL(3) | REL(3), + [ARMMMUIdx_E3_GCS] =3D EL(3) | REL(3) | GCS, [ARMMMUIdx_E30_0] =3D EL(0) | REL(3), [ARMMMUIdx_E30_3_PAN] =3D EL(3) | REL(3) | PAN, =20 @@ -38,8 +45,10 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { [ARMMMUIdx_Stage2] =3D REL(2) | S2, =20 [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2 | S1 | USER, + [ARMMMUIdx_Stage1_E0_GCS] =3D REL(1) | R2 | S1 | USER | GCS, [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2 | S1, [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2 | S1 | PAN, + [ARMMMUIdx_Stage1_E1_GCS] =3D REL(1) | R2 | S1 | GCS, =20 /* * M-profile. diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 23307b2760..ccdf9076c3 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -166,6 +166,10 @@ ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx mmu_idx) return ARMMMUIdx_Stage1_E1; case ARMMMUIdx_E10_1_PAN: return ARMMMUIdx_Stage1_E1_PAN; + case ARMMMUIdx_E10_0_GCS: + return ARMMMUIdx_Stage1_E0_GCS; + case ARMMMUIdx_E10_1_GCS: + return ARMMMUIdx_Stage1_E1_GCS; default: return mmu_idx; } @@ -273,8 +277,10 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, return (hcr_el2 & (HCR_DC | HCR_VM)) =3D=3D 0; =20 case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_0_GCS: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E10_1_GCS: /* TGE means that EL0/1 act as if SCTLR_EL1.M is zero */ hcr_el2 =3D arm_hcr_el2_eff_secstate(env, space); if (hcr_el2 & HCR_TGE) { @@ -283,8 +289,10 @@ static bool regime_translation_disabled(CPUARMState *e= nv, ARMMMUIdx mmu_idx, break; =20 case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E0_GCS: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_E1_GCS: /* HCR.DC means SCTLR_EL1.M behaves as 0 */ hcr_el2 =3D arm_hcr_el2_eff_secstate(env, space); if (hcr_el2 & HCR_DC) { @@ -293,10 +301,14 @@ static bool regime_translation_disabled(CPUARMState *= env, ARMMMUIdx mmu_idx, break; =20 case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_0_GCS: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_E20_2_GCS: case ARMMMUIdx_E2: + case ARMMMUIdx_E2_GCS: case ARMMMUIdx_E3: + case ARMMMUIdx_E3_GCS: case ARMMMUIdx_E30_0: case ARMMMUIdx_E30_3_PAN: break; @@ -3761,15 +3773,22 @@ arm_mmu_idx_to_security_space(CPUARMState *env, ARM= MMUIdx mmu_idx) =20 switch (mmu_idx) { case ARMMMUIdx_E10_0: + case ARMMMUIdx_E10_0_GCS: case ARMMMUIdx_E10_1: case ARMMMUIdx_E10_1_PAN: + case ARMMMUIdx_E10_1_GCS: case ARMMMUIdx_E20_0: + case ARMMMUIdx_E20_0_GCS: case ARMMMUIdx_E20_2: case ARMMMUIdx_E20_2_PAN: + case ARMMMUIdx_E20_2_GCS: case ARMMMUIdx_Stage1_E0: + case ARMMMUIdx_Stage1_E0_GCS: case ARMMMUIdx_Stage1_E1: case ARMMMUIdx_Stage1_E1_PAN: + case ARMMMUIdx_Stage1_E1_GCS: case ARMMMUIdx_E2: + case ARMMMUIdx_E2_GCS: ss =3D arm_security_space_below_el3(env); break; case ARMMMUIdx_Stage2: @@ -3798,6 +3817,7 @@ arm_mmu_idx_to_security_space(CPUARMState *env, ARMMM= UIdx mmu_idx) ss =3D ARMSS_Secure; break; case ARMMMUIdx_E3: + case ARMMMUIdx_E3_GCS: case ARMMMUIdx_E30_0: case ARMMMUIdx_E30_3_PAN: if (arm_feature(env, ARM_FEATURE_AARCH64) && diff --git a/target/arm/tcg/tlb-insns.c b/target/arm/tcg/tlb-insns.c index 95c26c6d46..1a0a332583 100644 --- a/target/arm/tcg/tlb-insns.c +++ b/target/arm/tcg/tlb-insns.c @@ -149,7 +149,8 @@ static void tlbimva_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, CPUState *cs =3D env_cpu(env); uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E2); + tlb_flush_page_by_mmuidx(cs, pageaddr, + ARMMMUIdxBit_E2 | ARMMMUIdxBit_E2_GCS); } =20 static void tlbimva_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -159,7 +160,8 @@ static void tlbimva_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, uint64_t pageaddr =3D value & ~MAKE_64BIT_MASK(0, 12); =20 tlb_flush_page_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E2); + ARMMMUIdxBit_E2 | + ARMMMUIdxBit_E2_GCS); } =20 static void tlbiipas2_hyp_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -202,7 +204,7 @@ static void tlbiall_hyp_write(CPUARMState *env, const A= RMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E2 | ARMMMUIdxBit_E2_GCS); } =20 static void tlbiall_hyp_is_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -210,7 +212,8 @@ static void tlbiall_hyp_is_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2); + tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E2 | + ARMMMUIdxBit_E2_GCS); } =20 /* @@ -228,12 +231,16 @@ static int vae1_tlbmask(CPUARMState *env) if ((hcr & (HCR_E2H | HCR_TGE)) =3D=3D (HCR_E2H | HCR_TGE)) { mask =3D ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; + ARMMMUIdxBit_E20_2_GCS | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_0_GCS; } else { /* This is AArch64 only, so we don't need to touch the EL30_x TLBs= */ mask =3D ARMMMUIdxBit_E10_1 | ARMMMUIdxBit_E10_1_PAN | - ARMMMUIdxBit_E10_0; + ARMMMUIdxBit_E10_1_GCS | + ARMMMUIdxBit_E10_0 | + ARMMMUIdxBit_E10_0_GCS; } return mask; } @@ -246,13 +253,20 @@ static int vae2_tlbmask(CPUARMState *env) if (hcr & HCR_E2H) { mask =3D ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E20_0; + ARMMMUIdxBit_E20_2_GCS | + ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_0_GCS; } else { - mask =3D ARMMMUIdxBit_E2; + mask =3D ARMMMUIdxBit_E2 | ARMMMUIdxBit_E2_GCS; } return mask; } =20 +static int vae3_tlbmask(void) +{ + return ARMMMUIdxBit_E3 | ARMMMUIdxBit_E3_GCS; +} + /* Return 56 if TBI is enabled, 64 otherwise. */ static int tlbbits_for_regime(CPUARMState *env, ARMMMUIdx mmu_idx, uint64_t addr) @@ -325,9 +339,12 @@ static void tlbi_aa64_vmalle1_write(CPUARMState *env, = const ARMCPRegInfo *ri, static int e2_tlbmask(CPUARMState *env) { return (ARMMMUIdxBit_E20_0 | + ARMMMUIdxBit_E20_0_GCS | ARMMMUIdxBit_E20_2 | ARMMMUIdxBit_E20_2_PAN | - ARMMMUIdxBit_E2); + ARMMMUIdxBit_E20_2_GCS | + ARMMMUIdxBit_E2 | + ARMMMUIdxBit_E2_GCS); } =20 static void tlbi_aa64_alle1_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -354,7 +371,7 @@ static void tlbi_aa64_alle3_write(CPUARMState *env, con= st ARMCPRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); CPUState *cs =3D CPU(cpu); =20 - tlb_flush_by_mmuidx(cs, ARMMMUIdxBit_E3); + tlb_flush_by_mmuidx(cs, vae3_tlbmask()); } =20 static void tlbi_aa64_alle1is_write(CPUARMState *env, const ARMCPRegInfo *= ri, @@ -380,7 +397,7 @@ static void tlbi_aa64_alle3is_write(CPUARMState *env, c= onst ARMCPRegInfo *ri, { CPUState *cs =3D env_cpu(env); =20 - tlb_flush_by_mmuidx_all_cpus_synced(cs, ARMMMUIdxBit_E3); + tlb_flush_by_mmuidx_all_cpus_synced(cs, vae3_tlbmask()); } =20 static void tlbi_aa64_vae2_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -411,7 +428,7 @@ static void tlbi_aa64_vae3_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, CPUState *cs =3D CPU(cpu); uint64_t pageaddr =3D sextract64(value << 12, 0, 56); =20 - tlb_flush_page_by_mmuidx(cs, pageaddr, ARMMMUIdxBit_E3); + tlb_flush_page_by_mmuidx(cs, pageaddr, vae3_tlbmask()); } =20 static void tlbi_aa64_vae1is_write(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -465,7 +482,7 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env, co= nst ARMCPRegInfo *ri, int bits =3D tlbbits_for_regime(env, ARMMMUIdx_E3, pageaddr); =20 tlb_flush_page_bits_by_mmuidx_all_cpus_synced(cs, pageaddr, - ARMMMUIdxBit_E3, bits); + vae3_tlbmask(), bits); } =20 static int ipas2e1_tlbmask(CPUARMState *env, int64_t value) @@ -963,7 +980,7 @@ static void tlbi_aa64_rvae3_write(CPUARMState *env, * flush-last-level-only. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_E3, tlb_force_broadcast(env)); + do_rvae_write(env, value, vae3_tlbmask(), tlb_force_broadcast(env)); } =20 static void tlbi_aa64_rvae3is_write(CPUARMState *env, @@ -977,7 +994,7 @@ static void tlbi_aa64_rvae3is_write(CPUARMState *env, * flush-last-level-only or inner/outer specific flushes. */ =20 - do_rvae_write(env, value, ARMMMUIdxBit_E3, true); + do_rvae_write(env, value, vae3_tlbmask(), true); } =20 static void tlbi_aa64_ripas2e1_write(CPUARMState *env, const ARMCPRegInfo = *ri, --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/mmuidx-internal.h | 10 ++++++++++ target/arm/mmuidx.c | 24 +++++++++++++----------- 2 files changed, 23 insertions(+), 11 deletions(-) diff --git a/target/arm/mmuidx-internal.h b/target/arm/mmuidx-internal.h index f494ec348d..962b053852 100644 --- a/target/arm/mmuidx-internal.h +++ b/target/arm/mmuidx-internal.h @@ -21,6 +21,7 @@ FIELD(MMUIDXINFO, USER, 8, 1) FIELD(MMUIDXINFO, STAGE1, 9, 1) FIELD(MMUIDXINFO, STAGE2, 10, 1) FIELD(MMUIDXINFO, GCS, 11, 1) +FIELD(MMUIDXINFO, TG, 12, 5) =20 extern const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8]; =20 @@ -100,4 +101,13 @@ static inline bool regime_is_gcs(ARMMMUIdx idx) return FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, GCS); } =20 +/* Return the GCS MMUIdx for a given regime. */ +static inline ARMMMUIdx regime_to_gcs(ARMMMUIdx idx) +{ + tcg_debug_assert(arm_mmuidx_is_valid(idx)); + uint32_t core =3D FIELD_EX32(arm_mmuidx_table[idx], MMUIDXINFO, TG); + tcg_debug_assert(core !=3D 0); /* core 0 is E10_0, not a GCS index */ + return core | ARM_MMU_IDX_A; +} + #endif /* TARGET_ARM_MMUIDX_INTERNAL_H */ diff --git a/target/arm/mmuidx.c b/target/arm/mmuidx.c index 42b003db9c..a4663c8d87 100644 --- a/target/arm/mmuidx.c +++ b/target/arm/mmuidx.c @@ -16,27 +16,29 @@ #define S1 R_MMUIDXINFO_STAGE1_MASK #define S2 R_MMUIDXINFO_STAGE2_MASK #define GCS R_MMUIDXINFO_GCS_MASK +#define TG(X) \ + ((ARMMMUIdx_##X##_GCS & ARM_MMU_IDX_COREIDX_MASK) << R_MMUIDXINFO_TG_S= HIFT) =20 const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { /* * A-profile. */ - [ARMMMUIdx_E10_0] =3D EL(0) | REL(1) | R2, + [ARMMMUIdx_E10_0] =3D EL(0) | REL(1) | R2 | TG(E10_0), [ARMMMUIdx_E10_0_GCS] =3D EL(0) | REL(1) | R2 | GCS, - [ARMMMUIdx_E10_1] =3D EL(1) | REL(1) | R2, - [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1) | R2 | PAN, + [ARMMMUIdx_E10_1] =3D EL(1) | REL(1) | R2 | TG(E10_1), + [ARMMMUIdx_E10_1_PAN] =3D EL(1) | REL(1) | R2 | TG(E10_1) | PAN, [ARMMMUIdx_E10_1_GCS] =3D EL(1) | REL(1) | R2 | GCS, =20 - [ARMMMUIdx_E20_0] =3D EL(0) | REL(2) | R2, + [ARMMMUIdx_E20_0] =3D EL(0) | REL(2) | R2 | TG(E20_0), [ARMMMUIdx_E20_0_GCS] =3D EL(0) | REL(2) | R2 | GCS, - [ARMMMUIdx_E20_2] =3D EL(2) | REL(2) | R2, - [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2) | R2 | PAN, + [ARMMMUIdx_E20_2] =3D EL(2) | REL(2) | R2 | TG(E20_2), + [ARMMMUIdx_E20_2_PAN] =3D EL(2) | REL(2) | R2 | TG(E20_2) | PAN, [ARMMMUIdx_E20_2_GCS] =3D EL(2) | REL(2) | R2 | GCS, =20 - [ARMMMUIdx_E2] =3D EL(2) | REL(2), + [ARMMMUIdx_E2] =3D EL(2) | REL(2) | TG(E2), [ARMMMUIdx_E2_GCS] =3D EL(2) | REL(2) | GCS, =20 - [ARMMMUIdx_E3] =3D EL(3) | REL(3), + [ARMMMUIdx_E3] =3D EL(3) | REL(3) | TG(E3), [ARMMMUIdx_E3_GCS] =3D EL(3) | REL(3) | GCS, [ARMMMUIdx_E30_0] =3D EL(0) | REL(3), [ARMMMUIdx_E30_3_PAN] =3D EL(3) | REL(3) | PAN, @@ -44,10 +46,10 @@ const uint32_t arm_mmuidx_table[ARM_MMU_IDX_M + 8] =3D { [ARMMMUIdx_Stage2_S] =3D REL(2) | S2, [ARMMMUIdx_Stage2] =3D REL(2) | S2, =20 - [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2 | S1 | USER, + [ARMMMUIdx_Stage1_E0] =3D REL(1) | R2 | S1 | USER | TG(Stage1_E0= ), [ARMMMUIdx_Stage1_E0_GCS] =3D REL(1) | R2 | S1 | USER | GCS, - [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2 | S1, - [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2 | S1 | PAN, + [ARMMMUIdx_Stage1_E1] =3D REL(1) | R2 | S1 | TG(Stage1_E1), + [ARMMMUIdx_Stage1_E1_PAN] =3D REL(1) | R2 | S1 | TG(Stage1_E1) | PAN, [ARMMMUIdx_Stage1_E1_GCS] =3D REL(1) | R2 | S1 | GCS, =20 /* --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/ptw.c | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-) diff --git a/target/arm/ptw.c b/target/arm/ptw.c index ccdf9076c3..62aaf0f792 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -1584,12 +1584,16 @@ static int get_S1prot_indirect(CPUARMState *env, S1= Translate *ptw, } } =20 - if (perm & PAGE_WXN) { + if (regime_is_gcs(mmu_idx)) { + /* + * Note that the one s1perms.gcs bit controls both read and write + * access via AccessType_GCS. See AArch64.S1CheckPermissions. + */ + perm =3D (perm & PAGE_GCS ? PAGE_READ | PAGE_WRITE : 0); + } else if (perm & PAGE_WXN) { perm &=3D ~PAGE_EXEC; } =20 - /* TODO: FEAT_GCS */ - return perm & PAGE_RWX; } =20 @@ -2236,6 +2240,13 @@ static bool get_phys_addr_lpae(CPUARMState *env, S1T= ranslate *ptw, */ prot =3D get_S1prot_indirect(env, ptw, mmu_idx, pi, po, result->f.attrs.space, out_space); + } else if (regime_is_gcs(mmu_idx)) { + /* + * While one must use indirect permissions to successfully + * use GCS instructions, AArch64.S1DirectBasePermissions + * faithfully supplies s1perms.gcs =3D 0, Just In Case. + */ + prot =3D 0; } else { int xn =3D extract64(attrs, 54, 1); int pxn =3D extract64(attrs, 53, 1); --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756574297; cv=none; d=zohomail.com; s=zohoarc; b=OCL1U9pwy5eoVCI9hhGNHyCtt+9DIoOtBo/HJMxXhcJKlX7fyndUiewKCwKd9ABLX3g+b6hZjeJRg6q7TD605HvlLcfjoAYVb1cijIBfbqzrQFy+jgA1vAWvg83L5qqlrlBGXFZ0FFv2+9s8rixq3Yy08Aht7k5dWOxgH3e5wAY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756574297; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=ZnGv3gaWQ9shrmt0WGxn8YCEO4EdUIFI2jl/MhJPR7Y=; b=FSYmHqmgY4BlYW+MyH54Q7R8wAD9PaadxtldXt5GM5psP19KCRqA63db50PRoreQw1Z5hOptYj2AnGmLGrk+wj7EdeubvRRtCsBP2CVoleDGOIOvvbPJq+Yh9IPbgBWzsO6c/pnngh2lVuzpnUS12N/RCU2KdYDQruGSxYMxNFQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756574297819170.3335810629253; Sat, 30 Aug 2025 10:18:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usODA-0002sU-P1; Sat, 30 Aug 2025 12:13:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEQW-0007Eg-FH for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:00 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEQJ-0004pd-Tv for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:46:52 -0400 Received: by mail-pg1-x534.google.com with SMTP id 41be03b00d2f7-b4dc35711d9so688081a12.0 for ; Fri, 29 Aug 2025 22:46:47 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:46:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 46/84] target/arm: Implement gcs bit for data abort Date: Sat, 30 Aug 2025 15:40:50 +1000 Message-ID: <20250830054128.448363-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756574299208124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/tlb_helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/tcg/tlb_helper.c b/target/arm/tcg/tlb_helper.c index ae2acd6727..f1983a5732 100644 --- a/target/arm/tcg/tlb_helper.c +++ b/target/arm/tcg/tlb_helper.c @@ -28,7 +28,7 @@ static inline uint64_t merge_syn_data_abort(uint32_t temp= late_syn, ARMMMUFaultInfo *fi, unsigned int target_el, bool same_el, bool is_write, - int fsc) + int fsc, bool gcs) { uint64_t syn; =20 @@ -78,6 +78,7 @@ static inline uint64_t merge_syn_data_abort(uint32_t temp= late_syn, =20 /* Form ISS2 at the top of the syndrome. */ syn |=3D (uint64_t)fi->dirtybit << 37; + syn |=3D (uint64_t)gcs << 40; =20 return syn; } @@ -252,9 +253,10 @@ void arm_deliver_fault(ARMCPU *cpu, vaddr addr, syn =3D syn_insn_abort(same_el, fi->ea, fi->s1ptw, fsc); exc =3D EXCP_PREFETCH_ABORT; } else { + bool gcs =3D regime_is_gcs(core_to_arm_mmu_idx(env, mmu_idx)); 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Enable SCR_GCSEN in scr_write. Enable HCRX_GCSEN in hcrx_write. Default HCRX_GCSEN on if EL2 disabled. Add the GCSCR* and GCSPR* registers. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 2 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 12 ++++++ target/arm/internals.h | 3 ++ target/arm/cpregs-gcs.c | 91 +++++++++++++++++++++++++++++++++++++++ target/arm/cpu.c | 3 ++ target/arm/helper.c | 10 +++++ target/arm/meson.build | 2 + 8 files changed, 128 insertions(+) create mode 100644 target/arm/cpregs-gcs.c diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 9efe9238c1..bc6adf5956 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -774,6 +774,8 @@ typedef enum FGTBit { DO_BIT(HFGRTR, VBAR_EL1), DO_BIT(HFGRTR, ICC_IGRPENN_EL1), DO_BIT(HFGRTR, ERRIDR_EL1), + DO_REV_BIT(HFGRTR, NGCS_EL0), + DO_REV_BIT(HFGRTR, NGCS_EL1), DO_REV_BIT(HFGRTR, NSMPRI_EL1), DO_REV_BIT(HFGRTR, NTPIDR2_EL0), DO_REV_BIT(HFGRTR, NPIRE0_EL1), diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 30226814bb..4a35cf6b69 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -729,6 +729,11 @@ static inline bool isar_feature_aa64_nmi(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64PFR1, NMI) !=3D 0; } =20 +static inline bool isar_feature_aa64_gcs(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64PFR1, GCS) !=3D 0; +} + static inline bool isar_feature_aa64_tgran4_lpa2(const ARMISARegisters *id) { return FIELD_SEX64_IDREG(id, ID_AA64MMFR0, TGRAN4) >=3D 1; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8905798c8f..58696dcfaa 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -582,6 +582,9 @@ typedef struct CPUArchState { =20 /* NV2 register */ uint64_t vncr_el2; + + uint64_t gcscr_el[4]; /* GCSCRE0_EL1, GCSCR_EL[123] */ + uint64_t gcspr_el[4]; /* GCSPR_EL[0123] */ } cp15; =20 struct { @@ -1726,6 +1729,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_ENAS0 (1ULL << 36) #define SCR_ADEN (1ULL << 37) #define SCR_HXEN (1ULL << 38) +#define SCR_GCSEN (1ULL << 39) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) #define SCR_TCR2EN (1ULL << 43) @@ -1734,6 +1738,14 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 +/* GCSCR_ELx fields */ +#define GCSCR_PCRSEL (1ULL << 0) +#define GCSCR_RVCHKEN (1ULL << 5) +#define GCSCR_EXLOCKEN (1ULL << 6) +#define GCSCR_PUSHMEN (1ULL << 8) +#define GCSCR_STREN (1ULL << 9) +#define GCSCRE0_NTR (1ULL << 10) + /* Return the current FPSCR value. */ uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); diff --git a/target/arm/internals.h b/target/arm/internals.h index eb11389720..6a7f883f3c 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -251,6 +251,7 @@ FIELD(VSTCR, SA, 30, 1) #define HCRX_MSCEN (1ULL << 11) #define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) +#define HCRX_GCSEN (1ULL << 22) =20 #define HPFAR_NS (1ULL << 63) =20 @@ -1775,6 +1776,8 @@ void define_tlb_insn_regs(ARMCPU *cpu); void define_at_insn_regs(ARMCPU *cpu); /* Add the cpreg definitions for PM cpregs */ void define_pm_cpregs(ARMCPU *cpu); +/* Add the cpreg definitions for GCS cpregs */ +void define_gcs_cpregs(ARMCPU *cpu); =20 /* Effective value of MDCR_EL2 */ static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env) diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c new file mode 100644 index 0000000000..1a64acd584 --- /dev/null +++ b/target/arm/cpregs-gcs.c @@ -0,0 +1,91 @@ +/* + * QEMU ARM CP Register GCS regiters and instructions + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/timer.h" +#include "exec/icount.h" +#include "hw/irq.h" +#include "cpu.h" +#include "cpu-features.h" +#include "cpregs.h" +#include "internals.h" + + +static CPAccessResult access_gcs(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_GCSEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_gcs_el0(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + if (arm_current_el(env) =3D=3D 0 && !(env->cp15.gcscr_el[0] & GCSCRE0_= NTR)) { + return CP_ACCESS_TRAP_EL1; + } + return access_gcs(env, ri, isread); +} + +static void gcspr_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + /* + * Bits [2:0] are RES0, so we might as well clear them now, + * rather than upon each usage a-la GetCurrentGCSPointer. + */ + raw_write(env, ri, value & ~7); +} + +static const ARMCPRegInfo gcs_reginfo[] =3D { + { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL0, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[0]) }, + { .name =3D "GCSCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL1_RW, .accessfn =3D access_gcs, .fgt =3D FGT_NGCS_EL1, + .nv2_redirect_offset =3D 0x8d0 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[1]) }, + { .name =3D "GCSCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL2_RW, .accessfn =3D access_gcs, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[2]) }, + { .name =3D "GCSCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 0, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcscr_el[3]) }, + + { .name =3D "GCSPR_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL0_R | PL1_W, .accessfn =3D access_gcs_el0, + .fgt =3D FGT_NGCS_EL0, .writefn =3D gcspr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[0]) }, + { .name =3D "GCSPR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_gcs, + .fgt =3D FGT_NGCS_EL1, .writefn =3D gcspr_write, + .nv2_redirect_offset =3D 0x8c0 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[1]) }, + { .name =3D "GCSPR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL2_RW, .accessfn =3D access_gcs, .writefn =3D gcspr_wri= te, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, + { .name =3D "GCSPR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, + .access =3D PL3_RW, .writefn =3D gcspr_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, +}; + +void define_gcs_cpregs(ARMCPU *cpu) +{ + if (cpu_isar_feature(aa64_gcs, cpu)) { + define_arm_cp_regs(cpu, gcs_reginfo); + } +} diff --git a/target/arm/cpu.c b/target/arm/cpu.c index bf4bb04d95..6673d536bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -644,6 +644,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + env->cp15.scr_el3 |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { env->cp15.scr_el3 |=3D SCR_TCR2EN; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 5e5d1499f1..7a23730299 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -743,6 +743,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D SCR_GCSEN; + } if (cpu_isar_feature(aa64_tcr2, cpu)) { valid_mask |=3D SCR_TCR2EN; } @@ -3944,6 +3947,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPR= egInfo *ri, if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + valid_mask |=3D HCRX_GCSEN; + } =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; @@ -4014,6 +4020,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) if (cpu_isar_feature(aa64_sctlr2, cpu)) { hcrx |=3D HCRX_SCTLR2EN; } + if (cpu_isar_feature(aa64_gcs, cpu)) { + hcrx |=3D HCRX_GCSEN; + } return hcrx; } if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXE= N)) { @@ -7468,6 +7477,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 define_pm_cpregs(cpu); + define_gcs_cpregs(cpu); =20 #ifndef CONFIG_USER_ONLY /* diff --git a/target/arm/meson.build b/target/arm/meson.build index 91630a1f72..8c82304fde 100644 --- a/target/arm/meson.build +++ b/target/arm/meson.build @@ -27,6 +27,7 @@ arm_user_ss.add(when: 'TARGET_AARCH64', if_false: files( 'cpu32-stubs.c', )) arm_user_ss.add(files( + 'cpregs-gcs.c', 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', @@ -42,6 +43,7 @@ arm_common_system_ss.add(files( 'arch_dump.c', 'arm-powerctl.c', 'cortex-regs.c', + 'cpregs-gcs.c', 'cpregs-pmu.c', 'debug_helper.c', 'helper.c', --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpu.h | 3 +++ target/arm/tcg/translate.h | 6 ++++++ target/arm/tcg/hflags.c | 38 ++++++++++++++++++++++++++++++++++ target/arm/tcg/translate-a64.c | 3 +++ 4 files changed, 50 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 58696dcfaa..6568bca5f9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2908,6 +2908,9 @@ FIELD(TBFLAG_A64, NV2_MEM_BE, 36, 1) FIELD(TBFLAG_A64, AH, 37, 1) /* FPCR.AH */ FIELD(TBFLAG_A64, NEP, 38, 1) /* FPCR.NEP */ FIELD(TBFLAG_A64, ZT0EXC_EL, 39, 2) +FIELD(TBFLAG_A64, GCS_EN, 41, 1) +FIELD(TBFLAG_A64, GCS_RVCEN, 42, 1) +FIELD(TBFLAG_A64, GCSSTR_EL, 43, 2) =20 /* * Helpers for using the above. Note that only the A64 accessors use diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index f974996f3f..3e63dad2b6 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -164,6 +164,12 @@ typedef struct DisasContext { bool fpcr_ah; /* True if FPCR.NEP is 1 (FEAT_AFP scalar upper-element result handlin= g) */ bool fpcr_nep; + /* True if GCSEnabled. */ + bool gcs_en; + /* True if GCSReturnValueCheckEnabled. */ + bool gcs_rvcen; + /* GCSSTR exception EL or 0 if enabled */ + uint8_t gcsstr_el; /* * >=3D 0, a copy of PSTATE.BTYPE, which will be 0 without v8.5-BTI. * < 0, set by the current instruction. diff --git a/target/arm/tcg/hflags.c b/target/arm/tcg/hflags.c index 59ab526375..2e3a9cf0d3 100644 --- a/target/arm/tcg/hflags.c +++ b/target/arm/tcg/hflags.c @@ -449,6 +449,44 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMState *e= nv, int el, int fp_el, DP_TBFLAG_A64(flags, TCMA, aa64_va_parameter_tcma(tcr, mmu_idx)); } =20 + if (cpu_isar_feature(aa64_gcs, env_archcpu(env))) { + /* C.f. GCSEnabled */ + if (env->cp15.gcscr_el[el] & GCSCR_PCRSEL) { + switch (el) { + default: + if (!el_is_in_host(env, el) + && !(arm_hcrx_el2_eff(env) & HCRX_GCSEN)) { + break; + } + /* fall through */ + case 2: + if (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_GCSEN)) { + break; + } + /* fall through */ + case 3: + DP_TBFLAG_A64(flags, GCS_EN, 1); + break; + } + } + + /* C.f. GCSReturnValueCheckEnabled */ + if (env->cp15.gcscr_el[el] & GCSCR_RVCHKEN) { + DP_TBFLAG_A64(flags, GCS_RVCEN, 1); + } + + /* C.f. CheckGCSSTREnabled */ + if (!(env->cp15.gcscr_el[el] & GCSCR_STREN)) { + DP_TBFLAG_A64(flags, GCSSTR_EL, el ? el : 1); + } else if (el =3D=3D 1 + && EX_TBFLAG_ANY(flags, FGT_ACTIVE) + && !FIELD_EX64(env->cp15.fgt_exec[FGTREG_HFGITR], + HFGITR_EL2, NGCSSTR_EL1)) { + DP_TBFLAG_A64(flags, GCSSTR_EL, 2); + } + } + if (env->vfp.fpcr & FPCR_AH) { DP_TBFLAG_A64(flags, AH, 1); } diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 37bedc3780..4139b0345f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10313,6 +10313,9 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->nv2_mem_be =3D EX_TBFLAG_A64(tb_flags, NV2_MEM_BE); dc->fpcr_ah =3D EX_TBFLAG_A64(tb_flags, AH); dc->fpcr_nep =3D EX_TBFLAG_A64(tb_flags, NEP); + dc->gcs_en =3D EX_TBFLAG_A64(tb_flags, GCS_EN); + dc->gcs_rvcen =3D EX_TBFLAG_A64(tb_flags, GCS_RVCEN); + dc->gcsstr_el =3D EX_TBFLAG_A64(tb_flags, GCSSTR_EL); dc->vec_len =3D 0; dc->vec_stride =3D 0; dc->cp_regs =3D arm_cpu->cp_regs; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570109; cv=none; d=zohomail.com; s=zohoarc; b=MyOScTR+vN/qra4XBJub30btIuIvQ7IUQgUFnIiV5vJR3rmwXHnFDTBHHJBVxXyBSvXeFBpZGlSrYEh5/f3x216TfM5iVXg+cumwXfuyRDi81XaVkx/0WMa4L2AGyNMnd6wwTOibryGbWeDtLJz7cPs1mtyBfXZQrEgtgexwVkQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570109; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QZLKbvaJXmVjJqae0cs73+DMl1qe751GQQY47wH+UJk=; b=KnYvafD/8mO7yHfTlIYwOdLoHoIVhbz3DQjD0OG1agaxp09vQMJ6Q/9jPGRGxBbIyyvoA3CR1fR4ZYUE+i60Am1PiqzqT4/Pnkdmdr6hKiCruifd2GduVgBj9axF0JjSFDMFyFU9nUfMr9GHNiiIr1dv2zIsktvC3n2U6fYJrxc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175657010939971.63909361845629; Sat, 30 Aug 2025 09:08:29 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNxr-0005ew-9w; Sat, 30 Aug 2025 11:58:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEQb-0007Fc-Vp for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:08 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEQW-0004qW-6C for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:01 -0400 Received: by mail-pg1-x52c.google.com with SMTP id 41be03b00d2f7-b4e84a61055so71317a12.0 for ; Fri, 29 Aug 2025 22:46:56 -0700 (PDT) Received: from stoup.. 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[122.150.204.179]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2490658999fsm40852715ad.112.2025.08.29.22.46.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:46:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756532815; x=1757137615; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=QZLKbvaJXmVjJqae0cs73+DMl1qe751GQQY47wH+UJk=; b=P+ZCJQ7Z/vqqrN502oeGR6ivwkU1B5RlwzwD8B3NJUpcG2wYOx9k9SHifJ47CYuhXb +yA1fcY6tlUn5oobF+Z21Qac8DtmShekzYZXus+Br3hK2dHRuyO0ThsbuEFQJSIXopkx BqwhOBPNxPUdVOBoLw99BOou5H8prNOMElp+mhqSVqEh1JfkvHxPNosRs5oYPwkNdfBd dz5s8vvcur8xaP2A1x0fDC5ImhTld5Omy7/DVCZgOvgf1Sv7S6z8ZtyUBEaJBBl6OlM8 xqPWxkszoPWv73CGTVIAq9VT07vGH1H+n+L7hx9PLvxdJL90QVFjGcmM7sX/4BEuU24b /6Gw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756532815; x=1757137615; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QZLKbvaJXmVjJqae0cs73+DMl1qe751GQQY47wH+UJk=; b=l2b0DJNCevnGMzHZHUn2Zsb8ugXIER59PKX+iTTk+9iY6JEkfosi9wgNhiBTEJt3Xx xPST98YiVZ8Bycc7dGyNV5E1WIpJ1U6fFoRZ47I9iz4y8aKjT0L0Ea8DDB0q7QT0io76 CDK4Gvc59BNNd42plpakftxa73m9qI9rL6fFu7PGRpT0TBnOnX3FDwL5MVMyKqoIpATZ gob7nO806zW/jQXJYWgqHQtjqKabNJ+NoE7uqj6AGME9OLPDkjJj+Xgvhw9P9AWzTqxO CQt+wlqcnowEi5oRgleVxu261leV4LH7qe6Cbh6SMoM3vW41qQLh8C0Q/OPsSkyVJAFW nteA== X-Gm-Message-State: AOJu0Yxf0Hy1J6bB7+iSaE6F1wkXwyPJXJBVgOZ1Xj3L5HCnnuR9li16 Y7NOOYuHniSAWTDoRy128b/gLlfilSW2uO0jXHpB5Euz005HPKBKTuxBIkOoWaOg7bxanF4KNth NGmNWHS0= X-Gm-Gg: ASbGncs6v8fN4vq5KzLVyYg0GdO1EIQYybWc8ZleVWe7c8tuxAHAiOG8uBc+yiK8ob/ zEekmdrOuxOjw2ttNMiaNUVKW0Ga8Ou37quiLvi8GZf/wKvY+5kz+t6Wy6xsJJtVp0umiUWetZz /Hh7bu7jD9jpOqQOlGpKjdTDATA1v0MnL9vRsA+5mU8NHBrt/Qdkk0/N3iVhckr6rP9htaEiG+a ZNLU6/m6/btEIgXHuaY+4/d4SlIqA/aJGd7qitfTnLD4kZmiOiaH3bZ8bC6mH2yGpHkDLv8GVCK VgBRBw/Y8+rCC6nwiOG4zB7UVViKY7A0h7felb9tihsm/TccgiMa6JmPBfhIy3DBmFdniKlLAaV NEv92DmcpVjm0xfRdZRKQetUsHhjF7kGB4S1d7egiAlQTzA/FRbCeTtLFtZRr+sY= X-Google-Smtp-Source: AGHT+IEVNvqMG3+DGDs3rlePUboNFtyM1HZa+e+tI8fBAMOBtmtGPrJV9lbaPkeGHnRlWk3fPMNvqA== X-Received: by 2002:a17:903:1250:b0:249:1234:9f7c with SMTP id d9443c01a7336-24944b23caamr15133335ad.60.1756532815345; Fri, 29 Aug 2025 22:46:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Gustavo Romero , Pierrick Bouvier Subject: [PATCH v4 49/84] target/arm: Implement FEAT_CHK Date: Sat, 30 Aug 2025 15:40:53 +1000 Message-ID: <20250830054128.448363-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570111283116600 Content-Type: text/plain; charset="utf-8" This feature contains only the CHKFEAT instruction. It has no ID enable, being back-allocated into the hint nop space. Reviewed-by: Gustavo Romero Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 14 ++++++++++++++ docs/system/arm/emulation.rst | 1 + target/arm/tcg/a64.decode | 1 + 3 files changed, 16 insertions(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 4139b0345f..8c73f54e9a 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2124,6 +2124,20 @@ static bool trans_AUTIBSP(DisasContext *s, arg_AUTIB= SP *a) return true; } =20 +static bool trans_CHKFEAT(DisasContext *s, arg_CHKFEAT *a) +{ + uint64_t feat_en =3D 0; + + if (s->gcs_en) { + feat_en |=3D 1 << 0; + } + if (feat_en) { + TCGv_i64 x16 =3D cpu_reg(s, 16); + tcg_gen_andi_i64(x16, x16, ~feat_en); + } + return true; +} + static bool trans_CLREX(DisasContext *s, arg_CLREX *a) { tcg_gen_movi_i64(cpu_exclusive_addr, -1); diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 94a6192fa9..4b07af9eac 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -28,6 +28,7 @@ the following architecture extensions: - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CCIDX (Extended cache index) +- FEAT_CHK (Check Feature Status) - FEAT_CMOW (Control for cache maintenance permission) - FEAT_CRC32 (CRC32 instructions) - FEAT_Crypto (Cryptographic Extension) diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 55ff6c504f..8283a9c83d 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -256,6 +256,7 @@ ERETA 1101011 0100 11111 00001 m:1 11111 1111= 1 &reta # ERETAA, ERETAB AUTIASP 1101 0101 0000 0011 0010 0011 101 11111 AUTIBZ 1101 0101 0000 0011 0010 0011 110 11111 AUTIBSP 1101 0101 0000 0011 0010 0011 111 11111 + CHKFEAT 1101 0101 0000 0011 0010 0101 000 11111 ] # The canonical NOP has CRm =3D=3D op2 =3D=3D 0, but all of the space # that isn't specifically allocated to an instruction must NOP --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756574170; cv=none; d=zohomail.com; s=zohoarc; b=hPqUd+4UzeNSeb1adN2UBBciPV9mo7H21RdMKekhHAg+oG1kNSQMwzotAyh2qb3qZn737kNUHEpiWfR+ZkqaT0PNt9SMA+EyQHHQN5FDG+emtzUvs7/oRj3Jp7DZO+Ehl0KL2bc9rSJE8YzuvPKCjf4PhtW+QD+zKsI+MNrb1hY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756574170; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=APFM5mjm/10n5J+KtKVCrzvfw+w3wn4sm2ZqcCK7Dck=; b=L4ktkl7DEhXaJsS7++/cT2hjDlBeQWZj2UHt9I7XTukZJrqMvzqfK4wiYC51CnDN2uTriI68JQ+bZyoWO4HNO4NcQ8zhfTUoHlNfuRu2rTqFF05pTtdAjcNo5Mo2qkYSXIckdXyjTcra01ylAiFyH4WEJnBAA+0O+ehZHh1HE40= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756574170206704.8837205544373; Sat, 30 Aug 2025 10:16:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usODV-0003TA-Ft; Sat, 30 Aug 2025 12:14:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEQb-0007Fd-V9 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:08 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEQW-0004qk-6X for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:03 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-b47175d02dcso2347612a12.3 for ; Fri, 29 Aug 2025 22:46:59 -0700 (PDT) Received: from stoup.. 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[122.150.204.179]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2490658999fsm40852715ad.112.2025.08.29.22.46.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:46:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756532818; x=1757137618; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=APFM5mjm/10n5J+KtKVCrzvfw+w3wn4sm2ZqcCK7Dck=; b=t7s/W9/uErsJL9HQ9OYlZvacEnmXVBzmbXqf3jd+2u8eHHg4/NMbfooUH9IrjmQqkN oLQM5v1ezLTzfh0n4Jljs5wlBAB2ngeUpo0Dj9ifx27kdORK7rQI6SXnKrIsRc90zkcK I+t0VnDEKYf2W2dvQkrzoCXkqyLRx0zxNhdgk52eqxtbGcDGSX7yuq8m7WBGHKsvrLAQ 7XNkTQHd3RGRPSuvpawvrMAanPq/jNCHfVZkYqIf3jJnLF8egkVs1onREwH3jWr3GLjN OielGbtyuLgxmxoxVZ1zfF7IaQkDAYt3GKtWh8pj8hkhsVfbvx6tqnjg0lMMhGfu2t2P GkzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756532818; x=1757137618; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=APFM5mjm/10n5J+KtKVCrzvfw+w3wn4sm2ZqcCK7Dck=; b=BvyEmmJe0+QCtjVkECANBANkVf3i/eHS7DxXd6VqLaGUSerp5A384wtM55ZrlDGi/R otrI2owt39BwH6WRKTEivMSzVsfIdyDQp9ZLA2HF9JfwEAhacgiiZD4tGQEkzfsMBqQl FVr7euPBWhYAZgs0T6DdIUSjjAS/hRcO8MLzEhYoSxtC9JJceA7ulphLcnw5g+z8qxSy f8fqWW7jxq1fqUmyOuZyolz0EszGWD9Xv3sfCIylDhC93ySurpj7G+cOY87lCL59S3gt GOse0Vy6qpkvYD85soIqF7vBDj+S1oGRboK0rkrVF7xZ2bV39fyebhIn7zuMIJujvwO6 y3zQ== X-Gm-Message-State: AOJu0YzaMN8O+ZhK2XY0Z/ja8DQ0Zasn60RCD+GP7dgyjBoqBKsSYUC1 PL48YeaQP4tawBQDufX+w+Pb6uGkSqHTyAG0O7qoMbs4Yuy4V5/fNugsh/+XNCmQp6CyJOQp37K QutRVmcE= X-Gm-Gg: ASbGncuckecf1/LSSulLoBmxYyWs7X1HAyiuo74YPq6vfSK1KwJwPU+QJkzMbsEiVGg ccY8uBbMP/t9FQyBByQRsf3s8TupGYMXfr2TOp6bDzGcgkjt3Q/TA6V4Rmw1qNLuleq3QXkv4EK 8VMIhB3lZl/Mi3eVAs2NtNcRmL/Eg4Ty8Jw8ptgGJbUHOfUK4U/dU9wfK9CPhsqwPbdEDUJu+fA u1Ybe2LivCdsk0Pm3xhhqmDHzJigQiE1PZjG22lFow8/GcnYoksrD7S04yO8URTIqA1YnPf7/Sy lv2TNh87J505foQb0+66hF+9sfVuvMYWMl2IKjuIgI/Wp0yBJUTjAXc9mPmTs56uT9xxD58+Ev9 hSy1GerYNQl7ojYRObCzIdmt1xQ1btNadNG+XBD3hQmhnnwrpexm3l/vQfOKS6gmbGD/V18mt8g == X-Google-Smtp-Source: AGHT+IGOpRhE9pQLGDhZcr2o6Z6SojgAcyfqYi6vsTQdOqpj+tDYl93J6/UoPZpvt6pTlxxcgq6Ktg== X-Received: by 2002:a17:903:2cf:b0:248:9e56:e806 with SMTP id d9443c01a7336-24944870a36mr17350975ad.12.1756532818082; Fri, 29 Aug 2025 22:46:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 50/84] target/arm: Expand pstate to 64 bits Date: Sat, 30 Aug 2025 15:40:54 +1000 Message-ID: <20250830054128.448363-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756574171451116600 Content-Type: text/plain; charset="utf-8" The ARM now defines 36 bits in SPSR_ELx in aarch64 mode, so it's time to bite the bullet and extend PSTATE to match. Most changes are straightforward, adjusting printf formats, changing local variable types. More complex is migration, where to maintain backward compatibility a new pstate64 record is introduced, and only when one of the extensions that sets bits 32-35 are active. The fate of gdbstub is left undecided for the moment. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpu.h | 8 +++--- target/arm/tcg/translate.h | 20 ++++++------- target/arm/cpu.c | 6 ++-- target/arm/gdbstub64.c | 2 ++ target/arm/helper.c | 11 ++++---- target/arm/machine.c | 56 +++++++++++++++++++++++++++++++++++++ target/arm/tcg/helper-a64.c | 2 +- 7 files changed, 82 insertions(+), 23 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6568bca5f9..d5a5152a9c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -268,7 +268,7 @@ typedef struct CPUArchState { uint64_t xregs[32]; uint64_t pc; /* PSTATE isn't an architectural register for ARMv8. However, it is - * convenient for us to assemble the underlying state into a 32 bit fo= rmat + * convenient for us to assemble the underlying state into a 64 bit fo= rmat * identical to the architectural format used for the SPSR. (This is a= lso * what the Linux kernel's 'pstate' field in signal handlers and KVM's * 'pstate' register are.) Of the PSTATE bits: @@ -280,7 +280,7 @@ typedef struct CPUArchState { * SM and ZA are kept in env->svcr * all other bits are stored in their correct places in env->pstate */ - uint32_t pstate; + uint64_t pstate; bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nR= W */ bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ =20 @@ -1547,7 +1547,7 @@ static inline unsigned int aarch64_pstate_mode(unsign= ed int el, bool handler) * interprocessing, so we don't attempt to sync with the cpsr state used by * the 32 bit decoder. */ -static inline uint32_t pstate_read(CPUARMState *env) +static inline uint64_t pstate_read(CPUARMState *env) { int ZF; =20 @@ -1557,7 +1557,7 @@ static inline uint32_t pstate_read(CPUARMState *env) | env->pstate | env->daif | (env->btype << 10); } =20 -static inline void pstate_write(CPUARMState *env, uint32_t val) +static inline void pstate_write(CPUARMState *env, uint64_t val) { env->ZF =3D (~val) & PSTATE_Z; env->NF =3D val; diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 3e63dad2b6..1479f5bf74 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -378,27 +378,27 @@ static inline TCGv_i32 get_ahp_flag(void) } =20 /* Set bits within PSTATE. */ -static inline void set_pstate_bits(uint32_t bits) +static inline void set_pstate_bits(uint64_t bits) { - TCGv_i32 p =3D tcg_temp_new_i32(); + TCGv_i64 p =3D tcg_temp_new_i64(); =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); - tcg_gen_ori_i32(p, p, bits); - tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ori_i64(p, p, bits); + tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* Clear bits within PSTATE. */ -static inline void clear_pstate_bits(uint32_t bits) +static inline void clear_pstate_bits(uint64_t bits) { - TCGv_i32 p =3D tcg_temp_new_i32(); + TCGv_i64 p =3D tcg_temp_new_i64(); =20 tcg_debug_assert(!(bits & CACHED_PSTATE_BITS)); =20 - tcg_gen_ld_i32(p, tcg_env, offsetof(CPUARMState, pstate)); - tcg_gen_andi_i32(p, p, ~bits); - tcg_gen_st_i32(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_ld_i64(p, tcg_env, offsetof(CPUARMState, pstate)); + tcg_gen_andi_i64(p, p, ~bits); + tcg_gen_st_i64(p, tcg_env, offsetof(CPUARMState, pstate)); } =20 /* If the singlestep state is Active-not-pending, advance to Active-pendin= g. */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6673d536bf..1c2ff87b89 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1205,7 +1205,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; - uint32_t psr =3D pstate_read(env); + uint64_t psr =3D pstate_read(env); int i, j; int el =3D arm_current_el(env); uint64_t hcr =3D arm_hcr_el2_eff(env); @@ -1227,7 +1227,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) } else { ns_status =3D ""; } - qemu_fprintf(f, "PSTATE=3D%08x %c%c%c%c %sEL%d%c", + qemu_fprintf(f, "PSTATE=3D%016" PRIx64 " %c%c%c%c %sEL%d%c", psr, psr & PSTATE_N ? 'N' : '-', psr & PSTATE_Z ? 'Z' : '-', @@ -1244,7 +1244,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE= *f, int flags) (FIELD_EX64(env->svcr, SVCR, SM) ? 'S' : '-')); } if (cpu_isar_feature(aa64_bti, cpu)) { - qemu_fprintf(f, " BTYPE=3D%d", (psr & PSTATE_BTYPE) >> 10); + qemu_fprintf(f, " BTYPE=3D%d", (int)(psr & PSTATE_BTYPE) >> 10); } qemu_fprintf(f, "%s%s%s", (hcr & HCR_NV) ? " NV" : "", diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 08e2858539..d0d769df53 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -47,6 +47,7 @@ int aarch64_cpu_gdb_read_register(CPUState *cs, GByteArra= y *mem_buf, int n) case 32: return gdb_get_reg64(mem_buf, env->pc); case 33: + /* pstate is now a 64-bit value; can we simply adjust the xml? */ return gdb_get_reg32(mem_buf, pstate_read(env)); } /* Unknown register. */ @@ -75,6 +76,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cs, uint8_t = *mem_buf, int n) return 8; case 33: /* CPSR */ + /* pstate is now a 64-bit value; can we simply adjust the xml? */ pstate_write(env, tmp); return 4; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 7a23730299..83a7d6ae36 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9079,8 +9079,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) CPUARMState *env =3D &cpu->env; unsigned int new_el =3D env->exception.target_el; vaddr addr =3D env->cp15.vbar_el[new_el]; - unsigned int new_mode =3D aarch64_pstate_mode(new_el, true); - unsigned int old_mode; + uint64_t new_mode =3D aarch64_pstate_mode(new_el, true); + uint64_t old_mode; unsigned int cur_el =3D arm_current_el(env); int rt; =20 @@ -9228,7 +9228,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) * If NV2 is disabled, change SPSR when NV,NV1 =3D=3D 1,0 = (I_ZJRNN) * If NV2 is enabled, change SPSR when NV is 1 (I_DBTLM) */ - old_mode =3D deposit32(old_mode, 2, 2, 2); + old_mode =3D deposit64(old_mode, 2, 2, 2); } } } else { @@ -9241,7 +9241,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) } env->banked_spsr[aarch64_banked_spsr_index(new_el)] =3D old_mode; =20 - qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%x\n", old_mode); + qemu_log_mask(CPU_LOG_INT, "...with SPSR 0x%" PRIx64 "\n", old_mode); qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n", env->elr_el[new_el]); =20 @@ -9295,7 +9295,8 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *cs) =20 env->pc =3D addr; =20 - qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 " PSTATE 0x%x\n", + qemu_log_mask(CPU_LOG_INT, "...to EL%d PC 0x%" PRIx64 + " PSTATE 0x%" PRIx64 "\n", new_el, env->pc, pstate_read(env)); } =20 diff --git a/target/arm/machine.c b/target/arm/machine.c index 8dbeca2867..9b00c14b4a 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -836,6 +836,61 @@ static const VMStateInfo vmstate_cpsr =3D { .put =3D put_cpsr, }; =20 +static int get_pstate64_1(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + uint64_t val =3D qemu_get_be64(f); + + env->aarch64 =3D ((val & PSTATE_nRW) =3D=3D 0); + pstate_write(env, val); + return 0; +} + +static int put_pstate64_1(QEMUFile *f, void *opaque, size_t size, + const VMStateField *field, JSONWriter *vmdesc) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + uint64_t val =3D pstate_read(env); + + qemu_put_be64(f, val); + return 0; +} + +static const VMStateInfo vmstate_pstate64_1 =3D { + .name =3D "pstate64", + .get =3D get_pstate64_1, + .put =3D put_pstate64_1, +}; + +static bool pstate64_needed(void *opaque) +{ + ARMCPU *cpu =3D opaque; + CPUARMState *env =3D &cpu->env; + + return is_a64(env) && pstate_read(env) > UINT32_MAX; +} + +static const VMStateDescription vmstate_pstate64 =3D { + .name =3D "cpu/pstate64", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D pstate64_needed, + .fields =3D (const VMStateField[]) { + { + .name =3D "pstate64", + .version_id =3D 0, + .size =3D sizeof(uint64_t), + .info =3D &vmstate_pstate64_1, + .flags =3D VMS_SINGLE, + .offset =3D 0, + }, + VMSTATE_END_OF_LIST() + }, +}; + static int get_power(QEMUFile *f, void *opaque, size_t size, const VMStateField *field) { @@ -1119,6 +1174,7 @@ const VMStateDescription vmstate_arm_cpu =3D { &vmstate_serror, &vmstate_irq_line_state, &vmstate_wfxt_timer, + &vmstate_pstate64, NULL } }; diff --git a/target/arm/tcg/helper-a64.c b/target/arm/tcg/helper-a64.c index 71c6c44ee8..f61adf1f80 100644 --- a/target/arm/tcg/helper-a64.c +++ b/target/arm/tcg/helper-a64.c @@ -639,7 +639,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) ARMCPU *cpu =3D env_archcpu(env); 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Fri, 29 Aug 2025 22:47:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 51/84] target/arm: Add syndrome data for EC_GCS Date: Sat, 30 Aug 2025 15:40:55 +1000 Message-ID: <20250830054128.448363-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756573125208116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/syndrome.h | 35 +++++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index c48d3b8587..bff61f052c 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -63,6 +63,7 @@ enum arm_exception_class { EC_MOP =3D 0x27, EC_AA32_FPTRAP =3D 0x28, EC_AA64_FPTRAP =3D 0x2c, + EC_GCS =3D 0x2d, EC_SERROR =3D 0x2f, EC_BREAKPOINT =3D 0x30, EC_BREAKPOINT_SAME_EL =3D 0x31, @@ -83,6 +84,23 @@ typedef enum { SME_ET_InaccessibleZT0, } SMEExceptionType; =20 +typedef enum { + GCS_ET_DataCheck, + GCS_ET_EXLOCK, + GCS_ET_GCSSTR_GCSSTTR, +} GCSExceptionType; + +typedef enum { + GCS_IT_RET_nPauth =3D 0, + GCS_IT_GCSPOPM =3D 1, + GCS_IT_RET_PauthA =3D 2, + GCS_IT_RET_PauthB =3D 3, + GCS_IT_GCSSS1 =3D 4, + GCS_IT_GCSSS2 =3D 5, + GCS_IT_GCSPOPCX =3D 8, + GCS_IT_GCSPOPX =3D 9, +} GCSInstructionType; + #define ARM_EL_EC_LENGTH 6 #define ARM_EL_EC_SHIFT 26 #define ARM_EL_IL_SHIFT 25 @@ -351,6 +369,23 @@ static inline uint32_t syn_pcalignment(void) return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_gcs_data_check(GCSInstructionType it, int rn) +{ + return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | + (GCS_ET_DataCheck << 20) | (rn << 5) | it); +} + +static inline uint32_t syn_gcs_exlock(void) +{ + return (EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | (GCS_ET_EXLOCK << 20); +} + +static inline uint32_t syn_gcs_gcsstr(int ra, int rn) +{ + return ((EC_GCS << ARM_EL_EC_SHIFT) | ARM_EL_IL | + (GCS_ET_GCSSTR_GCSSTTR << 20) | (ra << 10) | (rn << 5)); +} + static inline uint32_t syn_serror(uint32_t extra) { return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570685; cv=none; d=zohomail.com; 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Since PSTATE.EXLOCK cannot be set without GCS being present and enabled, no explicit check for GCS is required. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 3 ++ target/arm/cpu.h | 1 + target/arm/helper.c | 83 +++++++++++++++++++++++++++++++++++--- target/arm/tcg/op_helper.c | 4 ++ 4 files changed, 85 insertions(+), 6 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index bc6adf5956..15894332b2 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -346,6 +346,9 @@ typedef enum CPAccessResult { * specified target EL. */ CP_ACCESS_UNDEFINED =3D (2 << 2), + + /* Access fails with EXLOCK, a GCS exception syndrome. */ + CP_ACCESS_EXLOCK =3D (3 << 2), } CPAccessResult; =20 /* Indexes into fgt_read[] */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d5a5152a9c..17902eb40d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1511,6 +1511,7 @@ void pmu_init(ARMCPU *cpu); #define PSTATE_C (1U << 29) #define PSTATE_Z (1U << 30) #define PSTATE_N (1U << 31) +#define PSTATE_EXLOCK (1ULL << 34) #define PSTATE_NZCV (PSTATE_N | PSTATE_Z | PSTATE_C | PSTATE_V) #define PSTATE_DAIF (PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F) #define CACHED_PSTATE_BITS (PSTATE_NZCV | PSTATE_DAIF | PSTATE_BTYPE) diff --git a/target/arm/helper.c b/target/arm/helper.c index 83a7d6ae36..2f19695d82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3432,6 +3432,77 @@ static CPAccessResult access_nv1(CPUARMState *env, c= onst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_exlock_el1(CPUARMState *env, + const ARMCPRegInfo *ri, bool isrea= d) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + /* + * EXLOCK check is disabled for NVx in 'x11'. + * Since we have to diagnose that, dispatch NV1 trap too. + */ + if ((hcr & HCR_NV) && (hcr & HCR_NV1)) { + if (hcr & HCR_NV2) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_EL2; + } + } + + if (!isread && + (env->pstate & PSTATE_EXLOCK) && + (el_is_in_host(env, el) ? el =3D=3D 2 : el =3D=3D 1) && + (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN)) { + return CP_ACCESS_EXLOCK; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_exlock_el2(CPUARMState *env, + const ARMCPRegInfo *ri, bool isrea= d) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 3) { + return CP_ACCESS_OK; + } + if (el =3D=3D 1) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + + /* + * EXLOCK check is disabled for NVx in 'xx1'. + * Since we have to diagnose that, dispatch NV1 trap too. + */ + if (hcr & HCR_NV) { + if (hcr & HCR_NV2) { + return CP_ACCESS_OK; + } + return CP_ACCESS_TRAP_EL2; + } + } + + if (!isread && + (env->pstate & PSTATE_EXLOCK) && + (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN)) { + return CP_ACCESS_EXLOCK; + } + return CP_ACCESS_OK; +} + +static CPAccessResult access_exlock_el3(CPUARMState *env, + const ARMCPRegInfo *ri, bool isrea= d) +{ + if (!isread && + (env->pstate & PSTATE_EXLOCK) && + (env->cp15.gcscr_el[3] & GCSCR_EXLOCKEN)) { + return CP_ACCESS_EXLOCK; + } + return CP_ACCESS_OK; +} + #ifdef CONFIG_USER_ONLY /* * `IC IVAU` is handled to improve compatibility with JITs that dual-map t= heir @@ -3603,13 +3674,13 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { { .name =3D "ELR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, .accessfn =3D access_nv1, + .access =3D PL1_RW, .accessfn =3D access_exlock_el1, .nv2_redirect_offset =3D 0x230 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .accessfn =3D access_nv1, + .access =3D PL1_RW, .accessfn =3D access_exlock_el1, .nv2_redirect_offset =3D 0x160 | NV2_REDIR_NV1, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, /* @@ -4080,7 +4151,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "ELR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS | ARM_CP_NV2_REDIRECT, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, + .access =3D PL2_RW, .accessfn =3D access_exlock_el2, .fieldoffset =3D offsetof(CPUARMState, elr_el[2]) }, { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, .type =3D ARM_CP_NV2_REDIRECT, @@ -4098,7 +4169,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "SPSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS | ARM_CP_NV2_REDIRECT, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, + .access =3D PL2_RW, .accessfn =3D access_exlock_el2, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_HYP]) }, { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, @@ -4380,7 +4451,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "ELR_EL3", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, - .access =3D PL3_RW, + .access =3D PL3_RW, .accessfn =3D access_exlock_el3, .fieldoffset =3D offsetof(CPUARMState, elr_el[3]) }, { .name =3D "ESR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, @@ -4391,7 +4462,7 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { { .name =3D "SPSR_EL3", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, - .access =3D PL3_RW, + .access =3D PL3_RW, .accessfn =3D access_exlock_el3, .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_MON]) }, { .name =3D "VBAR_EL3", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 6, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, diff --git a/target/arm/tcg/op_helper.c b/target/arm/tcg/op_helper.c index 46a3b911ec..56e117c01e 100644 --- a/target/arm/tcg/op_helper.c +++ b/target/arm/tcg/op_helper.c @@ -887,6 +887,10 @@ const void *HELPER(access_check_cp_reg)(CPUARMState *e= nv, uint32_t key, } syndrome =3D syn_uncategorized(); break; + case CP_ACCESS_EXLOCK: + /* CP_ACCESS_EXLOCK is always directed to the current EL */ + syndrome =3D syn_gcs_exlock(); + break; default: g_assert_not_reached(); } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756573088; cv=none; d=zohomail.com; s=zohoarc; b=XWjUz9qtVJLHrMGQnzm1DOPdU6U0m6ffM71ruyhxY1mL2iz8PmIPZqn9ADhScn0elggcy1R1RCG7XbILHVjXJ6VF6q3BeHs9gPHlX4B0zXA6lBnlvgcQaAAXK5j/DiGxdRQ7InYFIgoBtdI64iFzlsBZj9LCJ5TV5NcSbcKZIuM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756573088; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8c73f54e9a..ca1633540f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -93,7 +93,7 @@ void a64_translate_init(void) } =20 /* - * Return the core mmu_idx to use for A64 load/store insns which + * Return the full arm mmu_idx to use for A64 load/store insns which * have a "unprivileged load/store" variant. Those insns access * EL0 if executed from an EL which has control over EL0 (usually * EL1) but behave like normal loads and stores if executed from @@ -103,7 +103,7 @@ void a64_translate_init(void) * normal encoding (in which case we will return the same * thing as get_mem_index(). */ -static int get_a64_user_mem_index(DisasContext *s, bool unpriv) +static ARMMMUIdx arm_user_mem_index(DisasContext *s, bool unpriv) { /* * If AccType_UNPRIV is not used, the insn uses AccType_NORMAL, @@ -130,7 +130,13 @@ static int get_a64_user_mem_index(DisasContext *s, boo= l unpriv) g_assert_not_reached(); } } - return arm_to_core_mmu_idx(useridx); + return useridx; +} + +/* Return the core mmu_idx per above. */ +static int core_user_mem_index(DisasContext *s, bool unpriv) +{ + return arm_to_core_mmu_idx(arm_user_mem_index(s, unpriv)); } =20 static void set_btype_raw(int val) @@ -3539,7 +3545,7 @@ static void op_addr_ldst_imm_pre(DisasContext *s, arg= _ldst_imm *a, if (!a->p) { tcg_gen_addi_i64(*dirty_addr, *dirty_addr, offset); } - memidx =3D get_a64_user_mem_index(s, a->unpriv); + memidx =3D core_user_mem_index(s, a->unpriv); *clean_addr =3D gen_mte_check1_mmuidx(s, *dirty_addr, is_store, a->w || a->rn !=3D 31, mop, a->unpriv, memidx); @@ -3560,7 +3566,7 @@ static bool trans_STR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D get_a64_user_mem_index(s, a->unpriv); + int memidx =3D core_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, true, mop= ); @@ -3578,7 +3584,7 @@ static bool trans_LDR_i(DisasContext *s, arg_ldst_imm= *a) { bool iss_sf, iss_valid =3D !a->w; TCGv_i64 clean_addr, dirty_addr, tcg_rt; - int memidx =3D get_a64_user_mem_index(s, a->unpriv); + int memidx =3D core_user_mem_index(s, a->unpriv); MemOp mop =3D finalize_memop(s, a->sz + a->sign * MO_SIGN); =20 op_addr_ldst_imm_pre(s, a, &clean_addr, &dirty_addr, a->imm, false, mo= p); @@ -4476,7 +4482,7 @@ static bool do_SET(DisasContext *s, arg_set *a, bool = is_epilogue, return false; } =20 - memidx =3D get_a64_user_mem_index(s, a->unpriv); + memidx =3D core_user_mem_index(s, a->unpriv); =20 /* * We pass option_a =3D=3D true, matching our implementation; @@ -4530,8 +4536,8 @@ static bool do_CPY(DisasContext *s, arg_cpy *a, bool = is_epilogue, CpyFn fn) return false; } =20 - rmemidx =3D get_a64_user_mem_index(s, runpriv); - wmemidx =3D get_a64_user_mem_index(s, wunpriv); + rmemidx =3D core_user_mem_index(s, runpriv); + wmemidx =3D core_user_mem_index(s, wunpriv); =20 /* * We pass option_a =3D=3D true, matching our implementation; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate.h | 20 +++++++++++++ target/arm/tcg/translate-a64.c | 2 ++ target/arm/tcg/translate.c | 53 ++++++++++++++++++++++++++++++++++ 3 files changed, 75 insertions(+) diff --git a/target/arm/tcg/translate.h b/target/arm/tcg/translate.h index 1479f5bf74..a40cbd4479 100644 --- a/target/arm/tcg/translate.h +++ b/target/arm/tcg/translate.h @@ -21,9 +21,25 @@ typedef struct DisasLabel { target_ulong pc_save; } DisasLabel; =20 +/* + * Emit an exception call out of line. + */ +typedef struct DisasDelayException { + struct DisasDelayException *next; + TCGLabel *lab; + target_long pc_curr; + target_long pc_save; + int condexec_mask; + int condexec_cond; + uint32_t excp; + uint32_t syn; + uint32_t target_el; +} DisasDelayException; + typedef struct DisasContext { DisasContextBase base; const ARMISARegisters *isar; + DisasDelayException *delay_excp_list; =20 /* The address of the current instruction being translated. */ target_ulong pc_curr; @@ -365,6 +381,10 @@ void gen_exception_insn_el(DisasContext *s, target_lon= g pc_diff, int excp, uint32_t syn, uint32_t target_el); void gen_exception_insn(DisasContext *s, target_long pc_diff, int excp, uint32_t syn); +TCGLabel *delay_exception_el(DisasContext *s, int excp, + uint32_t syn, uint32_t target_el); +TCGLabel *delay_exception(DisasContext *s, int excp, uint32_t syn); +void emit_delayed_exceptions(DisasContext *s); =20 /* Return state of Alternate Half-precision flag, caller frees result */ static inline TCGv_i32 get_ahp_flag(void) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index ca1633540f..1175d37c87 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -10562,6 +10562,8 @@ static void aarch64_tr_tb_stop(DisasContextBase *dc= base, CPUState *cpu) break; } } + + emit_delayed_exceptions(dc); } =20 const TranslatorOps aarch64_translator_ops =3D { diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f7d6d8ce19..c4dd3a747c 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -1090,6 +1090,57 @@ void gen_exception_insn(DisasContext *s, target_long= pc_diff, s->base.is_jmp =3D DISAS_NORETURN; } =20 +TCGLabel *delay_exception_el(DisasContext *s, int excp, + uint32_t syn, uint32_t target_el) +{ + /* Use tcg_malloc for automatic release on longjmp out of translation.= */ + DisasDelayException *e =3D tcg_malloc(sizeof(DisasDelayException)); + + memset(e, 0, sizeof(*e)); + + /* Save enough of the current state to satisfy gen_exception_insn. */ + e->pc_curr =3D s->pc_curr; + e->pc_save =3D s->pc_save; + if (!s->aarch64) { + e->condexec_cond =3D s->condexec_cond; + e->condexec_mask =3D s->condexec_mask; + } + + e->excp =3D excp; + e->syn =3D syn; + e->target_el =3D target_el; + + e->next =3D s->delay_excp_list; + s->delay_excp_list =3D e; + + e->lab =3D gen_new_label(); + return e->lab; +} + +TCGLabel *delay_exception(DisasContext *s, int excp, uint32_t syn) +{ + return delay_exception_el(s, excp, syn, 0); +} + +void emit_delayed_exceptions(DisasContext *s) +{ + for (DisasDelayException *e =3D s->delay_excp_list; e ; e =3D e->next)= { + gen_set_label(e->lab); + + /* Restore the insn state to satisfy gen_exception_insn. */ + s->pc_curr =3D e->pc_curr; + s->pc_save =3D e->pc_save; + s->condexec_cond =3D e->condexec_cond; + s->condexec_mask =3D e->condexec_mask; + + if (e->target_el) { + gen_exception_insn_el(s, 0, e->excp, e->syn, e->target_el); + } else { + gen_exception_insn(s, 0, e->excp, e->syn); + } + } +} + static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { gen_set_condexec(s); @@ -8107,6 +8158,8 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cpu) gen_goto_tb(dc, 1, curr_insn_len(dc)); } } + + emit_delayed_exceptions(dc); } =20 static const TranslatorOps arm_translator_ops =3D { --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756574318; cv=none; d=zohomail.com; s=zohoarc; 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Use TCG_COND_TSTNE instead of separate AND+NE. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate.c | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index c4dd3a747c..f6fdfaa551 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -3033,21 +3033,11 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, =20 if (maskbit !=3D 4 && maskbit !=3D 14) { /* T4 and T14 are RES0 so never cause traps */ - TCGv_i32 t; - DisasLabel over =3D gen_disas_label(s); + TCGLabel *fail =3D delay_exception_el(s, EXCP_UDEF, syndrome, = 2); + TCGv_i32 t =3D + load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2)); =20 - t =3D load_cpu_offset(offsetoflow32(CPUARMState, cp15.hstr_el2= )); - tcg_gen_andi_i32(t, t, 1u << maskbit); - tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); - - gen_exception_insn_el(s, 0, EXCP_UDEF, syndrome, 2); - /* - * gen_exception_insn() will set is_jmp to DISAS_NORETURN, - * but since we're conditionally branching over it, we want - * to assume continue-to-next-instruction. - */ - s->base.is_jmp =3D DISAS_NEXT; - set_disas_label(s, over); + tcg_gen_brcondi_i32(TCG_COND_TSTNE, t, 1u << maskbit, fail); } } =20 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756576736; cv=none; d=zohomail.com; s=zohoarc; b=A4aCW7iuZqN0XmQmTeaW8H0LDmlIEW5BuntNKw6Ctv1u+o6C0pJP92C02KZibeai2La/+019kL0FXnV2C6buROdB9m+ZWd+UX5KhwHJLIU/74Jhq/hK7oi6U+uMK5TPRMExr/77x4ukBLq3kGQ7dENl3+bQ2sFj/DCGgOKWDBfw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756576736; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=1dB1cHT1ha866F85MzBv2WZgn+PHcRylb/+Q2tL/eLA=; b=RcXS+9cs8OJ0pHCZapHHvJxX7rNp7821DRWQGiCP6WmVngHMpU9xjCvgmM8ZE0GkLLx3zC1O/J/jmeFs9HfvJG/+zZULYwlWNuVX/9pG85FcegCwTU1TKCS+SSl3kai28EzI5Hvw2EaVIcklHyKg3krRN+8YnMidZBuLj8O3qbs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756576736770623.5983270489775; Sat, 30 Aug 2025 10:58:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usODn-000527-V6; Sat, 30 Aug 2025 12:14:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEQt-0007Jz-Fm for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:23 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEQr-0004uS-OL for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:23 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-b4c72885c8bso1656063a12.0 for ; Fri, 29 Aug 2025 22:47:16 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:47:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 56/84] target/arm: Emit v7m LTPSIZE exception out of line Date: Sat, 30 Aug 2025 15:41:00 +1000 Message-ID: <20250830054128.448363-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756576737968124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index f6fdfaa551..e787acfc66 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -6885,11 +6885,10 @@ static bool trans_LE(DisasContext *s, arg_LE *a) =20 if (!a->tp && dc_isar_feature(aa32_mve, s) && fpu_active) { /* Need to do a runtime check for LTPSIZE !=3D 4 */ - DisasLabel skipexc =3D gen_disas_label(s); + TCGLabel *fail =3D delay_exception(s, EXCP_INVSTATE, syn_uncategor= ized()); + tmp =3D load_cpu_field(v7m.ltpsize); - tcg_gen_brcondi_i32(TCG_COND_EQ, tmp, 4, skipexc.label); - gen_exception_insn(s, 0, EXCP_INVSTATE, syn_uncategorized()); - set_disas_label(s, skipexc); + tcg_gen_brcondi_i32(TCG_COND_NE, tmp, 4, fail); } =20 if (a->f) { --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 42 ++++++++++++++++++++++++++++++++++ target/arm/tcg/a64.decode | 3 +++ 2 files changed, 45 insertions(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 1175d37c87..022a7c27e3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -139,6 +139,12 @@ static int core_user_mem_index(DisasContext *s, bool u= npriv) return arm_to_core_mmu_idx(arm_user_mem_index(s, unpriv)); } =20 +/* For a given translation regime, return the core mmu_idx for gcs access.= */ +static int core_gcs_mem_index(ARMMMUIdx armidx) +{ + return arm_to_core_mmu_idx(regime_to_gcs(armidx)); +} + static void set_btype_raw(int val) { tcg_gen_st_i32(tcg_constant_i32(val), tcg_env, @@ -3951,6 +3957,42 @@ static bool trans_STLR_i(DisasContext *s, arg_ldapr_= stlr_i *a) return true; } =20 +static bool trans_GCSSTR(DisasContext *s, arg_GCSSTR *a) +{ + ARMMMUIdx armidx; + + if (!dc_isar_feature(aa64_gcs, s)) { + return false; + } + + /* + * The pseudocode for GCSSTTR is + * + * effective_el =3D AArch64.IsUnprivAccessPriv() ? PSTATE.EL : EL0; + * if (effective_el =3D=3D PSTATE.EL) CheckGCSSTREnabled(); + * + * We have cached the result of IsUnprivAccessPriv in DisasContext, + * but since we need the result of arm_user_mem_index anyway, use + * the mmu_idx test as a proxy for the effective_el test. + */ + armidx =3D arm_user_mem_index(s, a->unpriv); + if (armidx =3D=3D s->mmu_idx && s->gcsstr_el !=3D 0) { + gen_exception_insn_el(s, 0, EXCP_UDEF, + syn_gcs_gcsstr(a->rn, a->rt), + s->gcsstr_el); + return true; + } + + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + tcg_gen_qemu_st_i64(cpu_reg(s, a->rt), + clean_data_tbi(s, cpu_reg_sp(s, a->rn)), + core_gcs_mem_index(armidx), + finalize_memop(s, MO_64 | MO_ALIGN)); + return true; +} + static bool trans_LD_mult(DisasContext *s, arg_ldst_mult *a) { TCGv_i64 clean_addr, tcg_rn, tcg_ebytes; diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8283a9c83d..2ae73f443a 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -571,6 +571,9 @@ LDAPR_i 10 011001 10 0 ......... 00 ..... .....= @ldapr_stlr_i sign=3D1 ext LDAPR_i 00 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D0 LDAPR_i 01 011001 11 0 ......... 00 ..... ..... @ldapr_stlr_i sign= =3D1 ext=3D1 sz=3D1 =20 +# GCSSTR, GCSSTTR +GCSSTR 11011001 000 11111 000 unpriv:1 11 rn:5 rt:5 + # Load/store multiple structures # The 4-bit opcode in [15:12] encodes repeat count and structure elements &ldst_mult rm rn rt sz q p rpt selem --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756575333; cv=none; d=zohomail.com; s=zohoarc; b=oL2KWiQzin2XdyL/tc/JJ32MZ5FHntPXLlAfDc6nKH9Q0bVJKtRr3zB3zwcsA/OYHxhjzbeOffLTNI09hUuJpaaoAchkOymZpc4+0pWC3OCKUkYhOB/ZEWektOxWrwVQmwY5fKaSImBeqNTV91sj+4QtUZLqI3y+FhoOgDlk7B4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756575333; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=hYJJNkCVSQ5j5v2XBrKXrPA82mG4YwUVjAuTO3fF/o0=; b=XP3Oaf1THDsneCX7BkwwnFK5yLIWx8yfwNQgcqCNO74ZZVFUt/zi9/uuXWcFltJwQvvacpy3EL+xtgFdPCTofR4TP6XeYK2LTmn3HXdaqGh9/2Ms3f9aBuyWoZmG/Vr0pZKAvkTbj4hrEAto/NWrxUkFxzETL42WzUMHhXFEp/E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756575333688429.8194904468444; Sat, 30 Aug 2025 10:35:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNyQ-0006C4-4K; Sat, 30 Aug 2025 11:58:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEQw-0007Kp-AG for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:28 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEQs-0004uv-39 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:26 -0400 Received: by mail-pl1-x635.google.com with SMTP id d9443c01a7336-248a638dbbeso24949965ad.2 for ; Fri, 29 Aug 2025 22:47:21 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:47:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 58/84] target/arm: Implement GCSB Date: Sat, 30 Aug 2025 15:41:02 +1000 Message-ID: <20250830054128.448363-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756575335731116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 8 ++++++++ target/arm/tcg/a64.decode | 1 + 2 files changed, 9 insertions(+) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 022a7c27e3..84c62fdb4e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2072,6 +2072,14 @@ static bool trans_ESB(DisasContext *s, arg_ESB *a) return true; } =20 +static bool trans_GCSB(DisasContext *s, arg_GCSB *a) +{ + if (dc_isar_feature(aa64_gcs, s)) { + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + } + return true; +} + static bool trans_PACIAZ(DisasContext *s, arg_PACIAZ *a) { if (s->pauth_active) { diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 2ae73f443a..01b1b3e38b 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -248,6 +248,7 @@ ERETA 1101011 0100 11111 00001 m:1 11111 1111= 1 &reta # ERETAA, ERETAB AUTIA1716 1101 0101 0000 0011 0010 0001 100 11111 AUTIB1716 1101 0101 0000 0011 0010 0001 110 11111 ESB 1101 0101 0000 0011 0010 0010 000 11111 + GCSB 1101 0101 0000 0011 0010 0010 011 11111 PACIAZ 1101 0101 0000 0011 0010 0011 000 11111 PACIASP 1101 0101 0000 0011 0010 0011 001 11111 PACIBZ 1101 0101 0000 0011 0010 0011 010 11111 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 22:47:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v4 59/84] target/arm: Implement GCSPUSHM Date: Sat, 30 Aug 2025 15:41:03 +1000 Message-ID: <20250830054128.448363-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756576147720124100 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 3 +++ target/arm/cpregs-gcs.c | 15 +++++++++++++++ target/arm/tcg/translate-a64.c | 29 +++++++++++++++++++++++++++++ 3 files changed, 47 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 15894332b2..93358e6123 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -46,6 +46,8 @@ enum { ARM_CP_DC_ZVA =3D 0x0005, ARM_CP_DC_GVA =3D 0x0006, ARM_CP_DC_GZVA =3D 0x0007, + /* Special: gcs instructions */ + ARM_CP_GCSPUSHM =3D 0x0008, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, @@ -861,6 +863,7 @@ typedef enum FGTBit { DO_BIT(HFGITR, DVPRCTX), DO_BIT(HFGITR, CPPRCTX), DO_BIT(HFGITR, DCCVAC), + DO_REV_BIT(HFGITR, NGCSPUSHM_EL1), DO_BIT(HFGITR, ATS1E1A), } FGTBit; =20 diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index 1a64acd584..d17c17dcb7 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -43,6 +43,16 @@ static void gcspr_write(CPUARMState *env, const ARMCPReg= Info *ri, raw_write(env, ri, value & ~7); } =20 +static CPAccessResult access_gcspushm(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + int el =3D arm_current_el(env); + if (!(env->cp15.gcscr_el[el] & GCSCR_PUSHMEN)) { + return CP_ACCESS_TRAP_BIT | (el ? el : 1); + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, @@ -81,6 +91,11 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 6, .crn =3D 2, .crm =3D 5, .opc2 =3D 1, .access =3D PL3_RW, .writefn =3D gcspr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.gcspr_el[2]) }, + + { .name =3D "GCSPUSHM", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 0, + .access =3D PL0_W, .accessfn =3D access_gcspushm, + .fgt =3D FGT_NGCSPUSHM_EL1, .type =3D ARM_CP_GCSPUSHM }, }; =20 void define_gcs_cpregs(ARMCPU *cpu) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 84c62fdb4e..0d2df839f6 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -26,6 +26,7 @@ #include "cpregs.h" =20 static TCGv_i64 cpu_X[32]; +static TCGv_i64 cpu_gcspr[32]; static TCGv_i64 cpu_pc; =20 /* Load/store exclusive handling */ @@ -77,6 +78,10 @@ static int scale_by_log2_tag_granule(DisasContext *s, in= t x) /* initialize TCG globals. */ void a64_translate_init(void) { + static const char gcspr_names[4][12] =3D { + "gcspr_el0", "gcspr_el1", "gcspr_el2", "gcspr_el3" + }; + int i; =20 cpu_pc =3D tcg_global_mem_new_i64(tcg_env, @@ -90,6 +95,13 @@ void a64_translate_init(void) =20 cpu_exclusive_high =3D tcg_global_mem_new_i64(tcg_env, offsetof(CPUARMState, exclusive_high), "exclusive_high"); + + for (i =3D 0; i < 4; i++) { + cpu_gcspr[i] =3D + tcg_global_mem_new_i64(tcg_env, + offsetof(CPUARMState, cp15.gcspr_el[i]), + gcspr_names[i]); + } } =20 /* @@ -420,6 +432,18 @@ static MemOp check_ordered_align(DisasContext *s, int = rn, int imm, return finalize_memop(s, mop); } =20 +static void gen_add_gcs_record(DisasContext *s, TCGv_i64 value) +{ + TCGv_i64 addr =3D tcg_temp_new_i64(); + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; 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Fri, 29 Aug 2025 22:47:25 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 60/84] target/arm: Implement GCSPOPM Date: Sat, 30 Aug 2025 15:41:04 +1000 Message-ID: <20250830054128.448363-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756571867746116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 3 +++ target/arm/tcg/translate-a64.c | 24 ++++++++++++++++++++++++ 3 files changed, 28 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 93358e6123..9b19520346 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -48,6 +48,7 @@ enum { ARM_CP_DC_GZVA =3D 0x0007, /* Special: gcs instructions */ ARM_CP_GCSPUSHM =3D 0x0008, + ARM_CP_GCSPOPM =3D 0x0009, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index d17c17dcb7..fdefb2e17a 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -96,6 +96,9 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 0, .access =3D PL0_W, .accessfn =3D access_gcspushm, .fgt =3D FGT_NGCSPUSHM_EL1, .type =3D ARM_CP_GCSPUSHM }, + { .name =3D "GCSPOPM", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 1, + .access =3D PL0_R, .type =3D ARM_CP_GCSPOPM }, }; =20 void define_gcs_cpregs(ARMCPU *cpu) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 0d2df839f6..badc24d2a5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2513,6 +2513,24 @@ static void gen_sysreg_undef(DisasContext *s, bool i= sread, gen_exception_insn(s, 0, EXCP_UDEF, syndrome); } =20 +static void gen_gcspopm(DisasContext *s, int rt) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 value =3D tcg_temp_new_i64(); + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSPOPM, r= t)); + + /* The value at top-of-stack must have low 2 bits clear. */ + tcg_gen_qemu_ld_i64(value, clean_data_tbi(s, gcspr), mmuidx, mop); + tcg_gen_brcondi_i64(TCG_COND_TSTNE, value, 3, fail_label); + + /* Complete the pop and return the value. */ + tcg_gen_addi_i64(gcspr, gcspr, 8); + tcg_gen_mov_i64(cpu_reg(s, rt), value); +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2794,6 +2812,12 @@ static void handle_sys(DisasContext *s, bool isread, gen_add_gcs_record(s, cpu_reg(s, rt)); } return; + case ARM_CP_GCSPOPM: + /* Note that X[rt] is unchanged if !GCSEnabled. */ + if (s->gcs_en) { + gen_gcspopm(s, rt); + } + return; default: g_assert_not_reached(); } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756573016; cv=none; d=zohomail.com; s=zohoarc; b=QCfRMejp2CE7hShevghM0dNRiGMx8+OXZv3OBfXWGgxOYtUSnpaWi7XlcmaXwnlUqOZey4RUvrbU/WwmhD8uDmp82DWfy3ND+COTClnkpIDr7cn5dFaEp66RjtEi1ydVHTdMOESUTdNscCxLMqeBEwgbxydmHdHjwU2beQaoSJE= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 22:47:27 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 61/84] target/arm: Implement GCSPUSHX Date: Sat, 30 Aug 2025 15:41:05 +1000 Message-ID: <20250830054128.448363-62-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756573017967116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 2 ++ target/arm/cpregs-gcs.c | 17 ++++++++++++++++ target/arm/tcg/translate-a64.c | 37 ++++++++++++++++++++++++++++++++++ 3 files changed, 56 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 9b19520346..3d76afd20b 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -49,6 +49,7 @@ enum { /* Special: gcs instructions */ ARM_CP_GCSPUSHM =3D 0x0008, ARM_CP_GCSPOPM =3D 0x0009, + ARM_CP_GCSPUSHX =3D 0x000a, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, @@ -865,6 +866,7 @@ typedef enum FGTBit { DO_BIT(HFGITR, CPPRCTX), DO_BIT(HFGITR, DCCVAC), DO_REV_BIT(HFGITR, NGCSPUSHM_EL1), + DO_REV_BIT(HFGITR, NGCSEPP), DO_BIT(HFGITR, ATS1E1A), } FGTBit; =20 diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index fdefb2e17a..c688d0c391 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -53,6 +53,19 @@ static CPAccessResult access_gcspushm(CPUARMState *env, = const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_gcspushx(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + /* Trap if lock taken, and enabled. */ + if (!(env->pstate & PSTATE_EXLOCK)) { + int el =3D arm_current_el(env); + if (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN) { + return CP_ACCESS_EXLOCK; + } + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, @@ -99,6 +112,10 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSPOPM", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 1, .access =3D PL0_R, .type =3D ARM_CP_GCSPOPM }, + { .name =3D "GCSPUSHX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 4, + .access =3D PL1_W, .accessfn =3D access_gcspushx, .fgt =3D FGT_NGCSE= PP, + .type =3D ARM_CP_GCSPUSHX }, }; =20 void define_gcs_cpregs(ARMCPU *cpu) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index badc24d2a5..e5d9a6e837 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2531,6 +2531,35 @@ static void gen_gcspopm(DisasContext *s, int rt) tcg_gen_mov_i64(cpu_reg(s, rt), value); } =20 +static void gen_gcspushx(DisasContext *s) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int spsr_idx =3D aarch64_banked_spsr_index(s->current_el); + int spsr_off =3D offsetof(CPUARMState, banked_spsr[spsr_idx]); + int elr_off =3D offsetof(CPUARMState, elr_el[s->current_el]); + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 addr =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); + + tcg_gen_addi_i64(addr, gcspr, -8); + tcg_gen_qemu_st_i64(cpu_reg(s, 30), addr, mmuidx, mop); + + tcg_gen_ld_i64(tmp, tcg_env, spsr_off); + tcg_gen_addi_i64(addr, addr, -8); + tcg_gen_qemu_st_i64(tmp, addr, mmuidx, mop); + + tcg_gen_ld_i64(tmp, tcg_env, elr_off); + tcg_gen_addi_i64(addr, addr, -8); + tcg_gen_qemu_st_i64(tmp, addr, mmuidx, mop); + + tcg_gen_addi_i64(addr, addr, -8); + tcg_gen_qemu_st_i64(tcg_constant_i64(0b1001), addr, mmuidx, mop); + + tcg_gen_mov_i64(gcspr, addr); + clear_pstate_bits(PSTATE_EXLOCK); +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2818,6 +2847,14 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcspopm(s, rt); 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Fri, 29 Aug 2025 22:47:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 62/84] target/arm: Implement GCSPOPX Date: Sat, 30 Aug 2025 15:41:06 +1000 Message-ID: <20250830054128.448363-63-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756574503275124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 3 +++ target/arm/tcg/translate-a64.c | 35 ++++++++++++++++++++++++++++++++++ 3 files changed, 39 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 3d76afd20b..084ea00e51 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -50,6 +50,7 @@ enum { ARM_CP_GCSPUSHM =3D 0x0008, ARM_CP_GCSPOPM =3D 0x0009, ARM_CP_GCSPUSHX =3D 0x000a, + ARM_CP_GCSPOPX =3D 0x000b, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index c688d0c391..2d39b17188 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -116,6 +116,9 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 4, .access =3D PL1_W, .accessfn =3D access_gcspushx, .fgt =3D FGT_NGCSE= PP, .type =3D ARM_CP_GCSPUSHX }, + { .name =3D "GCSPOPX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 6, + .access =3D PL1_W, .type =3D ARM_CP_GCSPOPX }, }; =20 void define_gcs_cpregs(ARMCPU *cpu) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e5d9a6e837..b0a1a62a91 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2560,6 +2560,33 @@ static void gen_gcspushx(DisasContext *s) clear_pstate_bits(PSTATE_EXLOCK); } =20 +static void gen_gcspopx(DisasContext *s) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 addr =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSPOPX, 3= 1)); + + /* The value at top-of-stack must be an exception token. */ + tcg_gen_qemu_ld_i64(tmp, gcspr, mmuidx, mop); + tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 0b1001, fail_label); + + /* + * The other three values in the exception return record + * are ignored, but are loaded anyway to raise faults. + */ + tcg_gen_addi_i64(addr, gcspr, 8); + tcg_gen_qemu_ld_i64(tmp, addr, mmuidx, mop); + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(tmp, addr, mmuidx, mop); + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(tmp, addr, mmuidx, mop); + tcg_gen_addi_i64(gcspr, addr, 8); +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2855,6 +2882,14 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcspushx(s); } return; + case ARM_CP_GCSPOPX: + /* Choose the CONSTRAINED UNPREDICTABLE for UNDEF. */ + if (rt !=3D 31) { + unallocated_encoding(s); + } else if (s->gcs_en) { + gen_gcspopx(s); + } + return; default: g_assert_not_reached(); } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Fri, 29 Aug 2025 22:47:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 63/84] target/arm: Implement GCSPOPCX Date: Sat, 30 Aug 2025 15:41:07 +1000 Message-ID: <20250830054128.448363-64-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756570145334116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 17 +++++++++++ target/arm/tcg/translate-a64.c | 56 ++++++++++++++++++++++++++++++++++ 3 files changed, 74 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 084ea00e51..392a0a264f 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -51,6 +51,7 @@ enum { ARM_CP_GCSPOPM =3D 0x0009, ARM_CP_GCSPUSHX =3D 0x000a, ARM_CP_GCSPOPX =3D 0x000b, + ARM_CP_GCSPOPCX =3D 0x000c, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index 2d39b17188..3236f607f3 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -66,6 +66,19 @@ static CPAccessResult access_gcspushx(CPUARMState *env, = const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +static CPAccessResult access_gcspopcx(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + /* Trap if lock not taken, and enabled. */ + if (env->pstate & PSTATE_EXLOCK) { + int el =3D arm_current_el(env); + if (env->cp15.gcscr_el[el] & GCSCR_EXLOCKEN) { + return CP_ACCESS_EXLOCK; + } + } + return CP_ACCESS_OK; +} + static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSCRE0_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 5, .opc2 =3D 2, @@ -116,6 +129,10 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 4, .access =3D PL1_W, .accessfn =3D access_gcspushx, .fgt =3D FGT_NGCSE= PP, .type =3D ARM_CP_GCSPUSHX }, + { .name =3D "GCSPOPCX", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 5, + .access =3D PL1_W, .accessfn =3D access_gcspopcx, .fgt =3D FGT_NGCSE= PP, + .type =3D ARM_CP_GCSPOPCX }, { .name =3D "GCSPOPX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 6, .access =3D PL1_W, .type =3D ARM_CP_GCSPOPX }, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index b0a1a62a91..193c199a2e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2560,6 +2560,54 @@ static void gen_gcspushx(DisasContext *s) clear_pstate_bits(PSTATE_EXLOCK); } =20 +static void gen_gcspopcx(DisasContext *s) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int spsr_idx =3D aarch64_banked_spsr_index(s->current_el); + int spsr_off =3D offsetof(CPUARMState, banked_spsr[spsr_idx]); + int elr_off =3D offsetof(CPUARMState, elr_el[s->current_el]); + int gcscr_off =3D offsetof(CPUARMState, cp15.gcscr_el[s->current_el]); + int pstate_off =3D offsetof(CPUARMState, pstate); + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 addr =3D tcg_temp_new_i64(); + TCGv_i64 tmp1 =3D tcg_temp_new_i64(); + TCGv_i64 tmp2 =3D tcg_temp_new_i64(); + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSPOPCX, = 31)); + + /* The value at top-of-stack must be an exception token. */ + tcg_gen_qemu_ld_i64(tmp1, gcspr, mmuidx, mop); + tcg_gen_brcondi_i64(TCG_COND_NE, tmp1, 0b1001, fail_label); + + /* Validate in turn, ELR ... */ + tcg_gen_addi_i64(addr, gcspr, 8); + tcg_gen_qemu_ld_i64(tmp1, addr, mmuidx, mop); + tcg_gen_ld_i64(tmp2, tcg_env, elr_off); + tcg_gen_brcond_i64(TCG_COND_NE, tmp1, tmp2, fail_label); + + /* ... SPSR ... */ + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(tmp1, addr, mmuidx, mop); + tcg_gen_ld_i64(tmp2, tcg_env, spsr_off); + tcg_gen_brcond_i64(TCG_COND_NE, tmp1, tmp2, fail_label); + + /* ... and LR. */ + tcg_gen_addi_i64(addr, addr, 8); + tcg_gen_qemu_ld_i64(tmp1, addr, mmuidx, mop); + tcg_gen_brcond_i64(TCG_COND_NE, tmp1, cpu_reg(s, 30), fail_label); + + /* Writeback stack pointer after pop. */ + tcg_gen_addi_i64(gcspr, addr, 8); + + /* PSTATE.EXLOCK =3D GetCurrentEXLOCKEN(). */ + tcg_gen_ld_i64(tmp1, tcg_env, gcscr_off); + tcg_gen_ld_i64(tmp2, tcg_env, pstate_off); + tcg_gen_shri_i64(tmp1, tmp1, ctz64(GCSCR_EXLOCKEN)); + tcg_gen_deposit_i64(tmp2, tmp2, tmp1, ctz64(PSTATE_EXLOCK), 1); + tcg_gen_st_i64(tmp2, tcg_env, pstate_off); +} + static void gen_gcspopx(DisasContext *s) { TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; @@ -2882,6 +2930,14 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcspushx(s); } return; + case ARM_CP_GCSPOPCX: + /* Choose the CONSTRAINED UNPREDICTABLE for UNDEF. */ + if (rt !=3D 31) { + unallocated_encoding(s); + } else if (s->gcs_en) { + gen_gcspopcx(s); + } + return; case ARM_CP_GCSPOPX: /* Choose the CONSTRAINED UNPREDICTABLE for UNDEF. */ if (rt !=3D 31) { --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756575533; cv=none; d=zohomail.com; s=zohoarc; b=MDRcwF642NiyXJpcIyeZWyZ70F5n51sQgIBcg75IpgZclnMMJNG0La8C7/qMiijwBt61UVbDNmdAKMjlCzUQ04SCDbjM/a4uhWFktfmO79oJSslqLeJ42Ocfb4Gcel8mzn92Tr0HKLJlsfKlghKM7ddTRYgBleLKx95nR5wek7U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756575533; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=bTDxsYCgOOY4AQ9WMuAsrWuHfULMfhqIx78Righ9ppA=; b=Eid5NUoIsJVR4mIwOvn8GlWzGjE9Wr4PejDr2xPat/GK9pOvugC0XHXCKNmRMPgA9V7gXHiQKbhray/kIcxt/UgSJdMnw0JRum3Sj2u20yATT+mUEZlZh8mfZNB9bKZiEWdgKwY7hPN1LySWQqHHYLsnxY9gCQWIvor+pvEpb0g= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756575533835777.2596043691921; Sat, 30 Aug 2025 10:38:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNyL-00062X-3o; Sat, 30 Aug 2025 11:58:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usERA-0007OO-46 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:44 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usER7-0004yQ-Bt for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:39 -0400 Received: by mail-pl1-x629.google.com with SMTP id d9443c01a7336-248e3ef1641so17134785ad.3 for ; Fri, 29 Aug 2025 22:47:36 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:47:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 64/84] target/arm: Implement GCSSS1 Date: Sat, 30 Aug 2025 15:41:08 +1000 Message-ID: <20250830054128.448363-65-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756575536042116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 3 +++ target/arm/tcg/translate-a64.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 34 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 392a0a264f..ee8b870e17 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -52,6 +52,7 @@ enum { ARM_CP_GCSPUSHX =3D 0x000a, ARM_CP_GCSPOPX =3D 0x000b, ARM_CP_GCSPOPCX =3D 0x000c, + ARM_CP_GCSSS1 =3D 0x000d, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index 3236f607f3..51fc8298af 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -125,6 +125,9 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSPOPM", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 1, .access =3D PL0_R, .type =3D ARM_CP_GCSPOPM }, + { .name =3D "GCSSS1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 2, + .access =3D PL0_W, .type =3D ARM_CP_GCSSS1 }, { .name =3D "GCSPUSHX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 4, .access =3D PL1_W, .accessfn =3D access_gcspushx, .fgt =3D FGT_NGCSE= PP, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 193c199a2e..e0ce2bd0a3 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2635,6 +2635,31 @@ static void gen_gcspopx(DisasContext *s) tcg_gen_addi_i64(gcspr, addr, 8); } =20 +static void gen_gcsss1(DisasContext *s, int rt) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 inptr =3D cpu_reg(s, rt); + TCGv_i64 cmp =3D tcg_temp_new_i64(); + TCGv_i64 new =3D tcg_temp_new_i64(); + TCGv_i64 old =3D tcg_temp_new_i64(); + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSSS1, rt= )); + + /* Compute the valid cap entry that the new stack must have. */ + tcg_gen_deposit_i64(cmp, inptr, tcg_constant_i64(1), 0, 12); + /* Compute the in-progress cap entry for the old stack. */ + tcg_gen_deposit_i64(new, gcspr, tcg_constant_i64(5), 0, 3); + + /* Swap the valid cap the with the in-progress cap. */ + tcg_gen_atomic_cmpxchg_i64(old, inptr, cmp, new, mmuidx, mop); + tcg_gen_brcond_i64(TCG_COND_NE, old, cmp, fail_label); + + /* The new stack had a valid cap: change gcspr. */ + tcg_gen_andi_i64(gcspr, inptr, ~7); +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2946,6 +2971,11 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcspopx(s); } return; + case ARM_CP_GCSSS1: + if (s->gcs_en) { + gen_gcsss1(s, rt); + } + return; default: g_assert_not_reached(); } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756575553; cv=none; d=zohomail.com; s=zohoarc; b=M0dB8QLEJe1UBPlzJ5OhtSjQughPCh7KUOfIRMoXgiukYdmkKM/kopgVHhralV62PQc9plbOfiNPOWFNoYMhs3g18Btxth+SQvpwLgqWZMGq+f3e+ezr5ut4yumik3ZsEXQJZk0arm0LqVpj9knJ0iC90MZkWhC+3a1tKhIMSCA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756575553; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 29 Aug 2025 22:47:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 65/84] target/arm: Implement GCSSS2 Date: Sat, 30 Aug 2025 15:41:09 +1000 Message-ID: <20250830054128.448363-66-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756575554496116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 1 + target/arm/cpregs-gcs.c | 3 +++ target/arm/tcg/translate-a64.c | 34 ++++++++++++++++++++++++++++++++++ 3 files changed, 38 insertions(+) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index ee8b870e17..1ee0bfd132 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -53,6 +53,7 @@ enum { ARM_CP_GCSPOPX =3D 0x000b, ARM_CP_GCSPOPCX =3D 0x000c, ARM_CP_GCSSS1 =3D 0x000d, + ARM_CP_GCSSS2 =3D 0x000e, =20 /* Flag: reads produce resetvalue; writes ignored. */ ARM_CP_CONST =3D 1 << 4, diff --git a/target/arm/cpregs-gcs.c b/target/arm/cpregs-gcs.c index 51fc8298af..b70bf47fc6 100644 --- a/target/arm/cpregs-gcs.c +++ b/target/arm/cpregs-gcs.c @@ -128,6 +128,9 @@ static const ARMCPRegInfo gcs_reginfo[] =3D { { .name =3D "GCSSS1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 2, .access =3D PL0_W, .type =3D ARM_CP_GCSSS1 }, + { .name =3D "GCSSS2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 7, .opc2 =3D 3, + .access =3D PL0_R, .type =3D ARM_CP_GCSSS2 }, { .name =3D "GCSPUSHX", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 7, .opc2 =3D 4, .access =3D PL1_W, .accessfn =3D access_gcspushx, .fgt =3D FGT_NGCSE= PP, diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index e0ce2bd0a3..481e748ce0 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2660,6 +2660,35 @@ static void gen_gcsss1(DisasContext *s, int rt) tcg_gen_andi_i64(gcspr, inptr, ~7); } =20 +static void gen_gcsss2(DisasContext *s, int rt) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 outptr =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(GCS_IT_GCSSS2, rt= )); + + /* Validate that the new stack has an in-progress cap. */ + tcg_gen_qemu_ld_i64(outptr, gcspr, mmuidx, mop); + tcg_gen_andi_i64(tmp, outptr, 7); + tcg_gen_brcondi_i64(TCG_COND_NE, tmp, 5, fail_label); + + /* Push a valid cap to the old stack. */ + tcg_gen_andi_i64(outptr, outptr, ~7); + tcg_gen_addi_i64(outptr, outptr, -8); + tcg_gen_deposit_i64(tmp, outptr, tcg_constant_i64(1), 0, 12); + tcg_gen_qemu_st_i64(tmp, outptr, mmuidx, mop); + tcg_gen_mb(TCG_BAR_SC | TCG_MO_ALL); + + /* Pop the in-progress cap from the new stack. */ + tcg_gen_addi_i64(gcspr, gcspr, 8); + + /* Return a pointer to the old stack cap. */ + tcg_gen_mov_i64(cpu_reg(s, rt), outptr); +} + /* MRS - move from system register * MSR (register) - move to system register * SYS @@ -2976,6 +3005,11 @@ static void handle_sys(DisasContext *s, bool isread, gen_gcsss1(s, rt); } return; + case ARM_CP_GCSSS2: + if (s->gcs_en) { + gen_gcsss2(s, rt); + } + return; default: g_assert_not_reached(); } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756569840; cv=none; d=zohomail.com; s=zohoarc; b=iYFFxZDZQ6ap54+ZaGaqrZxwKC1PRRWlQBtbTubkqnbhJ028FFcmbYduEB/H7XK/jJgWoEIuiarpflFJItUlm2tv2OFR37Afoj7O4Fr0y/hfuIDb9VRPfa7CJoneP34fE3aKM1PEwLzlqThP/08s2BAcKg0ARqiE+yKFN1qhJ80= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569840; 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Fri, 29 Aug 2025 22:47:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 66/84] target/arm: Add gcs record for BL Date: Sat, 30 Aug 2025 15:41:10 +1000 Message-ID: <20250830054128.448363-67-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756569842328124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 481e748ce0..336aac9d1e 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1678,7 +1678,14 @@ static bool trans_B(DisasContext *s, arg_i *a) =20 static bool trans_BL(DisasContext *s, arg_i *a) { - gen_pc_plus_diff(s, cpu_reg(s, 30), curr_insn_len(s)); + TCGv_i64 link =3D tcg_temp_new_i64(); + + gen_pc_plus_diff(s, link, 4); + if (s->gcs_en) { + gen_add_gcs_record(s, link); + } + tcg_gen_mov_i64(cpu_reg(s, 30), link); + reset_btype(s); gen_goto_tb(s, 0, a->imm); return true; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 29 Aug 2025 22:47:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 67/84] target/arm: Add gcs record for BLR Date: Sat, 30 Aug 2025 15:41:11 +1000 Message-ID: <20250830054128.448363-68-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756572833481116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 336aac9d1e..8230ac0fab 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1782,15 +1782,15 @@ static bool trans_BR(DisasContext *s, arg_r *a) =20 static bool trans_BLR(DisasContext *s, arg_r *a) { - TCGv_i64 dst =3D cpu_reg(s, a->rn); - TCGv_i64 lr =3D cpu_reg(s, 30); - if (dst =3D=3D lr) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(tmp, dst); - dst =3D tmp; + TCGv_i64 link =3D tcg_temp_new_i64(); + + gen_pc_plus_diff(s, link, 4); + if (s->gcs_en) { + gen_add_gcs_record(s, link); } - gen_pc_plus_diff(s, lr, curr_insn_len(s)); - gen_a64_set_pc(s, dst); + gen_a64_set_pc(s, cpu_reg(s, a->rn)); + tcg_gen_mov_i64(cpu_reg(s, 30), link); + set_btype_for_blr(s); s->base.is_jmp =3D DISAS_JUMP; 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Fri, 29 Aug 2025 22:47:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 68/84] target/arm: Add gcs record for BLR with PAuth Date: Sat, 30 Aug 2025 15:41:12 +1000 Message-ID: <20250830054128.448363-69-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756576845246116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 31 ++++++++++++++++--------------- 1 file changed, 16 insertions(+), 15 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 8230ac0fab..20e18687d5 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1842,20 +1842,20 @@ static bool trans_BRAZ(DisasContext *s, arg_braz *a) =20 static bool trans_BLRAZ(DisasContext *s, arg_braz *a) { - TCGv_i64 dst, lr; + TCGv_i64 dst, link; =20 if (!dc_isar_feature(aa64_pauth, s)) { return false; } - dst =3D auth_branch_target(s, cpu_reg(s, a->rn), tcg_constant_i64(0), = !a->m); - lr =3D cpu_reg(s, 30); - if (dst =3D=3D lr) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(tmp, dst); - dst =3D tmp; + + link =3D tcg_temp_new_i64(); + gen_pc_plus_diff(s, link, 4); + if (s->gcs_en) { + gen_add_gcs_record(s, link); } - gen_pc_plus_diff(s, lr, curr_insn_len(s)); + tcg_gen_mov_i64(cpu_reg(s, 30), link); + gen_a64_set_pc(s, dst); set_btype_for_blr(s); s->base.is_jmp =3D DISAS_JUMP; @@ -1892,19 +1892,20 @@ static bool trans_BRA(DisasContext *s, arg_bra *a) =20 static bool trans_BLRA(DisasContext *s, arg_bra *a) { - TCGv_i64 dst, lr; + TCGv_i64 dst, link; =20 if (!dc_isar_feature(aa64_pauth, s)) { return false; } dst =3D auth_branch_target(s, cpu_reg(s, a->rn), cpu_reg_sp(s, a->rm),= !a->m); - lr =3D cpu_reg(s, 30); - if (dst =3D=3D lr) { - TCGv_i64 tmp =3D tcg_temp_new_i64(); - tcg_gen_mov_i64(tmp, dst); - dst =3D tmp; + + link =3D tcg_temp_new_i64(); + gen_pc_plus_diff(s, link, 4); + if (s->gcs_en) { + gen_add_gcs_record(s, link); } - gen_pc_plus_diff(s, lr, curr_insn_len(s)); + tcg_gen_mov_i64(cpu_reg(s, 30), link); + gen_a64_set_pc(s, dst); set_btype_for_blr(s); s->base.is_jmp =3D DISAS_JUMP; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 29 Aug 2025 22:47:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 69/84] target/arm: Load gcs record for RET Date: Sat, 30 Aug 2025 15:41:13 +1000 Message-ID: <20250830054128.448363-70-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756577035501124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 29 ++++++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 20e18687d5..3ddf4bb018 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -444,6 +444,27 @@ static void gen_add_gcs_record(DisasContext *s, TCGv_i= 64 value) tcg_gen_mov_i64(gcspr, addr); } =20 +static void gen_load_check_gcs_record(DisasContext *s, TCGv_i64 target, + GCSInstructionType it, int rt) +{ + TCGv_i64 gcspr =3D cpu_gcspr[s->current_el]; + int mmuidx =3D core_gcs_mem_index(s->mmu_idx); + MemOp mop =3D finalize_memop(s, MO_64 | MO_ALIGN); + TCGv_i64 rec_va =3D tcg_temp_new_i64(); + + tcg_gen_qemu_ld_i64(rec_va, clean_data_tbi(s, gcspr), mmuidx, mop); + + if (s->gcs_rvcen) { + TCGLabel *fail_label =3D + delay_exception(s, EXCP_UDEF, syn_gcs_data_check(it, rt)); + + tcg_gen_brcond_i64(TCG_COND_NE, rec_va, target, fail_label); + } + + gen_a64_set_pc(s, rec_va); + tcg_gen_addi_i64(gcspr, gcspr, 8); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -1798,7 +1819,13 @@ static bool trans_BLR(DisasContext *s, arg_r *a) =20 static bool trans_RET(DisasContext *s, arg_r *a) { - gen_a64_set_pc(s, cpu_reg(s, a->rn)); + TCGv_i64 target =3D cpu_reg(s, a->rn); + + if (s->gcs_en) { + gen_load_check_gcs_record(s, target, GCS_IT_RET_nPauth, a->rn); + } else { + gen_a64_set_pc(s, target); + } s->base.is_jmp =3D DISAS_JUMP; return true; } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756575878; cv=none; d=zohomail.com; s=zohoarc; b=Lt70Gk2n+amL+IKJtMrw3yKw9LRE1THNx7VBGjSNlMuDmftGGrF9n64X6zSKjKhmqsb42KU2EMIUCZDZQ9W+9hXubSqkkvvZ1redTE0unollPC2NOblnEL/ki9I+2qEaSwOIfT82F6oGmWAbDUJLpouBgieOj1gtHNtzzq2/GZI= ARC-Message-Signature: i=1; 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[122.150.204.179]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2490658999fsm40852715ad.112.2025.08.29.22.47.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 29 Aug 2025 22:47:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756532873; x=1757137673; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=f5dGKmFEigKAhdoQrKYKjmoib66tUCQFbD5Z0usNefI=; b=AG5NFcRrIsDwQou6sr6EnNvPiFQEZRSLZ0imRb/4ZlfS7j0cByJMMI2+Om+i5RJUlT P84Hrb/6UP955qrnawHH8LMxCHUvnUOgOsolgQILPed/sMQ9CYgVRTsgQsWreCx5tv2/ N8ojkg49bDg+QjDVqorntjNOsH34Px5gVarmkwYPsEHiR6g7UOTAav10WyLnIo4QY743 nCl2OE3hjCne7HBiC4J8CNzaaAvh6CxCVe4+lidwKT8ljiapjMCE1/cu68GqaWrjklkD py4inNlBc3Piwnz68ZcYNfLKwPg+23WsczghDNAM+3fGR2W8IaIE28tI3SjWIsky6lE3 J3hQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756532873; x=1757137673; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=f5dGKmFEigKAhdoQrKYKjmoib66tUCQFbD5Z0usNefI=; b=kRHLL258pk0w4HEH2A0zYuPUsDyxONz+581PYSua1COb+4r+hmJOx6BEORfpDomWKx JSfnMVOAgwiNsbZSgagjK3MFdVlN+t7i2nqYRI/3y7hLpzliDjBjkABg3iZrVqBCC5E0 V0Cr77pSij2WAR0+cwVOBOjfM2+yC0hX2hnX9xQg5JlqdthAmiX/+nsgJSiRIpIIFAqj amCtYYNt7f2CWWZGzDLqZem7epdkNy2RIWKWR0yRqsX2joerSFaDXkLWm1ODYOjCkgQz MuZGMcwp86r/B9NprTKQQfTJT3U7QQd5VKwE3E1fxZUfQ0UUuVFIjjDN2AoXAL/W7sCE Q0Tg== X-Gm-Message-State: AOJu0YzMNycmDMnVo9H5zjClWpZdlYwxfttiO9zcg4P3/ej6003JJ9nt ABjWdwPlMDo8CorVLiZsgRnx0dYR/Mv+SkwJ9P2h0opz4wW0x/5aBFS8M6MVvpoCUbbD39nrsHz ZqiQ1Er4= X-Gm-Gg: ASbGncubAMWvCnLjqf/Xj9fozgx0pFaA5lXwPm1qlQDBAcSmU9FuVop/gSdA0sZ16iG 2Zi9HsyCBPk5Upskzrwj1Z2GpJtRBGKU9ywLYwCMb/ugevOwXJdw98DICyfE717XuEyOOS342fm dbkUUZ9oQ3FzwiAeFMFUPegurd4f8h4cAN9IMML1MujufX2CBDSYkYTeZcOvsPO5T3O8a57EZaf Wr/2xGe5Oy0AbYTbNvlyd8ucnupAhrQ6xHiJeUj2a8BvLkjeyPf1yhWSdYq9nfPa6mpRtLaw3mT Hfun5AvjMpT7elvq5oM2fdMIoGPz+jbBarsRw+0+k90HrSPugtVraSVYDXo7hPBFVy2PPb/CYTh 3jvWKSgM9yPPT1m8VYG3mfksAhq2UMPIVMduI0h1n7FVOgNp653+iIuq+08h26Uk= X-Google-Smtp-Source: AGHT+IHpwILMW1la4GLgqESLwjm3qtO7EzCqTpBu9haw6gJD6o3f6ILGnCbECz1Y/fdEmAclAIAwiw== X-Received: by 2002:a17:902:ce8b:b0:248:fc2d:3a2c with SMTP id d9443c01a7336-24944a0e28dmr15210635ad.26.1756532872717; Fri, 29 Aug 2025 22:47:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 70/84] target/arm: Load gcs record for RET with PAuth Date: Sat, 30 Aug 2025 15:41:14 +1000 Message-ID: <20250830054128.448363-71-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756575880286116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 3ddf4bb018..95d9842a4f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -1898,7 +1898,12 @@ static bool trans_RETA(DisasContext *s, arg_reta *a) } =20 dst =3D auth_branch_target(s, cpu_reg(s, 30), cpu_X[31], !a->m); - gen_a64_set_pc(s, dst); + if (s->gcs_en) { + GCSInstructionType it =3D a->m ? GCS_IT_RET_PauthB : GCS_IT_RET_Pa= uthA; + gen_load_check_gcs_record(s, dst, it, 30); + } else { + gen_a64_set_pc(s, dst); + } s->base.is_jmp =3D DISAS_JUMP; return true; } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756573133; cv=none; d=zohomail.com; s=zohoarc; b=AOE6KFLn8oqSTUzAcxiiW7Ym8EhtooncvaZCQ2KLVM/stiGIc/X3cDlNEeoxNKsO4JWQ+wvOLjv6PHkltx8RIhqvtYycuo/lq5i6Hh/S/KetrKfmBRxU5IpwZD7oa6Ck5arMgbN+f8XNQgd1BFUF2dYPxLuLKKjXkLdcvyro7W4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756573133; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iNjN5B/BY+FR/sks3ZCMW62nI8kvCxcg9XIZHJr9QyU=; b=YHMZ4FoDSZGeHiq/IwiFLQdbfauumEuAsPzBKkx2OliBojWkDCdl5DepnCXlr6WecgzKTMMKd1sFxUoP0DWTGG7uzWGouJwCWhyi5Gt6pCNw6JDQjp6dc1uil2aYk9PnKGBYrquQnytqKCVaVUnyYsCkxvZd05KRlC29wGRvK0U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756573133808564.0275335840782; Sat, 30 Aug 2025 09:58:53 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNzq-00006E-BH; Sat, 30 Aug 2025 12:00:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usERV-0007WX-BA for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:48:01 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usERQ-00051r-SP for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:47:58 -0400 Received: by mail-pl1-x62f.google.com with SMTP id d9443c01a7336-2445826fd9dso33012545ad.3 for ; Fri, 29 Aug 2025 22:47:56 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2f19695d82..4bd96de926 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9194,8 +9194,13 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *c= s) } else { addr +=3D 0x600; } - } else if (pstate_read(env) & PSTATE_SP) { - addr +=3D 0x200; + } else { + if (pstate_read(env) & PSTATE_SP) { + addr +=3D 0x200; + } + if (is_a64(env) && (env->cp15.gcscr_el[new_el] & GCSCR_EXLOCKEN)) { + new_mode |=3D PSTATE_EXLOCK; + } } =20 switch (cs->exception_index) { --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756573293; cv=none; d=zohomail.com; s=zohoarc; b=CjczoD6CMDBt1xoK4LPAJp3pKwYUDwoTMtVsIy8u9UH7wsCl5XOJrUCK+t9fINqtFNeJLE7GgKcqeA4xiZq4ap5lCFgx1mbXIjCUqjbN82DEJQU2sDaVZR+rvzS0cOqPa9wanHQGN8Imf7/dxB5TUKDCJHEclqcVUKKK6FC5w5Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756573293; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=52VfTzYDSgjyTkCxi2KMOJnfbsQ5A6/k4xx3za3L80c=; b=Fbd0znmjO0kyVr02wUK++lKGTKkHiIXL9e7sdneJ7ZnZVLrNYCl7gMWI1dCcL88WSIp/WrDjgCNjLr96hP4421z9kGu3s4fCBY/Xdvdk9yZ9e1EHMLHAG0lYZNQql7NaknlOJO9w7PCVB4Rys5bsDoTfa9lhXC1hB2h7pAaGfUM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756573293437353.98788134773747; Sat, 30 Aug 2025 10:01:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usOEl-0000ii-UJ; Sat, 30 Aug 2025 12:15:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usERW-0007X9-Na for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:48:03 -0400 Received: from mail-pg1-x529.google.com ([2607:f8b0:4864:20::529]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usERV-000526-5o for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:48:02 -0400 Received: by mail-pg1-x529.google.com with SMTP id 41be03b00d2f7-b482fd89b0eso2396446a12.2 for ; Fri, 29 Aug 2025 22:47:59 -0700 (PDT) Received: from stoup.. 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We need not explicitly check FEAT_GC= S, + * because GCSCR_ELx cannot be set without it. + */ + if (new_el =3D=3D cur_el && + (env->cp15.gcscr_el[cur_el] & GCSCR_EXLOCKEN) && + !(env->pstate & PSTATE_EXLOCK)) { + goto illegal_return; + } + bql_lock(); arm_call_pre_el_change_hook(cpu); bql_unlock(); --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756575157; cv=none; d=zohomail.com; s=zohoarc; b=kUxMPJnJNksuuqXtGNqluN7DwR+b9bWOeu5VnErj6b0FaHCj9Qn9WQWT/sFrNs3Vpzs92EaRe5Yq26vgr2zqA/ejLWDWdGidouXkR8wKmmmMyQG8KLYXRRSYCX36CWAYQSb0KyB+OFmlGgkO3l0Mx5d/utbwm1t80NDsLEPULpQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756575157; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DxayGpcvk1WgEIrwtrnI87HtMykvmuTE7R78plec4rY=; b=grhBh44tgS/6+BETuuBsepjm9avjHFpIbUjxwN4JH1CIKTd5Dr/5ebeQxA3xekWXb1ucUd3Pq2fUglkkxQ+PQIyrknGhqW6dGhScoCnwmaUnaKZ/WbxZ9lLq7sIDEZwG6kOWecgKj4oZ/6w2QSJJq2LfJ2AB0fimE+7G3ky6YWc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756575157795720.3480418514445; Sat, 30 Aug 2025 10:32:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNzu-0000JO-LC; Sat, 30 Aug 2025 12:00:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usERa-0007Y6-75 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:48:07 -0400 Received: from mail-pg1-x533.google.com ([2607:f8b0:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usERX-00052S-QJ for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:48:05 -0400 Received: by mail-pg1-x533.google.com with SMTP id 41be03b00d2f7-b4c29d2ea05so2718916a12.0 for ; Fri, 29 Aug 2025 22:48:02 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:48:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Thiago Jung Bauermann , Pierrick Bouvier Subject: [PATCH v4 73/84] target/arm: Enable FEAT_GCS with -cpu max Date: Sat, 30 Aug 2025 15:41:17 +1000 Message-ID: <20250830054128.448363-74-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756575160701124100 Content-Type: text/plain; charset="utf-8" Tested-by: Thiago Jung Bauermann Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/tcg/cpu64.c | 1 + docs/system/arm/emulation.rst | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 76193826ce..8ebb0a91db 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1206,6 +1206,7 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR1, SME, 2); /* FEAT_SME2 */ t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_3 */ t =3D FIELD_DP64(t, ID_AA64PFR1, NMI, 1); /* FEAT_NMI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, GCS, 1); /* FEAT_GCS */ SET_IDREG(isar, ID_AA64PFR1, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR0); diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 4b07af9eac..21c187a464 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -73,6 +73,7 @@ the following architecture extensions: - FEAT_FRINTTS (Floating-point to integer instructions) - FEAT_FlagM (Flag manipulation instructions v2) - FEAT_FlagM2 (Enhancements to flag manipulation instructions) +- FEAT_GCS (Guarded Control Stack Extension) - FEAT_GTG (Guest translation granule size) - FEAT_HAFDBS (Hardware management of the access flag and dirty bit state) - FEAT_HBC (Hinted conditional branches) --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/gcs-internal.h | 38 ++++++++++++ linux-user/aarch64/target_prctl.h | 96 +++++++++++++++++++++++++++++++ linux-user/qemu.h | 5 ++ linux-user/syscall.c | 29 ++++++++++ 4 files changed, 168 insertions(+) create mode 100644 linux-user/aarch64/gcs-internal.h diff --git a/linux-user/aarch64/gcs-internal.h b/linux-user/aarch64/gcs-int= ernal.h new file mode 100644 index 0000000000..e586c7e80e --- /dev/null +++ b/linux-user/aarch64/gcs-internal.h @@ -0,0 +1,38 @@ +/* + * AArch64 gcs functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef AARCH64_GCS_INTERNAL_H +#define AARCH64_GCS_INTERNAL_H + +#ifndef PR_SHADOW_STACK_ENABLE +# define PR_SHADOW_STACK_ENABLE (1U << 0) +# define PR_SHADOW_STACK_WRITE (1U << 1) +# define PR_SHADOW_STACK_PUSH (1U << 2) +#endif + +static inline uint64_t gcs_get_el0_mode(CPUArchState *env) +{ + uint64_t cr =3D env->cp15.gcscr_el[0]; + abi_ulong flags =3D 0; + + flags |=3D cr & GCSCR_PCRSEL ? PR_SHADOW_STACK_ENABLE : 0; + flags |=3D cr & GCSCR_STREN ? PR_SHADOW_STACK_WRITE : 0; + flags |=3D cr & GCSCR_PUSHMEN ? PR_SHADOW_STACK_PUSH : 0; + + return flags; +} + +static inline void gcs_set_el0_mode(CPUArchState *env, uint64_t flags) +{ + uint64_t cr =3D GCSCRE0_NTR; + + cr |=3D flags & PR_SHADOW_STACK_ENABLE ? GCSCR_RVCHKEN | GCSCR_PCRSEL = : 0; + cr |=3D flags & PR_SHADOW_STACK_WRITE ? GCSCR_STREN : 0; + cr |=3D flags & PR_SHADOW_STACK_PUSH ? GCSCR_PUSHMEN : 0; + + env->cp15.gcscr_el[0] =3D cr; +} + +#endif diff --git a/linux-user/aarch64/target_prctl.h b/linux-user/aarch64/target_= prctl.h index ed75b9e4b5..621be5727f 100644 --- a/linux-user/aarch64/target_prctl.h +++ b/linux-user/aarch64/target_prctl.h @@ -6,8 +6,10 @@ #ifndef AARCH64_TARGET_PRCTL_H #define AARCH64_TARGET_PRCTL_H =20 +#include "qemu/units.h" #include "target/arm/cpu-features.h" #include "mte_user_helper.h" +#include "gcs-internal.h" =20 static abi_long do_prctl_sve_get_vl(CPUArchState *env) { @@ -206,4 +208,98 @@ static abi_long do_prctl_get_tagged_addr_ctrl(CPUArchS= tate *env) } #define do_prctl_get_tagged_addr_ctrl do_prctl_get_tagged_addr_ctrl =20 +static abi_long do_prctl_get_shadow_stack_status(CPUArchState *env, + abi_long arg2) +{ + ARMCPU *cpu =3D env_archcpu(env); + + if (!cpu_isar_feature(aa64_gcs, cpu)) { + return -TARGET_EINVAL; + } + return put_user_ual(gcs_get_el0_mode(env), arg2); +} +#define do_prctl_get_shadow_stack_status do_prctl_get_shadow_stack_status + +static abi_long gcs_alloc(abi_ulong hint, abi_ulong size) +{ + /* + * Without softmmu, we cannot protect GCS memory properly. + * Make do with normal read/write permissions. This at least allows + * emulation of correct programs which don't access the gcs stack + * with normal instructions. + */ + return target_mmap(hint, size, PROT_READ | PROT_WRITE, + MAP_PRIVATE | MAP_ANONYMOUS | + (hint ? MAP_FIXED_NOREPLACE : 0), -1, 0); +} + +static abi_ulong gcs_new_stack(TaskState *ts) +{ + /* Use guest_stack_size as a proxy for RLIMIT_STACK. */ + abi_ulong size =3D MIN(MAX(guest_stack_size / 2, TARGET_PAGE_SIZE), 2 = * GiB); + abi_ulong base =3D gcs_alloc(0, size); + + if (base =3D=3D -1) { + return -1; + } + + ts->gcs_base =3D base; + ts->gcs_size =3D size; + return base + size - 8; +} + +static abi_long do_prctl_set_shadow_stack_status(CPUArchState *env, + abi_long new_mode) +{ + ARMCPU *cpu =3D env_archcpu(env); + TaskState *ts =3D get_task_state(env_cpu(env)); + abi_long cur_mode; + + if (!cpu_isar_feature(aa64_gcs, cpu)) { + return -TARGET_EINVAL; + } + if (new_mode & ~(PR_SHADOW_STACK_ENABLE | + PR_SHADOW_STACK_WRITE | + PR_SHADOW_STACK_PUSH)) { + return -TARGET_EINVAL; + } + + cur_mode =3D gcs_get_el0_mode(env); + if ((new_mode ^ cur_mode) & ts->gcs_el0_locked) { + return -TARGET_EBUSY; + } + + if (new_mode & ~cur_mode & PR_SHADOW_STACK_ENABLE) { + abi_long gcspr; + + if (ts->gcs_base || env->cp15.gcspr_el[0]) { + return -EINVAL; + } + gcspr =3D gcs_new_stack(ts); + if (gcspr =3D=3D -1) { + return -TARGET_ENOMEM; + } + env->cp15.gcspr_el[0] =3D gcspr; + } + + gcs_set_el0_mode(env, new_mode); + arm_rebuild_hflags(env); + return 0; +} +#define do_prctl_set_shadow_stack_status do_prctl_set_shadow_stack_status + +static abi_long do_prctl_lock_shadow_stack_status(CPUArchState *env, + abi_long arg2) +{ + ARMCPU *cpu =3D env_archcpu(env); + TaskState *ts =3D get_task_state(env_cpu(env)); + + if (!cpu_isar_feature(aa64_gcs, cpu)) { + return -EINVAL; + } + ts->gcs_el0_locked |=3D arg2; + return 0; +} +#define do_prctl_lock_shadow_stack_status do_prctl_lock_shadow_stack_status + #endif /* AARCH64_TARGET_PRCTL_H */ diff --git a/linux-user/qemu.h b/linux-user/qemu.h index e4dca0c20f..8a0d240405 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -121,6 +121,11 @@ struct TaskState { abi_ulong child_tidptr; #ifdef TARGET_M68K abi_ulong tp_value; +#endif +#if defined(TARGET_AARCH64) + vaddr gcs_base; + abi_ulong gcs_size; + abi_ulong gcs_el0_locked; #endif int used; /* non zero if used */ struct image_info *info; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 91360a072c..2f1e881046 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6351,6 +6351,11 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) # define PR_SME_VL_LEN_MASK 0xffff # define PR_SME_VL_INHERIT (1 << 17) #endif +#ifndef PR_GET_SHADOW_STACK_STATUS +# define PR_GET_SHADOW_STACK_STATUS 74 +# define PR_SET_SHADOW_STACK_STATUS 75 +# define PR_LOCK_SHADOW_STACK_STATUS 76 +#endif =20 #include "target_prctl.h" =20 @@ -6397,6 +6402,15 @@ static abi_long do_prctl_inval1(CPUArchState *env, a= bi_long arg2) #ifndef do_prctl_sme_set_vl #define do_prctl_sme_set_vl do_prctl_inval1 #endif +#ifndef do_prctl_get_shadow_stack_status +#define do_prctl_get_shadow_stack_status do_prctl_inval1 +#endif +#ifndef do_prctl_set_shadow_stack_status +#define do_prctl_set_shadow_stack_status do_prctl_inval1 +#endif +#ifndef do_prctl_lock_shadow_stack_status +#define do_prctl_lock_shadow_stack_status do_prctl_inval1 +#endif =20 static abi_long do_prctl(CPUArchState *env, abi_long option, abi_long arg2, abi_long arg3, abi_long arg4, abi_long arg5) @@ -6467,6 +6481,21 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, return -TARGET_EINVAL; } return do_prctl_get_tagged_addr_ctrl(env); + case PR_GET_SHADOW_STACK_STATUS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_get_shadow_stack_status(env, arg2); + case PR_SET_SHADOW_STACK_STATUS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_set_shadow_stack_status(env, arg2); + case PR_LOCK_SHADOW_STACK_STATUS: + if (arg3 || arg4 || arg5) { + return -TARGET_EINVAL; + } + return do_prctl_lock_shadow_stack_status(env, arg2); =20 case PR_GET_UNALIGN: return do_prctl_get_unalign(env, arg2); --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756573588; cv=none; d=zohomail.com; s=zohoarc; b=G7qW27waevFCGkQX1z7QHZdDEWaWIvy68//RIS66vV3H+Zu9rOECjSgmhn0XYmFwrbiSPrOpMji3h8zyMVvxJy2U59JSpBNJZesR3adoGiycp2qhsvGYNcEWBt1ja8yHZ0bHBAUHZC4OUpWlmqNk90YDr10OSliBvovhJkAO4eE= ARC-Message-Signature: i=1; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/syscall.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 2f1e881046..91210775ed 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6652,6 +6652,21 @@ static int do_fork(CPUArchState *env, unsigned int f= lags, abi_ulong newsp, ts =3D g_new0(TaskState, 1); init_task_state(ts); =20 +#ifdef TARGET_AARCH64 + /* + * If GCS is enabled in the parent thread, it is also enabled + * in the child thread, but with a newly allocated stack. + */ + abi_long new_gcspr =3D 0; + if (env->cp15.gcscr_el[0] & GCSCR_PCRSEL) { + new_gcspr =3D gcs_new_stack(ts); + if (new_gcspr =3D=3D -1) { + g_free(ts); + return -TARGET_ENOMEM; + } + } +#endif + /* Grab a mutex so that thread setup appears atomic. */ pthread_mutex_lock(&clone_lock); =20 @@ -6676,6 +6691,11 @@ static int do_fork(CPUArchState *env, unsigned int f= lags, abi_ulong newsp, ts->info =3D parent_ts->info; ts->signal_mask =3D parent_ts->signal_mask; =20 +#ifdef TARGET_AARCH64 + ts->gcs_el0_locked =3D parent_ts->gcs_el0_locked; + new_env->cp15.gcspr_el[0] =3D new_gcspr; +#endif + if (flags & CLONE_CHILD_CLEARTID) { ts->child_tidptr =3D child_tidptr; } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756569729; cv=none; d=zohomail.com; s=zohoarc; b=N9kJZnrbJJPgK41zvmjuhhNcw4iHvq2vtLQARMM/M/dEnAbpBGY3eZYvY1kJwNLUIXGYPMpycwKRx7CifIiBsYffwDct86HDFgPafx9im9hHShfsCXFXCKCZYQMoHq8GjDWe59Ml0UoGGPTpbkDGS7BFO/IhooyNGHdQbxqrrSg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569729; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=Bac99cWBoODM0lZjzPV8FafpKsc60jTDKb6XVoHXo24=; b=KjmXTLvK91k5Etc+Zsf9Vtnv0efVpTjBvW54uNDhtQpwLjB1ueTEZIu6q8otqJevqgETVC5BJ6XnsGm4q6lIGI7/TZcb7bWkIQeN98aAK85xCCcpHhTI7u9YSDiF8DpD4tI/w0UmdN+AmykxCYcj6y5hgDAIR5b+EIvlJnFxYsE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756569729530773.1555470267818; Sat, 30 Aug 2025 09:02:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNzz-0000XQ-3H; Sat, 30 Aug 2025 12:00:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usERg-0007Zg-VK for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:48:14 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usERe-00053t-U3 for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:48:12 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d9443c01a7336-248ff4403b9so17479275ad.0 for ; Fri, 29 Aug 2025 22:48:10 -0700 (PDT) Received: from stoup.. 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Fri, 29 Aug 2025 22:48:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 76/84] linux-user/aarch64: Release gcs stack on thread exit Date: Sat, 30 Aug 2025 15:41:20 +1000 Message-ID: <20250830054128.448363-77-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756569730558116600 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/syscall.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 91210775ed..dfe114ceb3 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -9309,6 +9309,12 @@ static abi_long do_syscall1(CPUArchState *cpu_env, i= nt num, abi_long arg1, FUTEX_WAKE, INT_MAX, NULL, NULL, 0); } =20 +#ifdef TARGET_AARCH64 + if (ts->gcs_base) { + target_munmap(ts->gcs_base, ts->gcs_size); + } +#endif + object_unparent(OBJECT(cpu)); object_unref(OBJECT(cpu)); /* --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756572986; cv=none; d=zohomail.com; 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Fri, 29 Aug 2025 22:48:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 77/84] linux-user/aarch64: Implement map_shadow_stack syscall Date: Sat, 30 Aug 2025 15:41:21 +1000 Message-ID: <20250830054128.448363-78-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756572987682124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/syscall.c | 59 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 59 insertions(+) diff --git a/linux-user/syscall.c b/linux-user/syscall.c index dfe114ceb3..0a7ce7a262 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -6356,6 +6356,12 @@ abi_long do_arch_prctl(CPUX86State *env, int code, a= bi_ulong addr) # define PR_SET_SHADOW_STACK_STATUS 75 # define PR_LOCK_SHADOW_STACK_STATUS 76 #endif +#ifndef SHADOW_STACK_SET_TOKEN +# define SHADOW_STACK_SET_TOKEN (1u << 0) +#endif +#ifndef SHADOW_STACK_SET_MARKER +# define SHADOW_STACK_SET_MARKER (1u << 1) +#endif =20 #include "target_prctl.h" =20 @@ -6571,6 +6577,54 @@ static abi_long do_prctl(CPUArchState *env, abi_long= option, abi_long arg2, } } =20 +#ifdef TARGET_AARCH64 +static abi_long do_map_shadow_stack(CPUArchState *env, abi_ulong addr, + abi_ulong size, abi_int flags) +{ + ARMCPU *cpu =3D env_archcpu(env); + abi_ulong alloc_size; + + if (!cpu_isar_feature(aa64_gcs, cpu)) { + return -TARGET_EOPNOTSUPP; + } + if (flags & ~(SHADOW_STACK_SET_TOKEN | SHADOW_STACK_SET_MARKER)) { + return -TARGET_EINVAL; + } + if (addr & ~TARGET_PAGE_MASK) { + return -TARGET_EINVAL; + } + if (size =3D=3D 8 || !QEMU_IS_ALIGNED(size, 8)) { + return -TARGET_EINVAL; + } + + alloc_size =3D TARGET_PAGE_ALIGN(size); + if (alloc_size < size) { + return -TARGET_EOVERFLOW; + } + + mmap_lock(); + addr =3D gcs_alloc(addr, alloc_size); + if (addr !=3D -1) { + if (flags & SHADOW_STACK_SET_TOKEN) { + abi_ptr cap_ptr =3D addr + size - 8; + uint64_t cap_val; + + if (flags & SHADOW_STACK_SET_MARKER) { + /* Leave an extra empty frame at top-of-stack. */ + cap_ptr -=3D 8; + } + cap_val =3D (cap_ptr & TARGET_PAGE_MASK) | 1; + if (put_user_u64(cap_val, cap_ptr)) { + /* Allocation succeeded above. */ + g_assert_not_reached(); + } + } + } + mmap_unlock(); + return get_errno(addr); +} +#endif + #define NEW_STACK_SIZE 0x40000 =20 =20 @@ -13945,6 +13999,11 @@ static abi_long do_syscall1(CPUArchState *cpu_env,= int num, abi_long arg1, return do_riscv_hwprobe(cpu_env, arg1, arg2, arg3, arg4, arg5); #endif =20 +#ifdef TARGET_AARCH64 + case TARGET_NR_map_shadow_stack: + return do_map_shadow_stack(cpu_env, arg1, arg2, arg3); +#endif + default: qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num); return -TARGET_ENOSYS; --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756575224; cv=none; d=zohomail.com; s=zohoarc; b=bg8bolDQrL0Dlic0vmkxaOskEWtRuVYuIeU1y6nlaCD3nFEwluL0ucSbd4uoDmwhzP2UEFJaru6UHzn3ehzLIP/QZ94xDOrLhgqvQ+AlYSpcWu5YNSghiND7d5CQv4anDQ5m0OCDvCiUAHV8JFJxRMM4vf8x8a+Nl+aA2jXdXE8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756575224; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 29 Aug 2025 22:48:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 78/84] target/arm: Enable GCSPR_EL0 for read in user-mode Date: Sat, 30 Aug 2025 15:41:22 +1000 Message-ID: <20250830054128.448363-79-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756575227404124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- target/arm/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1c2ff87b89..51d1956e28 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -317,6 +317,10 @@ static void arm_cpu_reset_hold(Object *obj, ResetType = type) env->cp15.mdscr_el1 |=3D 1 << 12; /* Enable FEAT_MOPS */ env->cp15.sctlr_el[1] |=3D SCTLR_MSCEN; + /* For Linux, GCSPR_EL0 is always readable. */ + if (cpu_isar_feature(aa64_gcs, cpu)) { + env->cp15.gcscr_el[0] =3D GCSCRE0_NTR; + } #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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Fri, 29 Aug 2025 22:48:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 79/84] linux-user/aarch64: Inject SIGSEGV for GCS faults Date: Sat, 30 Aug 2025 15:41:23 +1000 Message-ID: <20250830054128.448363-80-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756574958432124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/target_signal.h | 1 + linux-user/aarch64/cpu_loop.c | 5 +++++ 2 files changed, 6 insertions(+) diff --git a/linux-user/aarch64/target_signal.h b/linux-user/aarch64/target= _signal.h index 6f66a50bfd..e509ac1032 100644 --- a/linux-user/aarch64/target_signal.h +++ b/linux-user/aarch64/target_signal.h @@ -7,6 +7,7 @@ =20 #define TARGET_SEGV_MTEAERR 8 /* Asynchronous ARM MTE error */ #define TARGET_SEGV_MTESERR 9 /* Synchronous ARM MTE exception */ +#define TARGET_SEGV_CPERR 10 /* Control protection fault */ =20 #define TARGET_ARCH_HAS_SETUP_FRAME #define TARGET_ARCH_HAS_SIGTRAMP_PAGE 1 diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 6060572eed..41d6b35498 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -89,6 +89,11 @@ static void signal_for_exception(CPUARMState *env, vaddr= addr) si_code =3D TARGET_ILL_ILLOPN; break; =20 + case EC_GCS: + si_signo =3D TARGET_SIGSEGV; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/signal.c | 138 ++++++++++++++++++++++++++++++++++-- 1 file changed, 132 insertions(+), 6 deletions(-) diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index ef97be3ac7..f7edfa249e 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -22,6 +22,7 @@ #include "signal-common.h" #include "linux-user/trace.h" #include "target/arm/cpu-features.h" +#include "gcs-internal.h" =20 struct target_sigcontext { uint64_t fault_address; @@ -152,6 +153,16 @@ struct target_zt_context { QEMU_BUILD_BUG_ON(TARGET_ZT_SIG_REG_BYTES !=3D \ sizeof_field(CPUARMState, za_state.zt0)); =20 +#define TARGET_GCS_MAGIC 0x47435300 +#define GCS_SIGNAL_CAP(X) ((X) & TARGET_PAGE_MASK) + +struct target_gcs_context { + struct target_aarch64_ctx head; + uint64_t gcspr; + uint64_t features_enabled; + uint64_t reserved; +}; + struct target_rt_sigframe { struct target_siginfo info; struct target_ucontext uc; @@ -322,6 +333,35 @@ static void target_setup_zt_record(struct target_zt_co= ntext *zt, } } =20 +static bool target_setup_gcs_record(struct target_gcs_context *ctx, + CPUARMState *env, uint64_t return_addr) +{ + uint64_t mode =3D gcs_get_el0_mode(env); + uint64_t gcspr =3D env->cp15.gcspr_el[0]; + + if (mode & PR_SHADOW_STACK_ENABLE) { + /* Push a cap for the signal frame. */ + gcspr -=3D 8; + if (put_user_u64(GCS_SIGNAL_CAP(gcspr), gcspr)) { + return false; + } + + /* Push a gcs entry for the trampoline. */ + if (put_user_u64(return_addr, gcspr - 8)) { + return false; + } + env->cp15.gcspr_el[0] =3D gcspr - 8; + } + + __put_user(TARGET_GCS_MAGIC, &ctx->head.magic); + __put_user(sizeof(*ctx), &ctx->head.size); + __put_user(gcspr, &ctx->gcspr); + __put_user(mode, &ctx->features_enabled); + __put_user(0, &ctx->reserved); + + return true; +} + static void target_restore_general_frame(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -502,6 +542,64 @@ static bool target_restore_zt_record(CPUARMState *env, return true; } =20 +static bool target_restore_gcs_record(CPUARMState *env, + struct target_gcs_context *ctx, + bool *rebuild_hflags) +{ + TaskState *ts =3D get_task_state(env_cpu(env)); + uint64_t cur_mode =3D gcs_get_el0_mode(env); + uint64_t new_mode, gcspr; + + __get_user(new_mode, &ctx->features_enabled); + __get_user(gcspr, &ctx->gcspr); + + /* + * The kernel pushes the value through the hw register: + * write_sysreg_s(gcspr, SYS_GCSPR_EL0) in restore_gcs_context, + * then read_sysreg_s(SYS_GCSPR_EL0) in gcs_restore_signal. + * Since the bottom 3 bits are RES0, this can (CONSTRAINED UNPREDICTAB= LE) + * force align the value. Mirror the choice from gcspr_write(). + */ + gcspr &=3D ~7; + + if (new_mode & ~(PR_SHADOW_STACK_ENABLE | + PR_SHADOW_STACK_WRITE | + PR_SHADOW_STACK_PUSH)) { + return false; + } + if ((new_mode ^ cur_mode) & ts->gcs_el0_locked) { + return false; + } + if (new_mode & ~cur_mode & PR_SHADOW_STACK_ENABLE) { + return false; + } + + if (new_mode & PR_SHADOW_STACK_ENABLE) { + uint64_t cap; + + /* Pop and clear the signal cap. */ + if (get_user_u64(cap, gcspr)) { + return false; + } + if (cap !=3D GCS_SIGNAL_CAP(gcspr)) { + return false; + } + if (put_user_u64(0, gcspr)) { + return false; + } + gcspr +=3D 8; + } else { + new_mode =3D 0; + } + + env->cp15.gcspr_el[0] =3D gcspr; + if (new_mode !=3D cur_mode) { + *rebuild_hflags =3D true; + gcs_set_el0_mode(env, new_mode); + } + return true; +} + static int target_restore_sigframe(CPUARMState *env, struct target_rt_sigframe *sf) { @@ -511,8 +609,10 @@ static int target_restore_sigframe(CPUARMState *env, struct target_za_context *za =3D NULL; struct target_tpidr2_context *tpidr2 =3D NULL; struct target_zt_context *zt =3D NULL; + struct target_gcs_context *gcs =3D NULL; uint64_t extra_datap =3D 0; bool used_extra =3D false; + bool rebuild_hflags =3D false; int sve_size =3D 0; int za_size =3D 0; int zt_size =3D 0; @@ -582,6 +682,15 @@ static int target_restore_sigframe(CPUARMState *env, zt_size =3D size; break; =20 + case TARGET_GCS_MAGIC: + if (gcs + || size !=3D sizeof(struct target_gcs_context) + || !cpu_isar_feature(aa64_gcs, env_archcpu(env))) { + goto err; + } + gcs =3D (struct target_gcs_context *)ctx; + break; + case TARGET_EXTRA_MAGIC: if (extra || size !=3D sizeof(struct target_extra_context)) { goto err; @@ -612,6 +721,10 @@ static int target_restore_sigframe(CPUARMState *env, goto err; } =20 + if (gcs && !target_restore_gcs_record(env, gcs, &rebuild_hflags)) { + goto err; + } + /* SVE data, if present, overwrites FPSIMD data. */ if (sve && !target_restore_sve_record(env, sve, sve_size, &svcr)) { goto err; @@ -631,6 +744,9 @@ static int target_restore_sigframe(CPUARMState *env, } if (env->svcr !=3D svcr) { env->svcr =3D svcr; + rebuild_hflags =3D true; + } + if (rebuild_hflags) { arm_rebuild_hflags(env); } unlock_user(extra, extra_datap, 0); @@ -701,7 +817,7 @@ static void target_setup_frame(int usig, struct target_= sigaction *ka, uc.tuc_mcontext.__reserved), }; int fpsimd_ofs, fr_ofs, sve_ofs =3D 0, za_ofs =3D 0, tpidr2_ofs =3D 0; - int zt_ofs =3D 0, esr_ofs =3D 0; + int zt_ofs =3D 0, esr_ofs =3D 0, gcs_ofs =3D 0; int sve_size =3D 0, za_size =3D 0, tpidr2_size =3D 0, zt_size =3D 0; struct target_rt_sigframe *frame; struct target_rt_frame_record *fr; @@ -720,6 +836,11 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, &layout); } =20 + if (env->cp15.gcspr_el[0]) { + gcs_ofs =3D alloc_sigframe_space(sizeof(struct target_gcs_context), + &layout); + } + /* SVE state needs saving only if it exists. */ if (cpu_isar_feature(aa64_sve, env_archcpu(env)) || cpu_isar_feature(aa64_sme, env_archcpu(env))) { @@ -779,6 +900,12 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, goto give_sigsegv; } =20 + if (ka->sa_flags & TARGET_SA_RESTORER) { + return_addr =3D ka->sa_restorer; + } else { + return_addr =3D default_rt_sigreturn; + } + target_setup_general_frame(frame, env, set); target_setup_fpsimd_record((void *)frame + fpsimd_ofs, env); if (esr_ofs) { @@ -786,6 +913,10 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, /* Leave ESR_EL1 clear while it's not relevant. */ env->cp15.esr_el[1] =3D 0; } + if (gcs_ofs && + !target_setup_gcs_record((void *)frame + gcs_ofs, env, return_addr= )) { + goto give_sigsegv; + } target_setup_end_record((void *)frame + layout.std_end_ofs); if (layout.extra_ofs) { target_setup_extra_record((void *)frame + layout.extra_ofs, @@ -811,11 +942,6 @@ static void target_setup_frame(int usig, struct target= _sigaction *ka, __put_user(env->xregs[29], &fr->fp); __put_user(env->xregs[30], &fr->lr); =20 - if (ka->sa_flags & TARGET_SA_RESTORER) { - return_addr =3D ka->sa_restorer; - } else { - return_addr =3D default_rt_sigreturn; - } env->xregs[0] =3D usig; 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Fri, 29 Aug 2025 22:51:26 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v4 81/84] linux-user/aarch64: Enable GCS in HWCAP Date: Sat, 30 Aug 2025 15:41:25 +1000 Message-ID: <20250830054128.448363-82-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250830054128.448363-1-richard.henderson@linaro.org> References: <20250830054128.448363-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756571197571124100 Content-Type: text/plain; charset="utf-8" Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- linux-user/aarch64/elfload.c | 1 + 1 file changed, 1 insertion(+) diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index 77d03b50e1..3af5a37776 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -169,6 +169,7 @@ abi_ulong get_elf_hwcap(CPUState *cs) GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); + GET_FEATURE_ID(aa64_gcs, ARM_HWCAP_A64_GCS); =20 return hwcaps; } --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756575553; cv=none; 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Validate successful and trapped executions of GCSSTR. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tests/tcg/aarch64/gcs.h | 71 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/gcsstr.c | 48 +++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 5 +++ 3 files changed, 124 insertions(+) create mode 100644 tests/tcg/aarch64/gcs.h create mode 100644 tests/tcg/aarch64/gcsstr.c diff --git a/tests/tcg/aarch64/gcs.h b/tests/tcg/aarch64/gcs.h new file mode 100644 index 0000000000..99cb4d4e38 --- /dev/null +++ b/tests/tcg/aarch64/gcs.h @@ -0,0 +1,71 @@ +/* + * Linux kernel fallback API definitions for GCS and test helpers. + * + * Copyright (c) 2025 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_GET_SHADOW_STACK_STATUS +#define PR_GET_SHADOW_STACK_STATUS 74 +#endif +#ifndef PR_SET_SHADOW_STACK_STATUS +#define PR_SET_SHADOW_STACK_STATUS 75 +#endif +#ifndef PR_LOCK_SHADOW_STACK_STATUS +#define PR_LOCK_SHADOW_STACK_STATUS 76 +#endif +#ifndef PR_SHADOW_STACK_ENABLE +# define PR_SHADOW_STACK_ENABLE (1 << 0) +# define PR_SHADOW_STACK_WRITE (1 << 1) +# define PR_SHADOW_STACK_PUSH (1 << 2) +#endif +#ifndef SHADOW_STACK_SET_TOKEN +#define SHADOW_STACK_SET_TOKEN (1 << 0) +#endif +#ifndef SHADOW_STACK_SET_MARKER +#define SHADOW_STACK_SET_MARKER (1 << 1) +#endif +#ifndef SEGV_CPERR +#define SEGV_CPERR 10 +#endif +#ifndef __NR_map_shadow_stack +#define __NR_map_shadow_stack 453 +#endif + +/* + * Macros, and implement the syscall inline, lest we fail + * the checked return from any function call. + */ +#define enable_gcs(flags) \ + do { = \ + register long num __asm__ ("x8") =3D __NR_prctl; = \ + register long arg1 __asm__ ("x0") =3D PR_SET_SHADOW_STACK_STATUS; = \ + register long arg2 __asm__ ("x1") =3D PR_SHADOW_STACK_ENABLE | fla= gs; \ + register long arg3 __asm__ ("x2") =3D 0; = \ + register long arg4 __asm__ ("x3") =3D 0; = \ + register long arg5 __asm__ ("x4") =3D 0; = \ + asm volatile("svc #0" = \ + : "+r"(arg1) = \ + : "r"(arg2), "r"(arg3), "r"(arg4), "r"(arg5), "r"(num= ) \ + : "memory", "cc"); = \ + if (arg1) { = \ + errno =3D -arg1; = \ + perror("PR_SET_SHADOW_STACK_STATUS"); = \ + exit(2); = \ + } = \ + } while (0) + +#define gcspr() \ + ({ uint64_t *r; asm volatile("mrs %0, s3_3_c2_c5_1" : "=3Dr"(r)); r; }) diff --git a/tests/tcg/aarch64/gcsstr.c b/tests/tcg/aarch64/gcsstr.c new file mode 100644 index 0000000000..b045aee925 --- /dev/null +++ b/tests/tcg/aarch64/gcsstr.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "gcs.h" + +/* + * A single garbage store to the gcs stack. + * The asm inside must be unique, so disallow inlining. + */ +void __attribute__((noinline)) +test_gcsstr(void) +{ + register uint64_t *ptr __asm__("x0") =3D gcspr(); + /* GCSSTR x1, x0 */ + __asm__("inst_gcsstr: .inst 0xd91f1c01" : : "r"(--ptr)); +} + +static void test_sigsegv(int sig, siginfo_t *info, void *vuc) +{ + ucontext_t *uc =3D vuc; + uint64_t inst_gcsstr; + + __asm__("adr %0, inst_gcsstr" : "=3Dr"(inst_gcsstr)); + assert(uc->uc_mcontext.pc =3D=3D inst_gcsstr); + assert(info->si_code =3D=3D SEGV_CPERR); + /* TODO: Dig for ESR and verify syndrome. */ + exit(0); +} + +int main() +{ + struct sigaction sa =3D { + .sa_sigaction =3D test_sigsegv, + .sa_flags =3D SA_SIGINFO, + }; + + /* Enable GCSSTR and test the store succeeds. */ + enable_gcs(PR_SHADOW_STACK_WRITE); + test_gcsstr(); + + /* Disable GCSSTR and test the resulting sigsegv. */ + enable_gcs(0); + if (sigaction(SIGSEGV, &sa, NULL) < 0) { + perror("sigaction"); + exit(1); + } + test_gcsstr(); + abort(); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 16ddcf4f88..0347a36e8d 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -75,6 +75,11 @@ AARCH64_TESTS +=3D $(SME_TESTS) $(SME_TESTS): CFLAGS +=3D $(CROSS_AS_HAS_ARMV9_SME) endif =20 +# GCS Tests +GCS_TESTS +=3D gcsstr +AARCH64_TESTS +=3D $(GCS_TESTS) +$(GCS_TESTS): gcs.h + # System Registers Tests AARCH64_TESTS +=3D sysregs =20 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tests/tcg/aarch64/gcspushm.c | 71 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 2 +- 2 files changed, 72 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/gcspushm.c diff --git a/tests/tcg/aarch64/gcspushm.c b/tests/tcg/aarch64/gcspushm.c new file mode 100644 index 0000000000..c330417a2f --- /dev/null +++ b/tests/tcg/aarch64/gcspushm.c @@ -0,0 +1,71 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "gcs.h" + + +#define GCSPUSHM "sys #3, c7, c7, #0, %[push]" +#define GCSPOPM "sysl %[pop], #3, c7, c7, #1" + +static void test_sigsegv(int sig, siginfo_t *info, void *vuc) +{ + ucontext_t *uc =3D vuc; + uint64_t inst_sigsegv; + + __asm__("adr %0, inst_sigsegv" : "=3Dr"(inst_sigsegv)); + assert(uc->uc_mcontext.pc =3D=3D inst_sigsegv); + assert(info->si_code =3D=3D SEGV_CPERR); + /* TODO: Dig for ESR and verify syndrome. */ + uc->uc_mcontext.pc +=3D 4; +} + +static void test_sigill(int sig, siginfo_t *info, void *vuc) +{ + ucontext_t *uc =3D vuc; + uint64_t inst_sigill; + + __asm__("adr %0, inst_sigill" : "=3Dr"(inst_sigill)); + assert(uc->uc_mcontext.pc =3D=3D inst_sigill); + assert(info->si_code =3D=3D ILL_ILLOPC); + uc->uc_mcontext.pc +=3D 4; +} + +int main() +{ + struct sigaction sa =3D { .sa_flags =3D SA_SIGINFO }; + uint64_t old, new; + + sa.sa_sigaction =3D test_sigsegv; + if (sigaction(SIGSEGV, &sa, NULL) < 0) { + perror("sigaction"); + exit(1); + } + + sa.sa_sigaction =3D test_sigill; + if (sigaction(SIGILL, &sa, NULL) < 0) { + perror("sigaction"); + exit(1); + } + + /* Pushm is disabled -- SIGILL via EC_SYSTEMREGISTERTRAP */ + asm volatile("inst_sigill:\t" GCSPUSHM + : : [push] "r" (1)); + + enable_gcs(PR_SHADOW_STACK_PUSH); + + /* Valid value -- low 2 bits clear */ + old =3D 0xdeadbeeffeedcaec; + asm volatile(GCSPUSHM "\n\t" GCSPOPM + : [pop] "=3Dr" (new) + : [push] "r" (old) + : "memory"); + assert(old =3D=3D new); + + /* Invalid value -- SIGSEGV via EC_GCS */ + asm volatile(GCSPUSHM "\n" + "inst_sigsegv:\t" GCSPOPM + : [pop] "=3Dr" (new) + : [push] "r" (1) + : "memory"); + + exit(0); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 0347a36e8d..c6f401c317 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -76,7 +76,7 @@ $(SME_TESTS): CFLAGS +=3D $(CROSS_AS_HAS_ARMV9_SME) endif =20 # GCS Tests -GCS_TESTS +=3D gcsstr +GCS_TESTS +=3D gcsstr gcspushm AARCH64_TESTS +=3D $(GCS_TESTS) $(GCS_TESTS): gcs.h =20 --=20 2.43.0 From nobody Sun Sep 7 18:35:11 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1756570556; cv=none; d=zohomail.com; s=zohoarc; b=m1rfdLxS6v22YrfSk3Z340yWZEtfdJHd6FN8KgxDmn1yJ5wP3JGLrVNLw25vzPJYVldanTQQjAfgUkFVPllLGmNZ06XzoS/RKrd7HYKdPuhLnSvFmW4rvGxLai6qUBtDr00b+8Sx/N2cmY1EBe/nTDCp3PgR7SHmdPWAzKg7IqQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756570556; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=L1ak1ZU/AR0+1y4HNoJj/qDB25/smzJJgjU2bzP6iSw=; b=mXk2pGQRyEfmpK8ezfPyi5S47JMCABs9cL+WtyZLZQDM932ysRdlLLTxVgTKiFHBy/xQW+hIeuUK0y6IC+r+m922aZYKd4SFpQFK4ZXvJ9sbv5TFIyJVZsC985U1rQO77AcOGNvSXxP8yHoSWnktMh2rvaaMDmwQMJpDTd0JJPI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756570556008137.76628628184096; Sat, 30 Aug 2025 09:15:56 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usNzs-0000A2-JF; Sat, 30 Aug 2025 12:00:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1usEUz-0008Va-HO for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:51:40 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1usEUx-0005kR-SB for qemu-devel@nongnu.org; Sat, 30 Aug 2025 01:51:37 -0400 Received: by mail-pf1-x431.google.com with SMTP id d2e1a72fcca58-7722d6cc437so1233448b3a.0 for ; Fri, 29 Aug 2025 22:51:35 -0700 (PDT) Received: from stoup.. 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Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tests/tcg/aarch64/gcs.h | 9 ++++ tests/tcg/aarch64/gcsss.c | 74 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 2 +- 3 files changed, 84 insertions(+), 1 deletion(-) create mode 100644 tests/tcg/aarch64/gcsss.c diff --git a/tests/tcg/aarch64/gcs.h b/tests/tcg/aarch64/gcs.h index 99cb4d4e38..e821963cb8 100644 --- a/tests/tcg/aarch64/gcs.h +++ b/tests/tcg/aarch64/gcs.h @@ -69,3 +69,12 @@ =20 #define gcspr() \ ({ uint64_t *r; asm volatile("mrs %0, s3_3_c2_c5_1" : "=3Dr"(r)); r; }) + +#define gcsss1(val) \ + do { = \ + asm volatile("sys #3, c7, c7, #2, %0" : : "r"(val) : "memory"); = \ + } while (0) + +#define gcsss2() \ + ({ uint64_t *r; = \ + asm volatile("sysl %0, #3, c7, c7, #3" : "=3Dr"(r) : : "memory"); r= ; }) diff --git a/tests/tcg/aarch64/gcsss.c b/tests/tcg/aarch64/gcsss.c new file mode 100644 index 0000000000..9550c68e7e --- /dev/null +++ b/tests/tcg/aarch64/gcsss.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "gcs.h" + +#define IN_PROGRESS(X) ((uint64_t)(X) | 5) +#define CAP(X) (((uint64_t)(X) & ~0xfff) + 1) + +static uint64_t * __attribute__((noinline)) recurse(size_t index) +{ + if (index =3D=3D 0) { + return gcspr(); + } + return recurse(index - 1); +} + +int main() +{ + void *tmp; + uint64_t *alt_stack, *alt_cap; + uint64_t *orig_pr, *orig_cap; + uint64_t *bottom; + size_t pagesize =3D getpagesize(); + size_t words; + + enable_gcs(0); + orig_pr =3D gcspr(); + + /* Allocate a guard page before and after. */ + tmp =3D mmap(0, 3 * pagesize, PROT_NONE, MAP_ANON | MAP_PRIVATE, -1, 0= ); + assert(tmp !=3D MAP_FAILED); + + /* map_shadow_stack won't replace existing mappings */ + munmap(tmp + pagesize, pagesize); + + /* Allocate a new stack between the guards. */ + alt_stack =3D (uint64_t *) + syscall(__NR_map_shadow_stack, tmp + pagesize, pagesize, + SHADOW_STACK_SET_TOKEN); + assert(alt_stack =3D=3D tmp + pagesize); + + words =3D pagesize / 8; + alt_cap =3D alt_stack + words - 1; + + /* SHADOW_STACK_SET_TOKEN set the cap. */ + assert(*alt_cap =3D=3D CAP(alt_cap)); + + /* Swap to the alt stack, one step at a time. */ + gcsss1(alt_cap); + + assert(gcspr() =3D=3D alt_cap); + assert(*alt_cap =3D=3D IN_PROGRESS(orig_pr)); + + orig_cap =3D gcsss2(); + + assert(orig_cap =3D=3D orig_pr - 1); + assert(*orig_cap =3D=3D CAP(orig_cap)); + assert(gcspr() =3D=3D alt_stack + words); + + /* We should be able to use the whole stack. */ + bottom =3D recurse(words - 1); + assert(bottom =3D=3D alt_stack); + + /* We should be back where we started. */ + assert(gcspr() =3D=3D alt_stack + words); + + /* Swap back to the original stack. */ + gcsss1(orig_cap); + tmp =3D gcsss2(); + + assert(gcspr() =3D=3D orig_pr); + assert(tmp =3D=3D alt_cap); + + exit(0); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index c6f401c317..b858f8692e 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -76,7 +76,7 @@ $(SME_TESTS): CFLAGS +=3D $(CROSS_AS_HAS_ARMV9_SME) endif =20 # GCS Tests -GCS_TESTS +=3D gcsstr gcspushm +GCS_TESTS +=3D gcsstr gcspushm gcsss AARCH64_TESTS +=3D $(GCS_TESTS) $(GCS_TESTS): gcs.h =20 --=20 2.43.0