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Fri, 29 Aug 2025 06:00:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGF1UfZ01N6dZ/xHrZ7Z/scelEM3D0hdN1H4/pJIiCA6v6p/WnkrhleIqeaARm+GK/2zeraIw== X-Received: by 2002:adf:a155:0:b0:3ce:9872:fd3 with SMTP id ffacd0b85a97d-3ce987213dfmr2758822f8f.34.1756472418587; Fri, 29 Aug 2025 06:00:18 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 15/28] hw/i386/pc_piix.c: assume pcmc->pci_enabled is always true in pc_init1() Date: Fri, 29 Aug 2025 14:59:22 +0200 Message-ID: <20250829125935.1526984-16-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756569478134124100 From: Mark Cave-Ayland PCI is always enabled on the pc-i440fx machine so hardcode the relevant log= ic in pc_init1(). Add an assert() to ensure that this is always the case at runtime as already done in pc_q35_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-16-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 192 ++++++++++++++++++---------------------------- 1 file changed, 76 insertions(+), 116 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 72ddd9b149d..3ea77b2c44f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -125,6 +125,11 @@ static void pc_init1(MachineState *machine, const char= *pci_type) MemoryRegion *rom_memory =3D system_memory; ram_addr_t lowmem; uint64_t hole64_size =3D 0; + PCIDevice *pci_dev; + DeviceState *dev; + size_t i; + + assert(pcmc->pci_enabled); =20 /* * Calculate ram split, for memory below and above 4G. It's a bit @@ -195,38 +200,36 @@ static void pc_init1(MachineState *machine, const cha= r *pci_type) kvmclock_create(pcmc->kvmclock_create_always); } =20 - if (pcmc->pci_enabled) { - pci_memory =3D g_new(MemoryRegion, 1); - memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - rom_memory =3D pci_memory; + pci_memory =3D g_new(MemoryRegion, 1); + memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); + rom_memory =3D pci_memory; =20 - phb =3D OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); - object_property_add_child(OBJECT(machine), "i440fx", phb); - object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, - OBJECT(ram_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, - OBJECT(pci_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, - OBJECT(system_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, - OBJECT(system_io), &error_fatal); - object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, - x86ms->below_4g_mem_size, &error_fatal); - object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, - x86ms->above_4g_mem_size, &error_fatal); - object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, - &error_fatal); - sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + phb =3D OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); + object_property_add_child(OBJECT(machine), "i440fx", phb); + object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, + OBJECT(ram_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, + OBJECT(pci_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, + OBJECT(system_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, + OBJECT(system_io), &error_fatal); + object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, + x86ms->below_4g_mem_size, &error_fatal); + object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, + x86ms->above_4g_mem_size, &error_fatal); + object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, + &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); =20 - pcms->pcibus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); - pci_bus_map_irqs(pcms->pcibus, - xen_enabled() ? xen_pci_slot_get_pirq - : pc_pci_slot_get_pirq); + pcms->pcibus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); + pci_bus_map_irqs(pcms->pcibus, + xen_enabled() ? xen_pci_slot_get_pirq + : pc_pci_slot_get_pirq); =20 - hole64_size =3D object_property_get_uint(phb, - PCI_HOST_PROP_PCI_HOLE64_SI= ZE, - &error_abort); - } + hole64_size =3D object_property_get_uint(phb, + PCI_HOST_PROP_PCI_HOLE64_SIZE, + &error_abort); =20 /* allocate ram and load rom/bios */ if (!xen_enabled()) { @@ -242,72 +245,51 @@ static void pc_init1(MachineState *machine, const cha= r *pci_type) } } =20 - gsi_state =3D pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); + gsi_state =3D pc_gsi_create(&x86ms->gsi, true); =20 - if (pcmc->pci_enabled) { - PCIDevice *pci_dev; - DeviceState *dev; - size_t i; - - pci_dev =3D pci_new_multifunction(-1, pcms->south_bridge); - object_property_set_bool(OBJECT(pci_dev), "has-usb", - machine_usb(machine), &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-acpi", - x86_machine_is_acpi_enabled(x86ms), - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pic", false, - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pit", false, - &error_abort); - qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); - object_property_set_bool(OBJECT(pci_dev), "smm-enabled", - x86_machine_is_smm_enabled(x86ms), - &error_abort); - dev =3D DEVICE(pci_dev); - for (i =3D 0; i < ISA_NUM_IRQS; i++) { - qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); - } - pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal); - - if (xen_enabled()) { - pci_device_set_intx_routing_notifier( - pci_dev, piix_intx_routing_notifier_xen); - - /* - * Xen supports additional interrupt routes from the PCI devic= es to - * the IOAPIC: the four pins of each PCI device on the bus are= also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. - */ - pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev, - XEN_IOAPIC_NUM_PIRQS); - } - - isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); - x86ms->rtc =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci= _dev), - "rtc")); - piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); - dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide= ")); - pci_ide_create_devs(PCI_DEVICE(dev)); - pcms->idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); - pcms->idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); - } else { - uint32_t irq; - - isa_bus =3D isa_bus_new(NULL, system_memory, system_io, - &error_abort); - isa_bus_register_input_irqs(isa_bus, x86ms->gsi); - - x86ms->rtc =3D isa_new(TYPE_MC146818_RTC); - qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); - isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); - irq =3D object_property_get_uint(OBJECT(x86ms->rtc), "irq", - &error_fatal); - isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq); - - i8257_dma_init(OBJECT(machine), isa_bus, 0); - pcms->hpet_enabled =3D false; + pci_dev =3D pci_new_multifunction(-1, pcms->south_bridge); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-pic", false, + &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-pit", false, + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); + dev =3D DEVICE(pci_dev); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); } + pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal); + + if (xen_enabled()) { + pci_device_set_intx_routing_notifier( + pci_dev, piix_intx_routing_notifier_xen); + + /* + * Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. + */ + pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev, + XEN_IOAPIC_NUM_PIRQS); + } + + isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); + x86ms->rtc =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev= ), + "rtc")); + piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); + pci_ide_create_devs(PCI_DEVICE(dev)); + pcms->idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); + pcms->idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); + =20 if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); @@ -321,7 +303,7 @@ static void pc_init1(MachineState *machine, const char = *pci_type) x86_register_ferr_irq(x86ms->gsi[13]); } =20 - pc_vga_init(isa_bus, pcmc->pci_enabled ? pcms->pcibus : NULL); + pc_vga_init(isa_bus, pcms->pcibus); =20 /* init basic PC hardware */ pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, @@ -329,28 +311,6 @@ static void pc_init1(MachineState *machine, const char= *pci_type) =20 pc_nic_init(pcmc, isa_bus, pcms->pcibus); =20 -#ifdef CONFIG_IDE_ISA - if (!pcmc->pci_enabled) { - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - int i; - - ide_drive_get(hd, ARRAY_SIZE(hd)); - for (i =3D 0; i < MAX_IDE_BUS; i++) { - ISADevice *dev; - char busname[] =3D "ide.0"; - dev =3D isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], - ide_irq[i], - hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i += 1]); - /* - * The ide bus name is ide.0 for the first bus and ide.1 for t= he - * second one. - */ - busname[4] =3D '0' + i; - pcms->idebus[i] =3D qdev_get_child_bus(DEVICE(dev), busname); - } - } -#endif - if (piix4_pm) { smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); =20 --=20 2.51.0