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Fri, 29 Aug 2025 05:59:39 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGZ3BJkar1NmnX9u4VmzDEfyEjes5XeY+FXh2noUbd6eOe+vrTK2Kzl6rh7bVxs9emHXSZtwQ== X-Received: by 2002:a05:600c:4e87:b0:459:e094:92c2 with SMTP id 5b1f17b1804b1-45b517dd290mr220156575e9.27.1756472379387; Fri, 29 Aug 2025 05:59:39 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/28] hw/i386/pc_piix.c: restrict isapc machine to 32-bit CPUs Date: Fri, 29 Aug 2025 14:59:08 +0200 Message-ID: <20250829125935.1526984-2-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567089030116600 From: Mark Cave-Ayland The isapc machine represents a legacy ISA PC with a 486 CPU. Whilst it is possible to specify any CPU via -cpu on the command line, it makes no sense to allow modern 64-bit CPUs to be used. Restrict the isapc machine to the available 32-bit CPUs, taking care to handle the case where if a user inadvertently uses either -cpu max or -cpu host then the "best" 32-bit CPU is used (in this case the pentium3). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/r/20250828111057.468712-2-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index d165ac72ed7..8f5fb3cf90b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -436,6 +436,31 @@ static void pc_set_south_bridge(Object *obj, int value= , Error **errp) #ifdef CONFIG_ISAPC static void pc_init_isa(MachineState *machine) { + /* + * There is a small chance that someone unintentionally passes "-cpu m= ax" + * for the isapc machine, which will provide a much more modern 32-bit + * CPU than would be expected for an ISA-era PC. If the "max" cpu type= has + * been specified, choose the "best" 32-bit cpu possible which we cons= ider + * be the pentium3 (deliberately choosing an Intel CPU given that the + * default 486 CPU for the isapc machine is also an Intel CPU). + */ + if (!strcmp(machine->cpu_type, X86_CPU_TYPE_NAME("max"))) { + machine->cpu_type =3D X86_CPU_TYPE_NAME("pentium3"); + warn_report("-cpu max is invalid for isapc machine, using pentium3= "); + } + + /* + * Similarly if someone unintentionally passes "-cpu host" for the isa= pc + * machine then display a warning and also switch to the "best" 32-bit + * cpu possible which we consider to be the pentium3. This is because = any + * host CPU will already be modern than this, but it also ensures any + * newer CPU flags/features are filtered out for older guests. + */ + if (!strcmp(machine->cpu_type, X86_CPU_TYPE_NAME("host"))) { + machine->cpu_type =3D X86_CPU_TYPE_NAME("pentium3"); + warn_report("-cpu host is invalid for isapc machine, using pentium= 3"); + } + pc_init1(machine, NULL); } #endif @@ -815,7 +840,20 @@ DEFINE_I440FX_MACHINE(2, 6); #ifdef CONFIG_ISAPC static void isapc_machine_options(MachineClass *m) { + static const char * const valid_cpu_types[] =3D { + X86_CPU_TYPE_NAME("486"), + X86_CPU_TYPE_NAME("athlon"), + X86_CPU_TYPE_NAME("kvm32"), + X86_CPU_TYPE_NAME("pentium"), + X86_CPU_TYPE_NAME("pentium2"), + X86_CPU_TYPE_NAME("pentium3"), + X86_CPU_TYPE_NAME("qemu32"), + X86_CPU_TYPE_NAME("max"), + X86_CPU_TYPE_NAME("host"), + NULL + }; PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); + m->desc =3D "ISA-only PC"; m->max_cpus =3D 1; m->option_rom_has_mr =3D true; @@ -828,6 +866,7 @@ static void isapc_machine_options(MachineClass *m) pcmc->has_reserved_memory =3D false; m->default_nic =3D "ne2k_isa"; m->default_cpu_type =3D X86_CPU_TYPE_NAME("486"); + m->valid_cpu_types =3D valid_cpu_types; m->no_floppy =3D !module_object_class_by_name(TYPE_ISA_FDC); m->no_parallel =3D !module_object_class_by_name(TYPE_ISA_PARALLEL); } --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756569086; cv=none; d=zohomail.com; s=zohoarc; b=TNlq9yvGFiavM3cidUVXSrph1GZQuvulYul/2Zxu0n4rZw49rZF1cNlry7MuV2fAFnegVY9aT3tlh506B1C25q5RaKVtp44cjMiOVw2BjJpm192TT6Lia7S5rW3EnFqm6CtdMAw8tHq8fpJxQjW23EL7EABTMh0Q7I53zfTXdgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756569086; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; 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Fri, 29 Aug 2025 05:59:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFykXfgNICbjEkfJnBPpkOxPSDr+eYSMsQ5lhRO6hW02Rnm+jpRgIW7gYoCOPp+nlFXtotyHQ== X-Received: by 2002:a05:600c:4747:b0:45b:627a:60cf with SMTP id 5b1f17b1804b1-45b627a62cbmr175327455e9.24.1756472382244; Fri, 29 Aug 2025 05:59:42 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 02/28] hw/i386/pc_piix.c: restrict isapc machine to 3.5G memory Date: Fri, 29 Aug 2025 14:59:09 +0200 Message-ID: <20250829125935.1526984-3-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756569087170116600 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Since the isapc machine is now limited to using 32-bit CPUs, add a hard res= triction so that the machine cannot be started with more than 3.5G memory. This matc= hes the default value for max_ram_below_4g if not specified and provides consistent behaviour betweem TCG and KVM accelerators. Signed-off-by: Mark Cave-Ayland Link: https://lore.kernel.org/r/20250828111057.468712-3-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 8f5fb3cf90b..9a3b5d88f08 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -461,6 +461,12 @@ static void pc_init_isa(MachineState *machine) warn_report("-cpu host is invalid for isapc machine, using pentium= 3"); } =20 + if (machine->ram_size > 3.5 * GiB) { + error_report("Too much memory for this machine: %" PRId64 " MiB, " + "maximum 3584 MiB", machine->ram_size / MiB); + exit(1); + } + pc_init1(machine, NULL); } #endif --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Fri, 29 Aug 2025 05:59:45 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGKjyQTnZgNBRmgGfrYpi8vfZVF3wS5qeq/xg88hLiz4h6gQC4vB5nhGyepkWCvKbZPpGRQsA== X-Received: by 2002:a05:6000:2507:b0:3c5:9e0f:7608 with SMTP id ffacd0b85a97d-3c5dcdf9aa8mr22990912f8f.46.1756472384553; Fri, 29 Aug 2025 05:59:44 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 03/28] hw/i386/pc_piix.c: remove include for loader.h Date: Fri, 29 Aug 2025 14:59:10 +0200 Message-ID: <20250829125935.1526984-4-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567206199124100 From: Mark Cave-Ayland This header is not required since the loader functionality is handled separ= ately by pc_memory_init() in pc.c. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-4-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 9a3b5d88f08..351986232d6 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -28,7 +28,6 @@ #include "qemu/units.h" #include "hw/char/parallel-isa.h" #include "hw/dma/i8257.h" -#include "hw/loader.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" #include "hw/i386/apic.h" --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756567624; cv=none; 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Fri, 29 Aug 2025 05:59:48 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHNKIkXCfFLWhM6a9uf7DBKbhrZNmDWLMJCRzxgtaKwZ14JTBev7AFZ9N4+Utt9WHdRzfP/uw== X-Received: by 2002:a05:600c:16c4:b0:45b:7e07:af4c with SMTP id 5b1f17b1804b1-45b7e07b13cmr22096515e9.16.1756472387666; Fri, 29 Aug 2025 05:59:47 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 04/28] hw/i386/pc_piix.c: inline pc_xen_hvm_init_pci() into pc_xen_hvm_init() Date: Fri, 29 Aug 2025 14:59:11 +0200 Message-ID: <20250829125935.1526984-5-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567627017124100 From: Mark Cave-Ayland This helps to simplify the initialisation of the Xen hvm machine. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Mark Cave-Ayland Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-5-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 13 ++++--------- 1 file changed, 4 insertions(+), 9 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 351986232d6..8e302dc013b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -471,14 +471,6 @@ static void pc_init_isa(MachineState *machine) #endif =20 #ifdef CONFIG_XEN -static void pc_xen_hvm_init_pci(MachineState *machine) -{ - const char *pci_type =3D xen_igd_gfx_pt_enabled() ? - TYPE_IGD_PASSTHROUGH_I440FX_PCI_DEVICE : TYPE_I440FX_PCI_D= EVICE; - - pc_init1(machine, pci_type); -} - static void pc_xen_hvm_init(MachineState *machine) { PCMachineState *pcms =3D PC_MACHINE(machine); @@ -488,7 +480,10 @@ static void pc_xen_hvm_init(MachineState *machine) exit(1); } =20 - pc_xen_hvm_init_pci(machine); + pc_init1(machine, xen_igd_gfx_pt_enabled() + ? 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Fri, 29 Aug 2025 05:59:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG2CfBWucnXYgR8I0GkNh4N43+6VnxgOlF1xi850U2/mOA6jE1ClniOyLHnR36Yn2JbkB17BA== X-Received: by 2002:a05:600c:1c07:b0:45b:7ffa:1bf8 with SMTP id 5b1f17b1804b1-45b7ffa1d60mr19678665e9.23.1756472390143; Fri, 29 Aug 2025 05:59:50 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 05/28] hw/i386/pc_piix.c: duplicate pc_init1() into pc_isa_init() Date: Fri, 29 Aug 2025 14:59:12 +0200 Message-ID: <20250829125935.1526984-6-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568374361116600 From: Mark Cave-Ayland This is to prepare for splitting the isapc machine into its own separate fi= le. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/r/20250828111057.468712-6-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 275 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 274 insertions(+), 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 8e302dc013b..60bf18c680b 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -435,6 +435,23 @@ static void pc_set_south_bridge(Object *obj, int value= , Error **errp) #ifdef CONFIG_ISAPC static void pc_init_isa(MachineState *machine) { + const char *pci_type =3D NULL; + PCMachineState *pcms =3D PC_MACHINE(machine); + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + X86MachineState *x86ms =3D X86_MACHINE(machine); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *system_io =3D get_system_io(); + Object *phb =3D NULL; + ISABus *isa_bus; + Object *piix4_pm =3D NULL; + qemu_irq smi_irq; + GSIState *gsi_state; + MemoryRegion *ram_memory; + MemoryRegion *pci_memory =3D NULL; + MemoryRegion *rom_memory =3D system_memory; + ram_addr_t lowmem; + uint64_t hole64_size =3D 0; + /* * There is a small chance that someone unintentionally passes "-cpu m= ax" * for the isapc machine, which will provide a much more modern 32-bit @@ -466,7 +483,263 @@ static void pc_init_isa(MachineState *machine) exit(1); } =20 - pc_init1(machine, NULL); + /* + * Calculate ram split, for memory below and above 4G. It's a bit + * complicated for backward compatibility reasons ... + * + * - Traditional split is 3.5G (lowmem =3D 0xe0000000). This is the + * default value for max_ram_below_4g now. + * + * - Then, to gigabyte align the memory, we move the split to 3G + * (lowmem =3D 0xc0000000). But only in case we have to split in + * the first place, i.e. ram_size is larger than (traditional) + * lowmem. And for new machine types (gigabyte_align =3D true) + * only, for live migration compatibility reasons. + * + * - Next the max-ram-below-4g option was added, which allowed to + * reduce lowmem to a smaller value, to allow a larger PCI I/O + * window below 4G. qemu doesn't enforce gigabyte alignment here, + * but prints a warning. + * + * - Finally max-ram-below-4g got updated to also allow raising lowme= m, + * so legacy non-PAE guests can get as much memory as possible in + * the 32bit address space below 4G. + * + * - Note that Xen has its own ram setup code in xen_ram_init(), + * called via xen_hvm_init_pc(). + * + * Examples: + * qemu -M pc-1.7 -m 4G (old default) -> 3584M low, 512M high + * qemu -M pc -m 4G (new default) -> 3072M low, 1024M high + * qemu -M pc,max-ram-below-4g=3D2G -m 4G -> 2048M low, 2048M h= igh + * qemu -M pc,max-ram-below-4g=3D4G -m 3968M -> 3968M low (=3D4G-1= 28M) + */ + if (xen_enabled()) { + xen_hvm_init_pc(pcms, &ram_memory); + } else { + ram_memory =3D machine->ram; + if (!pcms->max_ram_below_4g) { + pcms->max_ram_below_4g =3D 0xe0000000; /* default: 3.5G */ + } + lowmem =3D pcms->max_ram_below_4g; + if (machine->ram_size >=3D pcms->max_ram_below_4g) { + if (pcmc->gigabyte_align) { + if (lowmem > 0xc0000000) { + lowmem =3D 0xc0000000; + } + if (lowmem & (1 * GiB - 1)) { + warn_report("Large machine and max_ram_below_4g " + "(%" PRIu64 ") not a multiple of 1G; " + "possible bad performance.", + pcms->max_ram_below_4g); + } + } + } + + if (machine->ram_size >=3D lowmem) { + x86ms->above_4g_mem_size =3D machine->ram_size - lowmem; + x86ms->below_4g_mem_size =3D lowmem; + } else { + x86ms->above_4g_mem_size =3D 0; + x86ms->below_4g_mem_size =3D machine->ram_size; + } + } + + pc_machine_init_sgx_epc(pcms); + x86_cpus_init(x86ms, pcmc->default_cpu_version); + + if (kvm_enabled()) { + kvmclock_create(pcmc->kvmclock_create_always); + } + + if (pcmc->pci_enabled) { + pci_memory =3D g_new(MemoryRegion, 1); + memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); + rom_memory =3D pci_memory; + + phb =3D OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); + object_property_add_child(OBJECT(machine), "i440fx", phb); + object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, + OBJECT(ram_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, + OBJECT(pci_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, + OBJECT(system_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, + OBJECT(system_io), &error_fatal); + object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, + x86ms->below_4g_mem_size, &error_fatal); + object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, + x86ms->above_4g_mem_size, &error_fatal); + object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, + &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + + pcms->pcibus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); + pci_bus_map_irqs(pcms->pcibus, + xen_enabled() ? xen_pci_slot_get_pirq + : pc_pci_slot_get_pirq); + + hole64_size =3D object_property_get_uint(phb, + PCI_HOST_PROP_PCI_HOLE64_SI= ZE, + &error_abort); + } + + /* allocate ram and load rom/bios */ + if (!xen_enabled()) { + pc_memory_init(pcms, system_memory, rom_memory, hole64_size); + } else { + assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + + x86ms->above_4g_mem_size); + + pc_system_flash_cleanup_unused(pcms); + if (machine->kernel_filename !=3D NULL) { + /* For xen HVM direct kernel boot, load linux here */ + xen_load_linux(pcms); + } + } + + gsi_state =3D pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); + + if (pcmc->pci_enabled) { + PCIDevice *pci_dev; + DeviceState *dev; + size_t i; + + pci_dev =3D pci_new_multifunction(-1, pcms->south_bridge); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-pic", false, + &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-pit", false, + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); + dev =3D DEVICE(pci_dev); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); + } + pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal); + + if (xen_enabled()) { + pci_device_set_intx_routing_notifier( + pci_dev, piix_intx_routing_notifier_xen); + + /* + * Xen supports additional interrupt routes from the PCI devic= es to + * the IOAPIC: the four pins of each PCI device on the bus are= also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. + */ + pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev, + XEN_IOAPIC_NUM_PIRQS); + } + + isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); + x86ms->rtc =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci= _dev), + "rtc")); + piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide= ")); + pci_ide_create_devs(PCI_DEVICE(dev)); + pcms->idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); + pcms->idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); + } else { + uint32_t irq; + + isa_bus =3D isa_bus_new(NULL, system_memory, system_io, + &error_abort); + isa_bus_register_input_irqs(isa_bus, x86ms->gsi); + + x86ms->rtc =3D isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); + isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); + irq =3D object_property_get_uint(OBJECT(x86ms->rtc), "irq", + &error_fatal); + isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq); + + i8257_dma_init(OBJECT(machine), isa_bus, 0); + pcms->hpet_enabled =3D false; + } + + if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { + pc_i8259_create(isa_bus, gsi_state->i8259_irq); + } + + if (phb) { + ioapic_init_gsi(gsi_state, phb); + } + + if (tcg_enabled()) { + x86_register_ferr_irq(x86ms->gsi[13]); + } + + pc_vga_init(isa_bus, pcmc->pci_enabled ? pcms->pcibus : NULL); + + /* init basic PC hardware */ + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, + !MACHINE_CLASS(pcmc)->no_floppy, 0x4); + + pc_nic_init(pcmc, isa_bus, pcms->pcibus); + +#ifdef CONFIG_IDE_ISA + if (!pcmc->pci_enabled) { + DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; + int i; + + ide_drive_get(hd, ARRAY_SIZE(hd)); + for (i =3D 0; i < MAX_IDE_BUS; i++) { + ISADevice *dev; + char busname[] =3D "ide.0"; + dev =3D isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], + ide_irq[i], + hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i += 1]); + /* + * The ide bus name is ide.0 for the first bus and ide.1 for t= he + * second one. + */ + busname[4] =3D '0' + i; + pcms->idebus[i] =3D qdev_get_child_bus(DEVICE(dev), busname); + } + } +#endif + + if (piix4_pm) { + smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); + + qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_ir= q); + pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"= )); + /* TODO: Populate SPD eeprom data. */ + smbus_eeprom_init(pcms->smbus, 8, NULL, 0); + + object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_P= ROP, + TYPE_HOTPLUG_HANDLER, + (Object **)&x86ms->acpi_dev, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG); + object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_P= ROP, + piix4_pm, &error_abort); + } + + if (machine->nvdimms_state->is_enabled) { + nvdimm_init_acpi_state(machine->nvdimms_state, system_io, + x86_nvdimm_acpi_dsmio, + x86ms->fw_cfg, OBJECT(pcms)); + } + +#if defined(CONFIG_IGVM) + /* Apply guest state from IGVM if supplied */ + if (x86ms->igvm) { + if (IGVM_CFG_GET_CLASS(x86ms->igvm) + ->process(x86ms->igvm, machine->cgs, false, &error_fatal) = < 0) { + g_assert_not_reached(); + } + } +#endif } #endif =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 05:59:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IG8rzu4K8ENJn+8O8znIoQn8j8L+2WKILVbtdkbTSl3ULdrpo38xzIyAOxmy15cqzXlIBYSPQ== X-Received: by 2002:a05:6000:18ad:b0:3b7:940e:6529 with SMTP id ffacd0b85a97d-3c5da73ee7bmr22614948f8f.10.1756472392874; Fri, 29 Aug 2025 05:59:52 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 06/28] hw/i386/pc_piix.c: remove pcmc->pci_enabled dependent initialisation from pc_init_isa() Date: Fri, 29 Aug 2025 14:59:13 +0200 Message-ID: <20250829125935.1526984-7-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568685266124100 From: Mark Cave-Ayland PCI code will never be used for an isapc machine. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-7-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 120 ++++++---------------------------------------- 1 file changed, 15 insertions(+), 105 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 60bf18c680b..f1b4468d0a1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -435,19 +435,17 @@ static void pc_set_south_bridge(Object *obj, int valu= e, Error **errp) #ifdef CONFIG_ISAPC static void pc_init_isa(MachineState *machine) { - const char *pci_type =3D NULL; PCMachineState *pcms =3D PC_MACHINE(machine); PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); X86MachineState *x86ms =3D X86_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *system_io =3D get_system_io(); - Object *phb =3D NULL; ISABus *isa_bus; Object *piix4_pm =3D NULL; qemu_irq smi_irq; + uint32_t irq; GSIState *gsi_state; MemoryRegion *ram_memory; - MemoryRegion *pci_memory =3D NULL; MemoryRegion *rom_memory =3D system_memory; ram_addr_t lowmem; uint64_t hole64_size =3D 0; @@ -552,39 +550,6 @@ static void pc_init_isa(MachineState *machine) kvmclock_create(pcmc->kvmclock_create_always); } =20 - if (pcmc->pci_enabled) { - pci_memory =3D g_new(MemoryRegion, 1); - memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - rom_memory =3D pci_memory; - - phb =3D OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); - object_property_add_child(OBJECT(machine), "i440fx", phb); - object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, - OBJECT(ram_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, - OBJECT(pci_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, - OBJECT(system_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, - OBJECT(system_io), &error_fatal); - object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, - x86ms->below_4g_mem_size, &error_fatal); - object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, - x86ms->above_4g_mem_size, &error_fatal); - object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, - &error_fatal); - sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); - - pcms->pcibus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); - pci_bus_map_irqs(pcms->pcibus, - xen_enabled() ? xen_pci_slot_get_pirq - : pc_pci_slot_get_pirq); - - hole64_size =3D object_property_get_uint(phb, - PCI_HOST_PROP_PCI_HOLE64_SI= ZE, - &error_abort); - } - /* allocate ram and load rom/bios */ if (!xen_enabled()) { pc_memory_init(pcms, system_memory, rom_memory, hole64_size); @@ -599,92 +564,37 @@ static void pc_init_isa(MachineState *machine) } } =20 - gsi_state =3D pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); + gsi_state =3D pc_gsi_create(&x86ms->gsi, false); =20 - if (pcmc->pci_enabled) { - PCIDevice *pci_dev; - DeviceState *dev; - size_t i; + isa_bus =3D isa_bus_new(NULL, system_memory, system_io, + &error_abort); + isa_bus_register_input_irqs(isa_bus, x86ms->gsi); =20 - pci_dev =3D pci_new_multifunction(-1, pcms->south_bridge); - object_property_set_bool(OBJECT(pci_dev), "has-usb", - machine_usb(machine), &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-acpi", - x86_machine_is_acpi_enabled(x86ms), - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pic", false, - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pit", false, - &error_abort); - qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); - object_property_set_bool(OBJECT(pci_dev), "smm-enabled", - x86_machine_is_smm_enabled(x86ms), - &error_abort); - dev =3D DEVICE(pci_dev); - for (i =3D 0; i < ISA_NUM_IRQS; i++) { - qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); - } - pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal); + x86ms->rtc =3D isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); + isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); + irq =3D object_property_get_uint(OBJECT(x86ms->rtc), "irq", + &error_fatal); + isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq); =20 - if (xen_enabled()) { - pci_device_set_intx_routing_notifier( - pci_dev, piix_intx_routing_notifier_xen); - - /* - * Xen supports additional interrupt routes from the PCI devic= es to - * the IOAPIC: the four pins of each PCI device on the bus are= also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. - */ - pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev, - XEN_IOAPIC_NUM_PIRQS); - } - - isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); - x86ms->rtc =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci= _dev), - "rtc")); - piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); - dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide= ")); - pci_ide_create_devs(PCI_DEVICE(dev)); - pcms->idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); - pcms->idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); - } else { - uint32_t irq; - - isa_bus =3D isa_bus_new(NULL, system_memory, system_io, - &error_abort); - isa_bus_register_input_irqs(isa_bus, x86ms->gsi); - - x86ms->rtc =3D isa_new(TYPE_MC146818_RTC); - qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); - isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); - irq =3D object_property_get_uint(OBJECT(x86ms->rtc), "irq", - &error_fatal); - isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq); - - i8257_dma_init(OBJECT(machine), isa_bus, 0); - pcms->hpet_enabled =3D false; - } + i8257_dma_init(OBJECT(machine), isa_bus, 0); + pcms->hpet_enabled =3D false; =20 if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); } =20 - if (phb) { - ioapic_init_gsi(gsi_state, phb); - } - if (tcg_enabled()) { x86_register_ferr_irq(x86ms->gsi[13]); } =20 - pc_vga_init(isa_bus, pcmc->pci_enabled ? pcms->pcibus : NULL); + pc_vga_init(isa_bus, NULL); =20 /* init basic PC hardware */ pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, !MACHINE_CLASS(pcmc)->no_floppy, 0x4); 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Fri, 29 Aug 2025 05:59:55 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF+sj9MyI6AWkXcd0EExH+cpJtxqqUhsI0xFlPqbBpk6/FMZhIHMbtY4fdp7F+YMVpvzx5SkA== X-Received: by 2002:a05:600c:4511:b0:456:1156:e5f5 with SMTP id 5b1f17b1804b1-45b517d27f6mr276577775e9.31.1756472395345; Fri, 29 Aug 2025 05:59:55 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland Subject: [PULL 07/28] hw/i386/pc_piix.c: remove igvm initialisation from pc_init_isa() Date: Fri, 29 Aug 2025 14:59:14 +0200 Message-ID: <20250829125935.1526984-8-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568792360124100 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland According to the QEMU documentation igvm is only supported for the pc and q= 35 machines so remove igvm support from the isapc machine. Signed-off-by: Mark Cave-Ayland Link: https://lore.kernel.org/r/20250828111057.468712-8-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f1b4468d0a1..5ae265bd538 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -640,16 +640,6 @@ static void pc_init_isa(MachineState *machine) x86_nvdimm_acpi_dsmio, x86ms->fw_cfg, OBJECT(pcms)); } - -#if defined(CONFIG_IGVM) - /* Apply guest state from IGVM if supplied */ - if (x86ms->igvm) { - if (IGVM_CFG_GET_CLASS(x86ms->igvm) - ->process(x86ms->igvm, machine->cgs, false, &error_fatal) = < 0) { - g_assert_not_reached(); - } - } -#endif } #endif =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 29 Aug 2025 05:59:58 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHt0cX2L/zzLDzf7Rh9RUDJy1nUsZVdlXOQZJTOPoem8luhXtgrmrOY7rCXPWMS+/1u1hgagg== X-Received: by 2002:a05:6000:26d2:b0:3d0:d6e6:5d76 with SMTP id ffacd0b85a97d-3d0d6e664b1mr1445311f8f.55.1756472397658; Fri, 29 Aug 2025 05:59:57 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 08/28] hw/i386/pc_piix.c: remove SMI and piix4_pm initialisation from pc_init_isa() Date: Fri, 29 Aug 2025 14:59:15 +0200 Message-ID: <20250829125935.1526984-9-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567951024124100 From: Mark Cave-Ayland These are based upon the PIIX4 PCI chipset and so can never be used on an i= sapc machine. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-9-mark.caveayland@nut= anix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 19 ------------------- 1 file changed, 19 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 5ae265bd538..57b02da5a82 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -441,8 +441,6 @@ static void pc_init_isa(MachineState *machine) MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *system_io =3D get_system_io(); ISABus *isa_bus; - Object *piix4_pm =3D NULL; - qemu_irq smi_irq; uint32_t irq; GSIState *gsi_state; MemoryRegion *ram_memory; @@ -618,23 +616,6 @@ static void pc_init_isa(MachineState *machine) } #endif =20 - if (piix4_pm) { - smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - - qdev_connect_gpio_out_named(DEVICE(piix4_pm), "smi-irq", 0, smi_ir= q); - pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"= )); - /* TODO: Populate SPD eeprom data. */ - smbus_eeprom_init(pcms->smbus, 8, NULL, 0); - - object_property_add_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_P= ROP, - TYPE_HOTPLUG_HANDLER, - (Object **)&x86ms->acpi_dev, - object_property_allow_set_link, - OBJ_PROP_LINK_STRONG); - object_property_set_link(OBJECT(machine), PC_MACHINE_ACPI_DEVICE_P= ROP, - piix4_pm, &error_abort); - } - if (machine->nvdimms_state->is_enabled) { nvdimm_init_acpi_state(machine->nvdimms_state, system_io, x86_nvdimm_acpi_dsmio, --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756573242; cv=none; d=zohomail.com; s=zohoarc; b=DQEnNmThO6J0oMjnXchTrtnenPaO6hO5LhXbUYrWv5NnPHMEE8/prHvIOO/f5lKXpyQczX+2V0lyaccJLb+xM4whxU5daUdZyj5xc9uq75OPaMkdw/z8kBRMinPUSSECaL6psiI8xZa3Jw7Ptedy8pz7FCD6i7vfdaxfv3ox0Ec= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 06:00:00 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH0Hn5+Og9blKbVwxOitJAIRTpFJsvQ0/ZpPEwV3a+lVvqexgSnn9w2yQfnmVB8oy91IDmjeQ== X-Received: by 2002:a05:6000:18aa:b0:3cd:7de0:729f with SMTP id ffacd0b85a97d-3cd7de074a5mr5454186f8f.4.1756472400157; Fri, 29 Aug 2025 06:00:00 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Xiaoyao Li Subject: [PULL 09/28] hw/i386/pc_piix.c: remove SGX initialisation from pc_init_isa() Date: Fri, 29 Aug 2025 14:59:16 +0200 Message-ID: <20250829125935.1526984-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756573244470124100 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland The Intel SGX instructions only exist on recent CPUs and so would never be = available on a CPU from the pre-PCI era. Signed-off-by: Mark Cave-Ayland Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-10-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 57b02da5a82..9a2eee8ab0a 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -541,7 +541,6 @@ static void pc_init_isa(MachineState *machine) } } =20 - pc_machine_init_sgx_epc(pcms); x86_cpus_init(x86ms, pcmc->default_cpu_version); =20 if (kvm_enabled()) { --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756567469; cv=none; d=zohomail.com; s=zohoarc; b=H9c2nxlhSzTLIPkqjGz2USkguTsWc8ggxZ7579nr/G2rcSZORWsj427X9u88lHzH1u5dGShDLuUimOUjgER94PdPPNEtcJfTl2YICIRXFkdNpYGnOQN/cAx0GhB9BJHavOl19ZEbYOdY+Vw8fUAYj+kRbUD9D/x9fgc+WFxVGVc= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 06:00:03 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEcBF57RSIt+clYMAReNX5cm1VeM86TgVVqqJXUuHT1aHDuaqYYqixAjMmUEzghRvC0Dx9pXA== X-Received: by 2002:a05:6000:40dc:b0:3c9:469d:c087 with SMTP id ffacd0b85a97d-3c9469dc445mr15812243f8f.25.1756472403287; Fri, 29 Aug 2025 06:00:03 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 10/28] hw/i386/pc_piix.c: remove nvdimm initialisation from pc_init_isa() Date: Fri, 29 Aug 2025 14:59:17 +0200 Message-ID: <20250829125935.1526984-11-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567471253124100 From: Mark Cave-Ayland NVDIMMs cannot be used by PCs from a pre-PCI era. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-11-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 9a2eee8ab0a..daf63a326b6 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -614,12 +614,6 @@ static void pc_init_isa(MachineState *machine) } } #endif - - if (machine->nvdimms_state->is_enabled) { - nvdimm_init_acpi_state(machine->nvdimms_state, system_io, - x86_nvdimm_acpi_dsmio, - x86ms->fw_cfg, OBJECT(pcms)); - } } #endif =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Fri, 29 Aug 2025 06:00:06 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHeRExpKznG0FMDzIDcV7empYGImPiru2lwiaqSFyXZr9Lf9EUeIxynWnRcR61ivvoyNeEtMw== X-Received: by 2002:a05:6000:178b:b0:3c9:a722:e189 with SMTP id ffacd0b85a97d-3c9a722e3e6mr13429039f8f.62.1756472405790; Fri, 29 Aug 2025 06:00:05 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 11/28] hw/i386/pc_piix.c: simplify RAM size logic in pc_init_isa() Date: Fri, 29 Aug 2025 14:59:18 +0200 Message-ID: <20250829125935.1526984-12-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568641880116600 From: Mark Cave-Ayland All isapc machines must have 32-bit CPUs and so the RAM split logic can be = hardcoded accordingly. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/r/20250828111057.468712-12-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 58 ++++------------------------------------------- 1 file changed, 4 insertions(+), 54 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index daf63a326b6..0bc033943ca 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -445,7 +445,6 @@ static void pc_init_isa(MachineState *machine) GSIState *gsi_state; MemoryRegion *ram_memory; MemoryRegion *rom_memory =3D system_memory; - ram_addr_t lowmem; uint64_t hole64_size =3D 0; =20 /* @@ -480,65 +479,16 @@ static void pc_init_isa(MachineState *machine) } =20 /* - * Calculate ram split, for memory below and above 4G. It's a bit - * complicated for backward compatibility reasons ... - * - * - Traditional split is 3.5G (lowmem =3D 0xe0000000). This is the - * default value for max_ram_below_4g now. - * - * - Then, to gigabyte align the memory, we move the split to 3G - * (lowmem =3D 0xc0000000). But only in case we have to split in - * the first place, i.e. ram_size is larger than (traditional) - * lowmem. And for new machine types (gigabyte_align =3D true) - * only, for live migration compatibility reasons. - * - * - Next the max-ram-below-4g option was added, which allowed to - * reduce lowmem to a smaller value, to allow a larger PCI I/O - * window below 4G. qemu doesn't enforce gigabyte alignment here, - * but prints a warning. - * - * - Finally max-ram-below-4g got updated to also allow raising lowme= m, - * so legacy non-PAE guests can get as much memory as possible in - * the 32bit address space below 4G. - * - * - Note that Xen has its own ram setup code in xen_ram_init(), - * called via xen_hvm_init_pc(). - * - * Examples: - * qemu -M pc-1.7 -m 4G (old default) -> 3584M low, 512M high - * qemu -M pc -m 4G (new default) -> 3072M low, 1024M high - * qemu -M pc,max-ram-below-4g=3D2G -m 4G -> 2048M low, 2048M h= igh - * qemu -M pc,max-ram-below-4g=3D4G -m 3968M -> 3968M low (=3D4G-1= 28M) + * There is no RAM split for the isapc machine */ if (xen_enabled()) { xen_hvm_init_pc(pcms, &ram_memory); } else { ram_memory =3D machine->ram; - if (!pcms->max_ram_below_4g) { - pcms->max_ram_below_4g =3D 0xe0000000; /* default: 3.5G */ - } - lowmem =3D pcms->max_ram_below_4g; - if (machine->ram_size >=3D pcms->max_ram_below_4g) { - if (pcmc->gigabyte_align) { - if (lowmem > 0xc0000000) { - lowmem =3D 0xc0000000; - } - if (lowmem & (1 * GiB - 1)) { - warn_report("Large machine and max_ram_below_4g " - "(%" PRIu64 ") not a multiple of 1G; " - "possible bad performance.", - pcms->max_ram_below_4g); - } - } - } =20 - if (machine->ram_size >=3D lowmem) { - x86ms->above_4g_mem_size =3D machine->ram_size - lowmem; - x86ms->below_4g_mem_size =3D lowmem; - } else { - x86ms->above_4g_mem_size =3D 0; - x86ms->below_4g_mem_size =3D machine->ram_size; - } + pcms->max_ram_below_4g =3D 3.5 * GiB; + x86ms->above_4g_mem_size =3D 0; + x86ms->below_4g_mem_size =3D machine->ram_size; } =20 x86_cpus_init(x86ms, pcmc->default_cpu_version); --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 06:00:09 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFX+JoRBf+P/lbVcUBADTBMTlEdHqi1xnX586DfxEksSoVDWPSvH7YGXB8suNz7FTMMm2eKqw== X-Received: by 2002:a05:600c:4511:b0:456:10a8:ff7 with SMTP id 5b1f17b1804b1-45b517dd3admr225707315e9.28.1756472409190; Fri, 29 Aug 2025 06:00:09 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 12/28] hw/i386/pc_piix.c: hardcode hole64_size to 0 in pc_init_isa() Date: Fri, 29 Aug 2025 14:59:19 +0200 Message-ID: <20250829125935.1526984-13-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756574527474116600 From: Mark Cave-Ayland All isapc machines must have 32-bit CPUs and have no PCI 64-bit hole so it = can be hardcoded to 0. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-13-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 0bc033943ca..66dc4a5186e 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -445,7 +445,6 @@ static void pc_init_isa(MachineState *machine) GSIState *gsi_state; MemoryRegion *ram_memory; MemoryRegion *rom_memory =3D system_memory; - uint64_t hole64_size =3D 0; =20 /* * There is a small chance that someone unintentionally passes "-cpu m= ax" @@ -499,7 +498,7 @@ static void pc_init_isa(MachineState *machine) =20 /* allocate ram and load rom/bios */ if (!xen_enabled()) { - pc_memory_init(pcms, system_memory, rom_memory, hole64_size); + pc_memory_init(pcms, system_memory, rom_memory, 0); } else { assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); 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Fri, 29 Aug 2025 06:00:12 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFY6a5M++V57bS+wpK+MuOfDStkPzeN9MtAnX3m6Z8KIV5YtsAP4l11iMRj4BKW0y6o5wcGeQ== X-Received: by 2002:a05:6000:40dd:b0:3a4:d6ed:8df8 with SMTP id ffacd0b85a97d-3c5dc734927mr21516430f8f.39.1756472412419; Fri, 29 Aug 2025 06:00:12 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 13/28] hw/i386/pc_piix.c: remove pc_system_flash_cleanup_unused() from pc_init_isa() Date: Fri, 29 Aug 2025 14:59:20 +0200 Message-ID: <20250829125935.1526984-14-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567570635116600 From: Mark Cave-Ayland This function contains 'assert(PC_MACHINE_GET_CLASS(pcms)->pci_enabled)' an= d so we can safely assume that it should never be used for the isapc machine. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Link: https://lore.kernel.org/r/20250828111057.468712-14-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 66dc4a5186e..fb936748bd1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -503,7 +503,6 @@ static void pc_init_isa(MachineState *machine) assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); =20 - pc_system_flash_cleanup_unused(pcms); if (machine->kernel_filename !=3D NULL) { /* For xen HVM direct kernel boot, load linux here */ xen_load_linux(pcms); --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Fri, 29 Aug 2025 06:00:15 -0700 (PDT) X-Google-Smtp-Source: AGHT+IEZjB/BRd9ep+ScA2MqOT8Eq1UUz0XEjActCby77NbkoMJIeuOsI/S5OSNJmO8sagmHTw1J+w== X-Received: by 2002:a05:6000:2289:b0:3c9:58b0:dad4 with SMTP id ffacd0b85a97d-3c958b0db85mr15058753f8f.35.1756472414891; Fri, 29 Aug 2025 06:00:14 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 14/28] hw/i386/pc_piix.c: always initialise ISA IDE drives in pc_init_isa() Date: Fri, 29 Aug 2025 14:59:21 +0200 Message-ID: <20250829125935.1526984-15-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568260439124100 From: Mark Cave-Ayland By definition an isapc machine must always use ISA IDE drives so ensure tha= t they are always enabled. At the same time also remove the surrounding CONFIG_IDE= _ISA define since it will be enabled via the ISAPC Kconfig. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-15-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 35 +++++++++++++++-------------------- 1 file changed, 15 insertions(+), 20 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index fb936748bd1..72ddd9b149d 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -445,6 +445,8 @@ static void pc_init_isa(MachineState *machine) GSIState *gsi_state; MemoryRegion *ram_memory; MemoryRegion *rom_memory =3D system_memory; + DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; + int i; =20 /* * There is a small chance that someone unintentionally passes "-cpu m= ax" @@ -541,27 +543,20 @@ static void pc_init_isa(MachineState *machine) =20 pc_nic_init(pcmc, isa_bus, NULL); =20 -#ifdef CONFIG_IDE_ISA - if (!pcmc->pci_enabled) { - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - int i; - - ide_drive_get(hd, ARRAY_SIZE(hd)); - for (i =3D 0; i < MAX_IDE_BUS; i++) { - ISADevice *dev; - char busname[] =3D "ide.0"; - dev =3D isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], - ide_irq[i], - hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i += 1]); - /* - * The ide bus name is ide.0 for the first bus and ide.1 for t= he - * second one. - */ - busname[4] =3D '0' + i; - pcms->idebus[i] =3D qdev_get_child_bus(DEVICE(dev), busname); - } + ide_drive_get(hd, ARRAY_SIZE(hd)); + for (i =3D 0; i < MAX_IDE_BUS; i++) { + ISADevice *dev; + char busname[] =3D "ide.0"; + dev =3D isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], + ide_irq[i], + hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]= ); + /* + * The ide bus name is ide.0 for the first bus and ide.1 for the + * second one. + */ + busname[4] =3D '0' + i; + pcms->idebus[i] =3D qdev_get_child_bus(DEVICE(dev), busname); } -#endif } #endif =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; 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Fri, 29 Aug 2025 06:00:19 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGF1UfZ01N6dZ/xHrZ7Z/scelEM3D0hdN1H4/pJIiCA6v6p/WnkrhleIqeaARm+GK/2zeraIw== X-Received: by 2002:adf:a155:0:b0:3ce:9872:fd3 with SMTP id ffacd0b85a97d-3ce987213dfmr2758822f8f.34.1756472418587; Fri, 29 Aug 2025 06:00:18 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 15/28] hw/i386/pc_piix.c: assume pcmc->pci_enabled is always true in pc_init1() Date: Fri, 29 Aug 2025 14:59:22 +0200 Message-ID: <20250829125935.1526984-16-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756569478134124100 From: Mark Cave-Ayland PCI is always enabled on the pc-i440fx machine so hardcode the relevant log= ic in pc_init1(). Add an assert() to ensure that this is always the case at runtime as already done in pc_q35_init(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-16-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 192 ++++++++++++++++++---------------------------- 1 file changed, 76 insertions(+), 116 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 72ddd9b149d..3ea77b2c44f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -125,6 +125,11 @@ static void pc_init1(MachineState *machine, const char= *pci_type) MemoryRegion *rom_memory =3D system_memory; ram_addr_t lowmem; uint64_t hole64_size =3D 0; + PCIDevice *pci_dev; + DeviceState *dev; + size_t i; + + assert(pcmc->pci_enabled); =20 /* * Calculate ram split, for memory below and above 4G. It's a bit @@ -195,38 +200,36 @@ static void pc_init1(MachineState *machine, const cha= r *pci_type) kvmclock_create(pcmc->kvmclock_create_always); } =20 - if (pcmc->pci_enabled) { - pci_memory =3D g_new(MemoryRegion, 1); - memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - rom_memory =3D pci_memory; + pci_memory =3D g_new(MemoryRegion, 1); + memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); + rom_memory =3D pci_memory; =20 - phb =3D OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); - object_property_add_child(OBJECT(machine), "i440fx", phb); - object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, - OBJECT(ram_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, - OBJECT(pci_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, - OBJECT(system_memory), &error_fatal); - object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, - OBJECT(system_io), &error_fatal); - object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, - x86ms->below_4g_mem_size, &error_fatal); - object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, - x86ms->above_4g_mem_size, &error_fatal); - object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, - &error_fatal); - sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); + phb =3D OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); + object_property_add_child(OBJECT(machine), "i440fx", phb); + object_property_set_link(phb, PCI_HOST_PROP_RAM_MEM, + OBJECT(ram_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_PCI_MEM, + OBJECT(pci_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_SYSTEM_MEM, + OBJECT(system_memory), &error_fatal); + object_property_set_link(phb, PCI_HOST_PROP_IO_MEM, + OBJECT(system_io), &error_fatal); + object_property_set_uint(phb, PCI_HOST_BELOW_4G_MEM_SIZE, + x86ms->below_4g_mem_size, &error_fatal); + object_property_set_uint(phb, PCI_HOST_ABOVE_4G_MEM_SIZE, + x86ms->above_4g_mem_size, &error_fatal); + object_property_set_str(phb, I440FX_HOST_PROP_PCI_TYPE, pci_type, + &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(phb), &error_fatal); =20 - pcms->pcibus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); - pci_bus_map_irqs(pcms->pcibus, - xen_enabled() ? xen_pci_slot_get_pirq - : pc_pci_slot_get_pirq); + pcms->pcibus =3D PCI_BUS(qdev_get_child_bus(DEVICE(phb), "pci.0")); + pci_bus_map_irqs(pcms->pcibus, + xen_enabled() ? xen_pci_slot_get_pirq + : pc_pci_slot_get_pirq); =20 - hole64_size =3D object_property_get_uint(phb, - PCI_HOST_PROP_PCI_HOLE64_SI= ZE, - &error_abort); - } + hole64_size =3D object_property_get_uint(phb, + PCI_HOST_PROP_PCI_HOLE64_SIZE, + &error_abort); =20 /* allocate ram and load rom/bios */ if (!xen_enabled()) { @@ -242,72 +245,51 @@ static void pc_init1(MachineState *machine, const cha= r *pci_type) } } =20 - gsi_state =3D pc_gsi_create(&x86ms->gsi, pcmc->pci_enabled); + gsi_state =3D pc_gsi_create(&x86ms->gsi, true); =20 - if (pcmc->pci_enabled) { - PCIDevice *pci_dev; - DeviceState *dev; - size_t i; - - pci_dev =3D pci_new_multifunction(-1, pcms->south_bridge); - object_property_set_bool(OBJECT(pci_dev), "has-usb", - machine_usb(machine), &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-acpi", - x86_machine_is_acpi_enabled(x86ms), - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pic", false, - &error_abort); - object_property_set_bool(OBJECT(pci_dev), "has-pit", false, - &error_abort); - qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); - object_property_set_bool(OBJECT(pci_dev), "smm-enabled", - x86_machine_is_smm_enabled(x86ms), - &error_abort); - dev =3D DEVICE(pci_dev); - for (i =3D 0; i < ISA_NUM_IRQS; i++) { - qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); - } - pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal); - - if (xen_enabled()) { - pci_device_set_intx_routing_notifier( - pci_dev, piix_intx_routing_notifier_xen); - - /* - * Xen supports additional interrupt routes from the PCI devic= es to - * the IOAPIC: the four pins of each PCI device on the bus are= also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. - */ - pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev, - XEN_IOAPIC_NUM_PIRQS); - } - - isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); - x86ms->rtc =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci= _dev), - "rtc")); - piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); - dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide= ")); - pci_ide_create_devs(PCI_DEVICE(dev)); - pcms->idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); - pcms->idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); - } else { - uint32_t irq; - - isa_bus =3D isa_bus_new(NULL, system_memory, system_io, - &error_abort); - isa_bus_register_input_irqs(isa_bus, x86ms->gsi); - - x86ms->rtc =3D isa_new(TYPE_MC146818_RTC); - qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); - isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); - irq =3D object_property_get_uint(OBJECT(x86ms->rtc), "irq", - &error_fatal); - isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq); - - i8257_dma_init(OBJECT(machine), isa_bus, 0); - pcms->hpet_enabled =3D false; + pci_dev =3D pci_new_multifunction(-1, pcms->south_bridge); + object_property_set_bool(OBJECT(pci_dev), "has-usb", + machine_usb(machine), &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-acpi", + x86_machine_is_acpi_enabled(x86ms), + &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-pic", false, + &error_abort); + object_property_set_bool(OBJECT(pci_dev), "has-pit", false, + &error_abort); + qdev_prop_set_uint32(DEVICE(pci_dev), "smb_io_base", 0xb100); + object_property_set_bool(OBJECT(pci_dev), "smm-enabled", + x86_machine_is_smm_enabled(x86ms), + &error_abort); + dev =3D DEVICE(pci_dev); + for (i =3D 0; i < ISA_NUM_IRQS; i++) { + qdev_connect_gpio_out_named(dev, "isa-irqs", i, x86ms->gsi[i]); } + pci_realize_and_unref(pci_dev, pcms->pcibus, &error_fatal); + + if (xen_enabled()) { + pci_device_set_intx_routing_notifier( + pci_dev, piix_intx_routing_notifier_xen); + + /* + * Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. + */ + pci_bus_irqs(pcms->pcibus, xen_intx_set_irq, pci_dev, + XEN_IOAPIC_NUM_PIRQS); + } + + isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(pci_dev), "isa.0")); + x86ms->rtc =3D ISA_DEVICE(object_resolve_path_component(OBJECT(pci_dev= ), + "rtc")); + piix4_pm =3D object_resolve_path_component(OBJECT(pci_dev), "pm"); + dev =3D DEVICE(object_resolve_path_component(OBJECT(pci_dev), "ide")); + pci_ide_create_devs(PCI_DEVICE(dev)); + pcms->idebus[0] =3D qdev_get_child_bus(dev, "ide.0"); + pcms->idebus[1] =3D qdev_get_child_bus(dev, "ide.1"); + =20 if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { pc_i8259_create(isa_bus, gsi_state->i8259_irq); @@ -321,7 +303,7 @@ static void pc_init1(MachineState *machine, const char = *pci_type) x86_register_ferr_irq(x86ms->gsi[13]); } =20 - pc_vga_init(isa_bus, pcmc->pci_enabled ? pcms->pcibus : NULL); + pc_vga_init(isa_bus, pcms->pcibus); =20 /* init basic PC hardware */ pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, @@ -329,28 +311,6 @@ static void pc_init1(MachineState *machine, const char= *pci_type) =20 pc_nic_init(pcmc, isa_bus, pcms->pcibus); =20 -#ifdef CONFIG_IDE_ISA - if (!pcmc->pci_enabled) { - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - int i; - - ide_drive_get(hd, ARRAY_SIZE(hd)); - for (i =3D 0; i < MAX_IDE_BUS; i++) { - ISADevice *dev; - char busname[] =3D "ide.0"; - dev =3D isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], - ide_irq[i], - hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i += 1]); - /* - * The ide bus name is ide.0 for the first bus and ide.1 for t= he - * second one. - */ - busname[4] =3D '0' + i; - pcms->idebus[i] =3D qdev_get_child_bus(DEVICE(dev), busname); - } - } -#endif - if (piix4_pm) { smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Fri, 29 Aug 2025 06:00:22 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGM36Wo0fGXggWQDnWWH4VL8xKO3DiinY19cQeFX+2iWAhLjwKUpW9KtQTr1PyqqCRS29bqcg== X-Received: by 2002:a5d:64e1:0:b0:3b6:436:b8ea with SMTP id ffacd0b85a97d-3c5da83c601mr18910133f8f.6.1756472421523; Fri, 29 Aug 2025 06:00:21 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , Bernhard Beschow , Xiaoyao Li Subject: [PULL 16/28] hw/i386: move isapc machine to separate isapc.c file Date: Fri, 29 Aug 2025 14:59:23 +0200 Message-ID: <20250829125935.1526984-17-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756569007094124100 Content-Type: text/plain; charset="utf-8" From: Mark Cave-Ayland Now that pc_init_isa() is independent of any PCI initialisation, move it in= to a separate isapc.c file including the ISA IDE variables which are now no long= er needed for the pc-i440fx machine. This enables us to finally fix the depend= ency of ISAPC on I440FX in hw/i386/Kconfig. Note that as part of the move to a separate file we can see that the licenc= e text is a verbatim copy of the MIT licence. The text originates from commit 1df9= 12cf9e ("VL license of the day is MIT/BSD") so we can be sure that this was the or= iginal intent. As a consequence we can update the file header to use a SPDX tag as= per the current project contribution guidelines. Signed-off-by: Mark Cave-Ayland Reviewed-by: Bernhard Beschow Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-17-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/isapc.c | 190 ++++++++++++++++++++++++++++++++++++++++++++ hw/i386/pc_piix.c | 172 --------------------------------------- hw/i386/Kconfig | 3 - hw/i386/meson.build | 1 + 4 files changed, 191 insertions(+), 175 deletions(-) create mode 100644 hw/i386/isapc.c diff --git a/hw/i386/isapc.c b/hw/i386/isapc.c new file mode 100644 index 00000000000..300d64b7ad2 --- /dev/null +++ b/hw/i386/isapc.c @@ -0,0 +1,190 @@ +/* + * QEMU PC System Emulator + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * SPDX-License-Identifier: MIT + */ + +#include "qemu/osdep.h" + +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "hw/char/parallel-isa.h" +#include "hw/dma/i8257.h" +#include "hw/i386/pc.h" +#include "hw/ide/isa.h" +#include "hw/ide/ide-bus.h" +#include "system/kvm.h" +#include "hw/i386/kvm/clock.h" +#include "hw/xen/xen-x86.h" +#include "system/xen.h" +#include "hw/rtc/mc146818rtc.h" +#include "target/i386/cpu.h" + +static const int ide_iobase[MAX_IDE_BUS] =3D { 0x1f0, 0x170 }; +static const int ide_iobase2[MAX_IDE_BUS] =3D { 0x3f6, 0x376 }; +static const int ide_irq[MAX_IDE_BUS] =3D { 14, 15 }; + + +static void pc_init_isa(MachineState *machine) +{ + PCMachineState *pcms =3D PC_MACHINE(machine); + PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); + X86MachineState *x86ms =3D X86_MACHINE(machine); + MemoryRegion *system_memory =3D get_system_memory(); + MemoryRegion *system_io =3D get_system_io(); + ISABus *isa_bus; + uint32_t irq; + GSIState *gsi_state; + MemoryRegion *ram_memory; + MemoryRegion *rom_memory =3D system_memory; + DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; + int i; + + /* + * There is a small chance that someone unintentionally passes "-cpu m= ax" + * for the isapc machine, which will provide a much more modern 32-bit + * CPU than would be expected for an ISA-era PC. If the "max" cpu type= has + * been specified, choose the "best" 32-bit cpu possible which we cons= ider + * be the pentium3 (deliberately choosing an Intel CPU given that the + * default 486 CPU for the isapc machine is also an Intel CPU). + */ + if (!strcmp(machine->cpu_type, X86_CPU_TYPE_NAME("max"))) { + machine->cpu_type =3D X86_CPU_TYPE_NAME("pentium3"); + warn_report("-cpu max is invalid for isapc machine, using pentium3= "); + } + + /* + * Similarly if someone unintentionally passes "-cpu host" for the isa= pc + * machine then display a warning and also switch to the "best" 32-bit + * cpu possible which we consider to be the pentium3. This is because = any + * host CPU will already be modern than this, but it also ensures any + * newer CPU flags/features are filtered out for older guests. + */ + if (!strcmp(machine->cpu_type, X86_CPU_TYPE_NAME("host"))) { + machine->cpu_type =3D X86_CPU_TYPE_NAME("pentium3"); + warn_report("-cpu host is invalid for isapc machine, using pentium= 3"); + } + + if (machine->ram_size > 3.5 * GiB) { + error_report("Too much memory for this machine: %" PRId64 " MiB, " + "maximum 3584 MiB", machine->ram_size / MiB); + exit(1); + } + + /* + * There is no RAM split for the isapc machine + */ + if (xen_enabled()) { + xen_hvm_init_pc(pcms, &ram_memory); + } else { + ram_memory =3D machine->ram; + + pcms->max_ram_below_4g =3D 3.5 * GiB; + x86ms->above_4g_mem_size =3D 0; + x86ms->below_4g_mem_size =3D machine->ram_size; + } + + x86_cpus_init(x86ms, pcmc->default_cpu_version); + + if (kvm_enabled()) { + kvmclock_create(pcmc->kvmclock_create_always); + } + + /* allocate ram and load rom/bios */ + if (!xen_enabled()) { + pc_memory_init(pcms, system_memory, rom_memory, 0); + } else { + assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + + x86ms->above_4g_mem_size); + + if (machine->kernel_filename !=3D NULL) { + /* For xen HVM direct kernel boot, load linux here */ + xen_load_linux(pcms); + } + } + + gsi_state =3D pc_gsi_create(&x86ms->gsi, false); + + isa_bus =3D isa_bus_new(NULL, system_memory, system_io, + &error_abort); + isa_bus_register_input_irqs(isa_bus, x86ms->gsi); + + x86ms->rtc =3D isa_new(TYPE_MC146818_RTC); + qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); + isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); + irq =3D object_property_get_uint(OBJECT(x86ms->rtc), "irq", + &error_fatal); + isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq); + + i8257_dma_init(OBJECT(machine), isa_bus, 0); + pcms->hpet_enabled =3D false; + + if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { + pc_i8259_create(isa_bus, gsi_state->i8259_irq); + } + + if (tcg_enabled()) { + x86_register_ferr_irq(x86ms->gsi[13]); + } + + pc_vga_init(isa_bus, NULL); + + /* init basic PC hardware */ + pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, + !MACHINE_CLASS(pcmc)->no_floppy, 0x4); + + pc_nic_init(pcmc, isa_bus, NULL); + + ide_drive_get(hd, ARRAY_SIZE(hd)); + for (i =3D 0; i < MAX_IDE_BUS; i++) { + ISADevice *dev; + char busname[] =3D "ide.0"; + dev =3D isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], + ide_irq[i], + hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]= ); + /* + * The ide bus name is ide.0 for the first bus and ide.1 for the + * second one. + */ + busname[4] =3D '0' + i; + pcms->idebus[i] =3D qdev_get_child_bus(DEVICE(dev), busname); + } +} + +static void isapc_machine_options(MachineClass *m) +{ + static const char * const valid_cpu_types[] =3D { + X86_CPU_TYPE_NAME("486"), + X86_CPU_TYPE_NAME("athlon"), + X86_CPU_TYPE_NAME("kvm32"), + X86_CPU_TYPE_NAME("pentium"), + X86_CPU_TYPE_NAME("pentium2"), + X86_CPU_TYPE_NAME("pentium3"), + X86_CPU_TYPE_NAME("qemu32"), + X86_CPU_TYPE_NAME("max"), + X86_CPU_TYPE_NAME("host"), + NULL + }; + PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); + + m->desc =3D "ISA-only PC"; + m->max_cpus =3D 1; + m->option_rom_has_mr =3D true; + m->rom_file_has_mr =3D false; + pcmc->pci_enabled =3D false; + pcmc->has_acpi_build =3D false; + pcmc->smbios_defaults =3D false; + pcmc->gigabyte_align =3D false; + pcmc->smbios_legacy_mode =3D true; + pcmc->has_reserved_memory =3D false; + m->default_nic =3D "ne2k_isa"; + m->default_cpu_type =3D X86_CPU_TYPE_NAME("486"); + m->valid_cpu_types =3D valid_cpu_types; + m->no_floppy =3D !module_object_class_by_name(TYPE_ISA_FDC); + m->no_parallel =3D !module_object_class_by_name(TYPE_ISA_PARALLEL); +} + +DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa, + isapc_machine_options); diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 3ea77b2c44f..988c9edc32c 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -71,12 +71,6 @@ =20 #define XEN_IOAPIC_NUM_PIRQS 128ULL =20 -#ifdef CONFIG_IDE_ISA -static const int ide_iobase[MAX_IDE_BUS] =3D { 0x1f0, 0x170 }; -static const int ide_iobase2[MAX_IDE_BUS] =3D { 0x3f6, 0x376 }; -static const int ide_irq[MAX_IDE_BUS] =3D { 14, 15 }; -#endif - static GlobalProperty pc_piix_compat_defaults[] =3D { { TYPE_RAMFB_DEVICE, "use-legacy-x86-rom", "true" }, { TYPE_VFIO_PCI_NOHOTPLUG, "use-legacy-x86-rom", "true" }, @@ -392,134 +386,6 @@ static void pc_set_south_bridge(Object *obj, int valu= e, Error **errp) pcms->south_bridge =3D PCSouthBridgeOption_lookup.array[value]; } =20 -#ifdef CONFIG_ISAPC -static void pc_init_isa(MachineState *machine) -{ - PCMachineState *pcms =3D PC_MACHINE(machine); - PCMachineClass *pcmc =3D PC_MACHINE_GET_CLASS(pcms); - X86MachineState *x86ms =3D X86_MACHINE(machine); - MemoryRegion *system_memory =3D get_system_memory(); - MemoryRegion *system_io =3D get_system_io(); - ISABus *isa_bus; - uint32_t irq; - GSIState *gsi_state; - MemoryRegion *ram_memory; - MemoryRegion *rom_memory =3D system_memory; - DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; - int i; - - /* - * There is a small chance that someone unintentionally passes "-cpu m= ax" - * for the isapc machine, which will provide a much more modern 32-bit - * CPU than would be expected for an ISA-era PC. If the "max" cpu type= has - * been specified, choose the "best" 32-bit cpu possible which we cons= ider - * be the pentium3 (deliberately choosing an Intel CPU given that the - * default 486 CPU for the isapc machine is also an Intel CPU). - */ - if (!strcmp(machine->cpu_type, X86_CPU_TYPE_NAME("max"))) { - machine->cpu_type =3D X86_CPU_TYPE_NAME("pentium3"); - warn_report("-cpu max is invalid for isapc machine, using pentium3= "); - } - - /* - * Similarly if someone unintentionally passes "-cpu host" for the isa= pc - * machine then display a warning and also switch to the "best" 32-bit - * cpu possible which we consider to be the pentium3. This is because = any - * host CPU will already be modern than this, but it also ensures any - * newer CPU flags/features are filtered out for older guests. - */ - if (!strcmp(machine->cpu_type, X86_CPU_TYPE_NAME("host"))) { - machine->cpu_type =3D X86_CPU_TYPE_NAME("pentium3"); - warn_report("-cpu host is invalid for isapc machine, using pentium= 3"); - } - - if (machine->ram_size > 3.5 * GiB) { - error_report("Too much memory for this machine: %" PRId64 " MiB, " - "maximum 3584 MiB", machine->ram_size / MiB); - exit(1); - } - - /* - * There is no RAM split for the isapc machine - */ - if (xen_enabled()) { - xen_hvm_init_pc(pcms, &ram_memory); - } else { - ram_memory =3D machine->ram; - - pcms->max_ram_below_4g =3D 3.5 * GiB; - x86ms->above_4g_mem_size =3D 0; - x86ms->below_4g_mem_size =3D machine->ram_size; - } - - x86_cpus_init(x86ms, pcmc->default_cpu_version); - - if (kvm_enabled()) { - kvmclock_create(pcmc->kvmclock_create_always); - } - - /* allocate ram and load rom/bios */ - if (!xen_enabled()) { - pc_memory_init(pcms, system_memory, rom_memory, 0); - } else { - assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + - x86ms->above_4g_mem_size); - - if (machine->kernel_filename !=3D NULL) { - /* For xen HVM direct kernel boot, load linux here */ - xen_load_linux(pcms); - } - } - - gsi_state =3D pc_gsi_create(&x86ms->gsi, false); - - isa_bus =3D isa_bus_new(NULL, system_memory, system_io, - &error_abort); - isa_bus_register_input_irqs(isa_bus, x86ms->gsi); - - x86ms->rtc =3D isa_new(TYPE_MC146818_RTC); - qdev_prop_set_int32(DEVICE(x86ms->rtc), "base_year", 2000); - isa_realize_and_unref(x86ms->rtc, isa_bus, &error_fatal); - irq =3D object_property_get_uint(OBJECT(x86ms->rtc), "irq", - &error_fatal); - isa_connect_gpio_out(ISA_DEVICE(x86ms->rtc), 0, irq); - - i8257_dma_init(OBJECT(machine), isa_bus, 0); - pcms->hpet_enabled =3D false; - - if (x86ms->pic =3D=3D ON_OFF_AUTO_ON || x86ms->pic =3D=3D ON_OFF_AUTO_= AUTO) { - pc_i8259_create(isa_bus, gsi_state->i8259_irq); - } - - if (tcg_enabled()) { - x86_register_ferr_irq(x86ms->gsi[13]); - } - - pc_vga_init(isa_bus, NULL); - - /* init basic PC hardware */ - pc_basic_device_init(pcms, isa_bus, x86ms->gsi, x86ms->rtc, - !MACHINE_CLASS(pcmc)->no_floppy, 0x4); - - pc_nic_init(pcmc, isa_bus, NULL); - - ide_drive_get(hd, ARRAY_SIZE(hd)); - for (i =3D 0; i < MAX_IDE_BUS; i++) { - ISADevice *dev; - char busname[] =3D "ide.0"; - dev =3D isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], - ide_irq[i], - hd[MAX_IDE_DEVS * i], hd[MAX_IDE_DEVS * i + 1]= ); - /* - * The ide bus name is ide.0 for the first bus and ide.1 for the - * second one. - */ - busname[4] =3D '0' + i; - pcms->idebus[i] =3D qdev_get_child_bus(DEVICE(dev), busname); - } -} -#endif - #ifdef CONFIG_XEN static void pc_xen_hvm_init(MachineState *machine) { @@ -887,44 +753,6 @@ static void pc_i440fx_machine_2_6_options(MachineClass= *m) =20 DEFINE_I440FX_MACHINE(2, 6); =20 -#ifdef CONFIG_ISAPC -static void isapc_machine_options(MachineClass *m) -{ - static const char * const valid_cpu_types[] =3D { - X86_CPU_TYPE_NAME("486"), - X86_CPU_TYPE_NAME("athlon"), - X86_CPU_TYPE_NAME("kvm32"), - X86_CPU_TYPE_NAME("pentium"), - X86_CPU_TYPE_NAME("pentium2"), - X86_CPU_TYPE_NAME("pentium3"), - X86_CPU_TYPE_NAME("qemu32"), - X86_CPU_TYPE_NAME("max"), - X86_CPU_TYPE_NAME("host"), - NULL - }; - PCMachineClass *pcmc =3D PC_MACHINE_CLASS(m); - - m->desc =3D "ISA-only PC"; - m->max_cpus =3D 1; - m->option_rom_has_mr =3D true; - m->rom_file_has_mr =3D false; - pcmc->pci_enabled =3D false; - pcmc->has_acpi_build =3D false; - pcmc->smbios_defaults =3D false; - pcmc->gigabyte_align =3D false; - pcmc->smbios_legacy_mode =3D true; - pcmc->has_reserved_memory =3D false; - m->default_nic =3D "ne2k_isa"; - m->default_cpu_type =3D X86_CPU_TYPE_NAME("486"); - m->valid_cpu_types =3D valid_cpu_types; - m->no_floppy =3D !module_object_class_by_name(TYPE_ISA_FDC); - m->no_parallel =3D !module_object_class_by_name(TYPE_ISA_PARALLEL); -} - -DEFINE_PC_MACHINE(isapc, "isapc", pc_init_isa, - isapc_machine_options); -#endif - #ifdef CONFIG_XEN static void xenfv_machine_4_2_options(MachineClass *m) { diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 3a0e2b8ebbb..6a0ab54bea4 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -96,9 +96,6 @@ config ISAPC select ISA_BUS select PC select IDE_ISA - # FIXME: it is in the same file as i440fx, and does not compile - # if separated - depends on I440FX =20 config Q35 bool diff --git a/hw/i386/meson.build b/hw/i386/meson.build index 7896f348cff..436b3ce52d6 100644 --- a/hw/i386/meson.build +++ b/hw/i386/meson.build @@ -14,6 +14,7 @@ i386_ss.add(when: 'CONFIG_X86_IOMMU', if_true: files('x86= -iommu.c'), i386_ss.add(when: 'CONFIG_AMD_IOMMU', if_true: files('amd_iommu.c'), if_false: files('amd_iommu-stub.c')) i386_ss.add(when: 'CONFIG_I440FX', if_true: files('pc_piix.c')) +i386_ss.add(when: 'CONFIG_ISAPC', if_true: files('isapc.c')) i386_ss.add(when: 'CONFIG_MICROVM', if_true: files('x86-common.c', 'microv= m.c', 'acpi-microvm.c', 'microvm-dt.c')) i386_ss.add(when: 'CONFIG_NITRO_ENCLAVE', if_true: files('nitro_enclave.c'= )) i386_ss.add(when: 'CONFIG_Q35', if_true: files('pc_q35.c')) --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 06:00:27 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHC39AnFlnFJOKwO17DxgdkrjB0FOZ/9F09oMhmKY3ZqiVwR6hWBRgd8SWEDOQ0wTR/2vPcrw== X-Received: by 2002:a5d:5d0a:0:b0:3b8:f358:e80d with SMTP id ffacd0b85a97d-3c5db8ab097mr23132322f8f.5.1756472426936; Fri, 29 Aug 2025 06:00:26 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 17/28] hw/i386/pc_piix.c: remove unused headers after isapc machine split Date: Fri, 29 Aug 2025 14:59:24 +0200 Message-ID: <20250829125935.1526984-18-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568050412116600 From: Mark Cave-Ayland The headers for isapc-only devices can be removed from pc_piix.c since they= are no longer used by the i440fx-pc machine. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-18-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 988c9edc32c..627de09c704 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -27,19 +27,16 @@ =20 #include "qemu/units.h" #include "hw/char/parallel-isa.h" -#include "hw/dma/i8257.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" #include "hw/i386/apic.h" #include "hw/pci-host/i440fx.h" -#include "hw/rtc/mc146818rtc.h" #include "hw/southbridge/piix.h" #include "hw/display/ramfb.h" #include "hw/pci/pci.h" #include "hw/pci/pci_ids.h" #include "hw/usb.h" #include "net/net.h" -#include "hw/ide/isa.h" #include "hw/ide/pci.h" #include "hw/irq.h" #include "system/kvm.h" --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 06:00:32 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFrbXIp/z6ozUS8UyytZ6B0s4SBc/e5GYxtgTLoi9+RrNq9uEW2dfcycZUO4I4Dr9ozcu2Ajw== X-Received: by 2002:a05:600d:19:b0:459:d3e2:d743 with SMTP id 5b1f17b1804b1-45b6870de14mr114964295e9.8.1756472431734; Fri, 29 Aug 2025 06:00:31 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 18/28] hw/i386/pc_piix.c: replace rom_memory with pci_memory Date: Fri, 29 Aug 2025 14:59:25 +0200 Message-ID: <20250829125935.1526984-19-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568904905116600 From: Mark Cave-Ayland Now that we can guarantee the i440fx-pc machine will always have a PCI bus,= any instances of rom_memory can be replaced by pci_memory and rom_memory removed completely. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-19-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/pc_piix.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 627de09c704..7e78b6daa6d 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -113,7 +113,6 @@ static void pc_init1(MachineState *machine, const char = *pci_type) GSIState *gsi_state; MemoryRegion *ram_memory; MemoryRegion *pci_memory =3D NULL; - MemoryRegion *rom_memory =3D system_memory; ram_addr_t lowmem; uint64_t hole64_size =3D 0; PCIDevice *pci_dev; @@ -193,7 +192,6 @@ static void pc_init1(MachineState *machine, const char = *pci_type) =20 pci_memory =3D g_new(MemoryRegion, 1); memory_region_init(pci_memory, NULL, "pci", UINT64_MAX); - rom_memory =3D pci_memory; =20 phb =3D OBJECT(qdev_new(TYPE_I440FX_PCI_HOST_BRIDGE)); object_property_add_child(OBJECT(machine), "i440fx", phb); @@ -224,7 +222,7 @@ static void pc_init1(MachineState *machine, const char = *pci_type) =20 /* allocate ram and load rom/bios */ if (!xen_enabled()) { - pc_memory_init(pcms, system_memory, rom_memory, hole64_size); + pc_memory_init(pcms, system_memory, pci_memory, hole64_size); } else { assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756568781; cv=none; d=zohomail.com; s=zohoarc; b=Mwy78r3F4o7/I8XvtS7PNE5OBVC2pMWDa92PoSJBl8l/0j4fENYpvIYbKMy5koNfwgLg8oWEmeNRfT7Ea7r+3YCQPxPXhCHHHXhyXDGq5MFTwRRxejln3qsDczZDvz7xy+uTS6FnZ/JqdyYbMmWmZ4HVm8LE77lEi5JXMcRrJAY= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 06:00:36 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFa8DZQ/d/Q29qaaQkZ/GREddHZy0PukUvlnzP0jmxuASNIK06ki3FUASLANKYhQDdSg79ttg== X-Received: by 2002:a05:600c:1c07:b0:45b:7ffa:1bf8 with SMTP id 5b1f17b1804b1-45b7ffa1d60mr19703255e9.23.1756472436042; Fri, 29 Aug 2025 06:00:36 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Mark Cave-Ayland , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Xiaoyao Li Subject: [PULL 19/28] hw/i386/isapc.c: replace rom_memory with system_memory Date: Fri, 29 Aug 2025 14:59:26 +0200 Message-ID: <20250829125935.1526984-20-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568783340116600 From: Mark Cave-Ayland Now that we can guarantee the isapc machine will never have a PCI bus, any instances of rom_memory can be replaced by system_memory and rom_memory removed completely. Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Xiaoyao Li Link: https://lore.kernel.org/r/20250828111057.468712-20-mark.caveayland@nu= tanix.com Signed-off-by: Paolo Bonzini --- hw/i386/isapc.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/hw/i386/isapc.c b/hw/i386/isapc.c index 300d64b7ad2..44f4a446724 100644 --- a/hw/i386/isapc.c +++ b/hw/i386/isapc.c @@ -38,7 +38,6 @@ static void pc_init_isa(MachineState *machine) uint32_t irq; GSIState *gsi_state; MemoryRegion *ram_memory; - MemoryRegion *rom_memory =3D system_memory; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; int i; =20 @@ -94,7 +93,7 @@ static void pc_init_isa(MachineState *machine) =20 /* allocate ram and load rom/bios */ if (!xen_enabled()) { - pc_memory_init(pcms, system_memory, rom_memory, 0); + pc_memory_init(pcms, system_memory, system_memory, 0); } else { assert(machine->ram_size =3D=3D x86ms->below_4g_mem_size + x86ms->above_4g_mem_size); --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Fri, 29 Aug 2025 06:00:42 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFA+IXhHNAq5Mvz62ij47oXOz5UcksSZg/GlMImUrn9SRZ9TNQJBj6tGCymnJHmyWipA7b+QA== X-Received: by 2002:a05:6000:1787:b0:3b7:94ad:ef50 with SMTP id ffacd0b85a97d-3cbb15ca78amr11348831f8f.2.1756472442052; Fri, 29 Aug 2025 06:00:42 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Subject: [PULL 20/28] user-exec: ensure interrupt_request is not used Date: Fri, 29 Aug 2025 14:59:27 +0200 Message-ID: <20250829125935.1526984-21-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567916747116600 Content-Type: text/plain; charset="utf-8" cpu_interrupt() is not called anymore except by ARM but even there it is dead code; disentangling the various cpregs accessors from user-mode emulation is a work in progress. Signed-off-by: Paolo Bonzini --- include/hw/core/cpu.h | 1 + accel/tcg/cpu-exec.c | 6 ++++-- accel/tcg/user-exec.c | 4 +--- 3 files changed, 6 insertions(+), 5 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 5eaf41a566f..f73b4357c7b 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -423,6 +423,7 @@ struct qemu_work_item; * @created: Indicates whether the CPU thread has been successfully create= d. * @halt_cond: condition variable sleeping threads can wait on. * @interrupt_request: Indicates a pending interrupt request. + * Only used by system emulation. * @halted: Nonzero if the CPU is in suspended state. * @stop: Indicates a pending stop request. * @stopped: Indicates the CPU has been artificially stopped. diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 713bdb20564..b44dd1e8205 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -778,6 +778,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, */ qatomic_set_mb(&cpu->neg.icount_decr.u16.high, 0); =20 +#ifdef CONFIG_USER_ONLY + g_assert(!qatomic_read(&cpu->interrupt_request)); +#else if (unlikely(qatomic_read(&cpu->interrupt_request))) { int interrupt_request; bql_lock(); @@ -792,7 +795,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, bql_unlock(); return true; } -#if !defined(CONFIG_USER_ONLY) if (replay_mode =3D=3D REPLAY_MODE_PLAY && !replay_has_interrupt()= ) { /* Do nothing */ } else if (interrupt_request & CPU_INTERRUPT_HALT) { @@ -840,7 +842,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * reload the 'interrupt_request' value */ interrupt_request =3D cpu->interrupt_request; } -#endif /* !CONFIG_USER_ONLY */ if (interrupt_request & CPU_INTERRUPT_EXITTB) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as @@ -851,6 +852,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, /* If we exit via cpu_loop_exit/longjmp it is reset in cpu_exec */ bql_unlock(); } +#endif /* !CONFIG_USER_ONLY */ =20 /* Finally, check if we need to exit to the main loop. */ if (unlikely(qatomic_read(&cpu->exit_request)) || icount_exit_request(= cpu)) { diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f25d80e2dc2..748bfab04a7 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -48,9 +48,7 @@ __thread uintptr_t helper_retaddr; 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Fri, 29 Aug 2025 06:00:46 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGqkMrqp/M7ykiWTyHyiK2DQWuABLTm4dTNWHIO5LdIntDuArYv4nTXQOnuGaDDb9UEWb+vHA== X-Received: by 2002:a05:6000:1a8a:b0:3ce:db36:607f with SMTP id ffacd0b85a97d-3cedb37566amr2766258f8f.37.1756472445360; Fri, 29 Aug 2025 06:00:45 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Igor Mammedov , Peter Xu , "Jason J. Herne" Subject: [PULL 21/28] add cpu_test_interrupt()/cpu_set_interrupt() helpers and use them tree wide Date: Fri, 29 Aug 2025 14:59:28 +0200 Message-ID: <20250829125935.1526984-22-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756567242852116600 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov The helpers form load-acquire/store-release pair and ensure that appropriate barriers are in place in case checks happen outside of BQL. Use them to replace open-coded checkers/setters across the code, to make sure that barriers are not missed. Helpers also make code a bit more readable. Signed-off-by: Igor Mammedov Reviewed-by: Peter Xu Reviewed-by: Jason J. Herne Link: https://lore.kernel.org/r/20250821155603.2422553-1-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- include/hw/core/cpu.h | 22 +++++++++++++++++++ accel/tcg/cpu-exec.c | 12 +++++----- accel/tcg/tcg-accel-ops.c | 2 +- hw/intc/s390_flic.c | 2 +- hw/openrisc/cputimer.c | 2 +- system/cpus.c | 9 +++++++- target/alpha/cpu.c | 8 +++---- target/arm/cpu.c | 20 ++++++++--------- target/arm/helper.c | 18 +++++++-------- target/arm/hvf/hvf.c | 6 ++--- target/avr/cpu.c | 2 +- target/hppa/cpu.c | 2 +- target/i386/hvf/hvf.c | 4 ++-- target/i386/hvf/x86hvf.c | 21 +++++++++--------- target/i386/kvm/kvm.c | 34 ++++++++++++++--------------- target/i386/nvmm/nvmm-all.c | 24 ++++++++++---------- target/i386/tcg/system/seg_helper.c | 2 +- target/i386/tcg/system/svm_helper.c | 2 +- target/i386/whpx/whpx-all.c | 34 ++++++++++++++--------------- target/loongarch/cpu.c | 2 +- target/m68k/cpu.c | 2 +- target/microblaze/cpu.c | 2 +- target/mips/cpu.c | 6 ++--- target/mips/kvm.c | 2 +- target/openrisc/cpu.c | 3 +-- target/ppc/cpu_init.c | 2 +- target/ppc/kvm.c | 2 +- target/rx/cpu.c | 3 +-- target/rx/helper.c | 2 +- target/s390x/cpu-system.c | 2 +- target/sh4/cpu.c | 2 +- target/sh4/helper.c | 2 +- target/sparc/cpu.c | 2 +- target/sparc/int64_helper.c | 4 ++-- 34 files changed, 145 insertions(+), 119 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index f73b4357c7b..b01a0cffd64 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -943,6 +943,28 @@ CPUState *cpu_by_arch_id(int64_t id); =20 void cpu_interrupt(CPUState *cpu, int mask); =20 +/** + * cpu_test_interrupt: + * @cpu: The CPU to check interrupt(s) on. + * @mask: The interrupts to check. + * + * Checks if any of interrupts in @mask are pending on @cpu. + */ +static inline bool cpu_test_interrupt(CPUState *cpu, int mask) +{ + return qatomic_load_acquire(&cpu->interrupt_request) & mask; +} + +/** + * cpu_set_interrupt: + * @cpu: The CPU to set pending interrupt(s) on. + * @mask: The interrupts to set. + * + * Sets interrupts in @mask as pending on @cpu. Unlike @cpu_interrupt, + * this does not kick the vCPU. + */ +void cpu_set_interrupt(CPUState *cpu, int mask); + /** * cpu_set_pc: * @cpu: The CPU to set the program counter for. diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index b44dd1e8205..96c124aa720 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -779,9 +779,9 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, qatomic_set_mb(&cpu->neg.icount_decr.u16.high, 0); =20 #ifdef CONFIG_USER_ONLY - g_assert(!qatomic_read(&cpu->interrupt_request)); + assert(!cpu_test_interrupt(cpu, ~0)); #else - if (unlikely(qatomic_read(&cpu->interrupt_request))) { + if (unlikely(cpu_test_interrupt(cpu, ~0))) { int interrupt_request; bql_lock(); interrupt_request =3D cpu->interrupt_request; @@ -789,7 +789,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, /* Mask out external interrupts for this step. */ interrupt_request &=3D ~CPU_INTERRUPT_SSTEP_MASK; } - if (interrupt_request & CPU_INTERRUPT_DEBUG) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_DEBUG)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_DEBUG; cpu->exception_index =3D EXCP_DEBUG; bql_unlock(); @@ -797,7 +797,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } if (replay_mode =3D=3D REPLAY_MODE_PLAY && !replay_has_interrupt()= ) { /* Do nothing */ - } else if (interrupt_request & CPU_INTERRUPT_HALT) { + } else if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HALT)) { replay_interrupt(); cpu->interrupt_request &=3D ~CPU_INTERRUPT_HALT; cpu->halted =3D 1; @@ -807,7 +807,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, } else { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; =20 - if (interrupt_request & CPU_INTERRUPT_RESET) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_RESET)) { replay_interrupt(); tcg_ops->cpu_exec_reset(cpu); bql_unlock(); @@ -842,7 +842,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, * reload the 'interrupt_request' value */ interrupt_request =3D cpu->interrupt_request; } - if (interrupt_request & CPU_INTERRUPT_EXITTB) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_EXITTB)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as the program flow was changed */ diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 3b0d7d298e6..9c37266c1e0 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -97,7 +97,7 @@ static void tcg_cpu_reset_hold(CPUState *cpu) /* mask must never be zero, except for A20 change call */ void tcg_handle_interrupt(CPUState *cpu, int mask) { - cpu->interrupt_request |=3D mask; + cpu_set_interrupt(cpu, mask); =20 /* * If called from iothread context, wake the target cpu in diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c index 8f4c9fd52e8..1eed5125d17 100644 --- a/hw/intc/s390_flic.c +++ b/hw/intc/s390_flic.c @@ -190,7 +190,7 @@ static void qemu_s390_flic_notify(uint32_t type) CPU_FOREACH(cs) { S390CPU *cpu =3D S390_CPU(cs); =20 - cs->interrupt_request |=3D CPU_INTERRUPT_HARD; + cpu_set_interrupt(cs, CPU_INTERRUPT_HARD); =20 /* ignore CPUs that are not sleeping */ if (s390_cpu_get_state(cpu) !=3D S390_CPU_STATE_OPERATING && diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c index 6331997d56b..51da226fcde 100644 --- a/hw/openrisc/cputimer.c +++ b/hw/openrisc/cputimer.c @@ -105,7 +105,7 @@ static void openrisc_timer_cb(void *opaque) CPUState *cs =3D CPU(cpu); =20 cpu->env.ttmr |=3D TTMR_IP; - cs->interrupt_request |=3D CPU_INTERRUPT_TIMER; + cpu_set_interrupt(cs, CPU_INTERRUPT_TIMER); } =20 switch (cpu->env.ttmr & TTMR_M) { diff --git a/system/cpus.c b/system/cpus.c index 256723558d0..437848b5eb4 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -254,9 +254,16 @@ int64_t cpus_get_elapsed_ticks(void) return cpu_get_ticks(); } =20 +void cpu_set_interrupt(CPUState *cpu, int mask) +{ + /* Pairs with cpu_test_interrupt(). */ + qatomic_store_release(&cpu->interrupt_request, + cpu->interrupt_request | mask); +} + void generic_handle_interrupt(CPUState *cpu, int mask) { - cpu->interrupt_request |=3D mask; + cpu_set_interrupt(cpu, mask); =20 if (!qemu_cpu_is_self(cpu)) { qemu_cpu_kick(cpu); diff --git a/target/alpha/cpu.c b/target/alpha/cpu.c index bf1787a69dd..932cddac055 100644 --- a/target/alpha/cpu.c +++ b/target/alpha/cpu.c @@ -86,10 +86,10 @@ static bool alpha_cpu_has_work(CPUState *cs) assume that if a CPU really wants to stay asleep, it will mask interrupts at the chipset level, which will prevent these bits from being set in the first place. */ - return cs->interrupt_request & (CPU_INTERRUPT_HARD - | CPU_INTERRUPT_TIMER - | CPU_INTERRUPT_SMP - | CPU_INTERRUPT_MCHK); + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD + | CPU_INTERRUPT_TIMER + | CPU_INTERRUPT_SMP + | CPU_INTERRUPT_MCHK); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e2b2337399c..a29c3facbfd 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -142,11 +142,11 @@ static bool arm_cpu_has_work(CPUState *cs) ARMCPU *cpu =3D ARM_CPU(cs); =20 return (cpu->power_state !=3D PSCI_OFF) - && cs->interrupt_request & - (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_VFNMI - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR - | CPU_INTERRUPT_EXITTB); + && cpu_test_interrupt(cs, + CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD + | CPU_INTERRUPT_NMI | CPU_INTERRUPT_VINMI | CPU_INTERRUPT_V= FNMI + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_V= SERR + | CPU_INTERRUPT_EXITTB); } #endif /* !CONFIG_USER_ONLY */ =20 @@ -958,7 +958,7 @@ void arm_cpu_update_virq(ARMCPU *cpu) !(arm_hcrx_el2_eff(env) & HCRX_VINMI)) || (env->irq_line_state & CPU_INTERRUPT_VIRQ); =20 - if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VIRQ) !=3D = 0)) { + if (new_state !=3D cpu_test_interrupt(cs, CPU_INTERRUPT_VIRQ)) { if (new_state) { cpu_interrupt(cs, CPU_INTERRUPT_VIRQ); } else { @@ -980,7 +980,7 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) !(arm_hcrx_el2_eff(env) & HCRX_VFNMI)) || (env->irq_line_state & CPU_INTERRUPT_VFIQ); =20 - if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VFIQ) !=3D = 0)) { + if (new_state !=3D cpu_test_interrupt(cs, CPU_INTERRUPT_VFIQ)) { if (new_state) { cpu_interrupt(cs, CPU_INTERRUPT_VFIQ); } else { @@ -1002,7 +1002,7 @@ void arm_cpu_update_vinmi(ARMCPU *cpu) (arm_hcrx_el2_eff(env) & HCRX_VINMI)) || (env->irq_line_state & CPU_INTERRUPT_VINMI); =20 - if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VINMI) !=3D= 0)) { + if (new_state !=3D cpu_test_interrupt(cs, CPU_INTERRUPT_VINMI)) { if (new_state) { cpu_interrupt(cs, CPU_INTERRUPT_VINMI); } else { @@ -1022,7 +1022,7 @@ void arm_cpu_update_vfnmi(ARMCPU *cpu) bool new_state =3D (arm_hcr_el2_eff(env) & HCR_VF) && (arm_hcrx_el2_eff(env) & HCRX_VFNMI); =20 - if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VFNMI) !=3D= 0)) { + if (new_state !=3D cpu_test_interrupt(cs, CPU_INTERRUPT_VFNMI)) { if (new_state) { cpu_interrupt(cs, CPU_INTERRUPT_VFNMI); } else { @@ -1041,7 +1041,7 @@ void arm_cpu_update_vserr(ARMCPU *cpu) =20 bool new_state =3D env->cp15.hcr_el2 & HCR_VSE; =20 - if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VSERR) !=3D= 0)) { + if (new_state !=3D cpu_test_interrupt(cs, CPU_INTERRUPT_VSERR)) { if (new_state) { cpu_interrupt(cs, CPU_INTERRUPT_VSERR); } else { diff --git a/target/arm/helper.c b/target/arm/helper.c index 0c1299ff841..4cd36e950aa 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -833,40 +833,40 @@ static uint64_t isr_read(CPUARMState *env, const ARMC= PRegInfo *ri) uint64_t ret =3D 0; =20 if (hcr_el2 & HCR_IMO) { - if (cs->interrupt_request & CPU_INTERRUPT_VIRQ) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_VIRQ)) { ret |=3D CPSR_I; } - if (cs->interrupt_request & CPU_INTERRUPT_VINMI) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_VINMI)) { ret |=3D ISR_IS; ret |=3D CPSR_I; } } else { - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { ret |=3D CPSR_I; } =20 - if (cs->interrupt_request & CPU_INTERRUPT_NMI) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_NMI)) { ret |=3D ISR_IS; ret |=3D CPSR_I; } } =20 if (hcr_el2 & HCR_FMO) { - if (cs->interrupt_request & CPU_INTERRUPT_VFIQ) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_VFIQ)) { ret |=3D CPSR_F; } - if (cs->interrupt_request & CPU_INTERRUPT_VFNMI) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_VFNMI)) { ret |=3D ISR_FS; ret |=3D CPSR_F; } } else { - if (cs->interrupt_request & CPU_INTERRUPT_FIQ) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_FIQ)) { ret |=3D CPSR_F; } } =20 if (hcr_el2 & HCR_AMO) { - if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_VSERR)) { ret |=3D CPSR_A; } } @@ -9147,7 +9147,7 @@ void arm_cpu_do_interrupt(CPUState *cs) arm_call_el_change_hook(cpu); =20 if (!kvm_enabled()) { - cs->interrupt_request |=3D CPU_INTERRUPT_EXITTB; + cpu_set_interrupt(cs, CPU_INTERRUPT_EXITTB); } } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 47b0cd3a351..b77db99079e 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1782,13 +1782,13 @@ static int hvf_sysreg_write(CPUState *cpu, uint32_t= reg, uint64_t val) =20 static int hvf_inject_interrupts(CPUState *cpu) { - if (cpu->interrupt_request & CPU_INTERRUPT_FIQ) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_FIQ)) { trace_hvf_inject_fiq(); hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_FI= Q, true); } =20 - if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { trace_hvf_inject_irq(); hv_vcpu_set_pending_interrupt(cpu->accel->fd, HV_INTERRUPT_TYPE_IR= Q, true); @@ -1840,7 +1840,7 @@ static void hvf_wfi(CPUState *cpu) uint64_t nanos; uint32_t cntfrq; =20 - if (cpu->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ))= { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIQ)) { /* Interrupt pending, no need to wait */ return; } diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 6995de6a12b..a6df71d0205 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -45,7 +45,7 @@ static vaddr avr_cpu_get_pc(CPUState *cs) =20 static bool avr_cpu_has_work(CPUState *cs) { - return (cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_RE= SET)) + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_RESET) && cpu_interrupts_enabled(cpu_env(cs)); } =20 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index 24777727e62..0ca79ee5e23 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -135,7 +135,7 @@ static void hppa_restore_state_to_opc(CPUState *cs, #ifndef CONFIG_USER_ONLY static bool hppa_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 818b50419f4..8445cadecec 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -773,9 +773,9 @@ int hvf_vcpu_exec(CPUState *cpu) switch (exit_reason) { case EXIT_REASON_HLT: { macvm_set_rip(cpu, rip + ins_len); - if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + if (!(cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) - && !(cpu->interrupt_request & CPU_INTERRUPT_NMI) && + && !cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI) && !(idtvec_info & VMCS_IDT_VEC_VALID)) { cpu->halted =3D 1; ret =3D EXCP_HLT; diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index 17fce1d3cdd..9e05e0e5765 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -395,7 +395,7 @@ bool hvf_inject_interrupts(CPUState *cs) }; } =20 - if (cs->interrupt_request & CPU_INTERRUPT_NMI) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_NMI)) { if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; @@ -406,7 +406,7 @@ bool hvf_inject_interrupts(CPUState *cs) } =20 if (!(env->hflags & HF_INHIBIT_IRQ_MASK) && - (cs->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) { int line =3D cpu_get_pic_interrupt(env); cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; @@ -415,11 +415,10 @@ bool hvf_inject_interrupts(CPUState *cs) VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); } } - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { vmx_set_int_window_exiting(cs); } - return (cs->interrupt_request - & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)); + return cpu_test_interrupt(cs, CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR); } =20 int hvf_process_events(CPUState *cs) @@ -432,25 +431,25 @@ int hvf_process_events(CPUState *cs) env->eflags =3D rreg(cs->accel->fd, HV_X86_RFLAGS); } =20 - if (cs->interrupt_request & CPU_INTERRUPT_INIT) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_INIT)) { cpu_synchronize_state(cs); do_cpu_init(cpu); } =20 - if (cs->interrupt_request & CPU_INTERRUPT_POLL) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_POLL)) { cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(cpu->apic_state); } - if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || - (cs->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu_test_interrupt(cs, CPU_INTERRUPT_NMI)) { cs->halted =3D 0; } - if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_SIPI)) { cpu_synchronize_state(cs); do_cpu_sipi(cpu); } - if (cs->interrupt_request & CPU_INTERRUPT_TPR) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_TPR)) { cs->interrupt_request &=3D ~CPU_INTERRUPT_TPR; cpu_synchronize_state(cs); apic_handle_tpr_access_report(cpu->apic_state, env->eip, diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 369626f8c8d..a7b5c8f81bc 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5453,8 +5453,8 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) int ret; =20 /* Inject NMI */ - if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { - if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { bql_lock(); cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; bql_unlock(); @@ -5465,7 +5465,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) strerror(-ret)); } } - if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SMI)) { bql_lock(); cpu->interrupt_request &=3D ~CPU_INTERRUPT_SMI; bql_unlock(); @@ -5486,12 +5486,12 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run= *run) * or (for userspace APIC, but it is cheap to combine the checks here) * pending TPR access reports. */ - if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR))= { - if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { cpu->exit_request =3D 1; } - if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_TPR)) { cpu->exit_request =3D 1; } } @@ -5499,7 +5499,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) if (!kvm_pic_in_kernel()) { /* Try to inject an interrupt if the guest can accept it */ if (run->ready_for_interrupt_injection && - (cpu->interrupt_request & CPU_INTERRUPT_HARD) && + cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) { int irq; =20 @@ -5523,7 +5523,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) * interrupt, request an interrupt window exit. This will * cause a return to userspace as soon as the guest is ready to * receive interrupts. */ - if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { run->request_interrupt_window =3D 1; } else { run->request_interrupt_window =3D 0; @@ -5595,7 +5595,7 @@ int kvm_arch_process_async_events(CPUState *cs) X86CPU *cpu =3D X86_CPU(cs); CPUX86State *env =3D &cpu->env; =20 - if (cs->interrupt_request & CPU_INTERRUPT_MCE) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_MCE)) { /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ assert(env->mcg_cap); =20 @@ -5618,7 +5618,7 @@ int kvm_arch_process_async_events(CPUState *cs) } } =20 - if ((cs->interrupt_request & CPU_INTERRUPT_INIT) && + if (cpu_test_interrupt(cs, CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { kvm_cpu_synchronize_state(cs); do_cpu_init(cpu); @@ -5628,20 +5628,20 @@ int kvm_arch_process_async_events(CPUState *cs) return 0; } =20 - if (cs->interrupt_request & CPU_INTERRUPT_POLL) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_POLL)) { cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(cpu->apic_state); } - if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if ((cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || - (cs->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu_test_interrupt(cs, CPU_INTERRUPT_NMI)) { cs->halted =3D 0; } - if (cs->interrupt_request & CPU_INTERRUPT_SIPI) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_SIPI)) { kvm_cpu_synchronize_state(cs); do_cpu_sipi(cpu); } - if (cs->interrupt_request & CPU_INTERRUPT_TPR) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_TPR)) { cs->interrupt_request &=3D ~CPU_INTERRUPT_TPR; kvm_cpu_synchronize_state(cs); apic_handle_tpr_access_report(cpu->apic_state, env->eip, @@ -5656,9 +5656,9 @@ static int kvm_handle_halt(X86CPU *cpu) CPUState *cs =3D CPU(cpu); CPUX86State *env =3D &cpu->env; =20 - if (!((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if (!(cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) && - !(cs->interrupt_request & CPU_INTERRUPT_NMI)) { + !cpu_test_interrupt(cs, CPU_INTERRUPT_NMI)) { cs->halted =3D 1; return EXCP_HLT; } diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 92e3b8b2f45..c1ac74c4f04 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -413,11 +413,11 @@ nvmm_vcpu_pre_run(CPUState *cpu) * Force the VCPU out of its inner loop to process any INIT requests * or commit pending TPR access. */ - if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR))= { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { cpu->exit_request =3D 1; } =20 - if (!has_event && (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + if (!has_event && cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { if (nvmm_can_take_nmi(cpu)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; event->type =3D NVMM_VCPU_EVENT_INTR; @@ -426,7 +426,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) } } =20 - if (!has_event && (cpu->interrupt_request & CPU_INTERRUPT_HARD)) { + if (!has_event && cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { if (nvmm_can_take_int(cpu)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; event->type =3D NVMM_VCPU_EVENT_INTR; @@ -436,7 +436,7 @@ nvmm_vcpu_pre_run(CPUState *cpu) } =20 /* Don't want SMIs. */ - if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SMI)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_SMI; } =20 @@ -651,9 +651,9 @@ nvmm_handle_halted(struct nvmm_machine *mach, CPUState = *cpu, =20 bql_lock(); =20 - if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + if (!(cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) && (cpu_env(cpu)->eflags & IF_MASK)) && - !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + !cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { cpu->exception_index =3D EXCP_HLT; cpu->halted =3D true; ret =3D 1; @@ -691,25 +691,25 @@ nvmm_vcpu_loop(CPUState *cpu) * Some asynchronous events must be handled outside of the inner * VCPU loop. They are handled here. */ - if (cpu->interrupt_request & CPU_INTERRUPT_INIT) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT)) { nvmm_cpu_synchronize_state(cpu); do_cpu_init(x86_cpu); /* set int/nmi windows back to the reset state */ } - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_POLL)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(x86_cpu->apic_state); } - if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + if ((cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || - (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { cpu->halted =3D false; } - if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) { nvmm_cpu_synchronize_state(cpu); do_cpu_sipi(x86_cpu); } - if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_TPR)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_TPR; nvmm_cpu_synchronize_state(cpu); apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip, diff --git a/target/i386/tcg/system/seg_helper.c b/target/i386/tcg/system/s= eg_helper.c index d4ea890c124..794a23ddfc4 100644 --- a/target/i386/tcg/system/seg_helper.c +++ b/target/i386/tcg/system/seg_helper.c @@ -133,7 +133,7 @@ bool x86_cpu_exec_halt(CPUState *cpu) X86CPU *x86_cpu =3D X86_CPU(cpu); CPUX86State *env =3D &x86_cpu->env; =20 - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_POLL)) { bql_lock(); apic_poll_irq(x86_cpu->apic_state); cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); diff --git a/target/i386/tcg/system/svm_helper.c b/target/i386/tcg/system/s= vm_helper.c index dea039b87a6..3569196bdda 100644 --- a/target/i386/tcg/system/svm_helper.c +++ b/target/i386/tcg/system/svm_helper.c @@ -403,7 +403,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next= _eip_addend) env->hflags2 |=3D HF2_GIF_MASK; =20 if (ctl_has_irq(env)) { - cs->interrupt_request |=3D CPU_INTERRUPT_VIRQ; + cpu_set_interrupt(cs, CPU_INTERRUPT_VIRQ); } =20 if (virtual_gif_set(env)) { diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index b72dcff3c8d..878cdd1668c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -1436,9 +1436,9 @@ static int whpx_handle_halt(CPUState *cpu) int ret =3D 0; =20 bql_lock(); - if (!((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + if (!(cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) && (cpu_env(cpu)->eflags & IF_MASK)) && - !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + !cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { cpu->exception_index =3D EXCP_HLT; cpu->halted =3D true; ret =3D 1; @@ -1469,15 +1469,15 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 /* Inject NMI */ if (!vcpu->interruption_pending && - cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { - if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { + cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; vcpu->interruptable =3D false; new_int.InterruptionType =3D WHvX64PendingNmi; new_int.InterruptionPending =3D 1; new_int.InterruptionVector =3D 2; } - if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SMI)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_SMI; } } @@ -1486,12 +1486,12 @@ static void whpx_vcpu_pre_run(CPUState *cpu) * Force the VCPU out of its inner loop to process any INIT requests or * commit pending TPR access. */ - if (cpu->interrupt_request & (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR))= { - if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { cpu->exit_request =3D 1; } - if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_TPR)) { cpu->exit_request =3D 1; } } @@ -1501,7 +1501,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) if (!vcpu->interruption_pending && vcpu->interruptable && (env->eflags & IF_MASK)) { assert(!new_int.InterruptionPending); - if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; irq =3D cpu_get_pic_interrupt(env); if (irq >=3D 0) { @@ -1519,7 +1519,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) reg_count +=3D 1; } } else if (vcpu->ready_for_pic_interrupt && - (cpu->interrupt_request & CPU_INTERRUPT_HARD)) { + cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; irq =3D cpu_get_pic_interrupt(env); if (irq >=3D 0) { @@ -1546,7 +1546,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) =20 /* Update the state of the interrupt delivery notification */ if (!vcpu->window_registered && - cpu->interrupt_request & CPU_INTERRUPT_HARD) { + cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD)) { reg_values[reg_count].DeliverabilityNotifications =3D (WHV_X64_DELIVERABILITY_NOTIFICATIONS_REGISTER) { .InterruptNotification =3D 1 @@ -1599,30 +1599,30 @@ static void whpx_vcpu_process_async_events(CPUState= *cpu) CPUX86State *env =3D &x86_cpu->env; AccelCPUState *vcpu =3D cpu->accel; =20 - if ((cpu->interrupt_request & CPU_INTERRUPT_INIT) && + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { whpx_cpu_synchronize_state(cpu); do_cpu_init(x86_cpu); vcpu->interruptable =3D true; } =20 - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_POLL)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; apic_poll_irq(x86_cpu->apic_state); } =20 - if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && + if ((cpu_test_interrupt(cpu, CPU_INTERRUPT_HARD) && (env->eflags & IF_MASK)) || - (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { + cpu_test_interrupt(cpu, CPU_INTERRUPT_NMI)) { cpu->halted =3D false; } =20 - if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_SIPI)) { whpx_cpu_synchronize_state(cpu); do_cpu_sipi(x86_cpu); } =20 - if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { + if (cpu_test_interrupt(cpu, CPU_INTERRUPT_TPR)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_TPR; whpx_cpu_synchronize_state(cpu); apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip, diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index abad84c0547..3a7621c0ea0 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -376,7 +376,7 @@ static bool loongarch_cpu_has_work(CPUState *cs) { bool has_work =3D false; =20 - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_loongarch_hw_interrupts_pending(cpu_env(cs))) { has_work =3D true; } diff --git a/target/m68k/cpu.c b/target/m68k/cpu.c index 6a09db3a6f6..f1b673119d6 100644 --- a/target/m68k/cpu.c +++ b/target/m68k/cpu.c @@ -74,7 +74,7 @@ static void m68k_restore_state_to_opc(CPUState *cs, #ifndef CONFIG_USER_ONLY static bool m68k_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & CPU_INTERRUPT_HARD; + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index ee0a869a94a..22231f09e60 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -129,7 +129,7 @@ static void mb_restore_state_to_opc(CPUState *cs, #ifndef CONFIG_USER_ONLY static bool mb_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 1f6c41fd340..5989c3ba177 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -145,7 +145,7 @@ static bool mips_cpu_has_work(CPUState *cs) * check for interrupts that can be taken. For pre-release 6 CPUs, * check for CP0 Config7 'Wait IE ignore' bit. */ - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_mips_hw_interrupts_pending(env)) { if (cpu_mips_hw_interrupts_enabled(env) || (env->CP0_Config7 & (1 << CP0C7_WII)) || @@ -160,7 +160,7 @@ static bool mips_cpu_has_work(CPUState *cs) * The QEMU model will issue an _WAKE request whenever the CPUs * should be woken up. */ - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_WAKE)) { has_work =3D true; } =20 @@ -170,7 +170,7 @@ static bool mips_cpu_has_work(CPUState *cs) } /* MIPS Release 6 has the ability to halt the CPU. */ if (env->CP0_Config5 & (1 << CP0C5_VP)) { - if (cs->interrupt_request & CPU_INTERRUPT_WAKE) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_WAKE)) { has_work =3D true; } if (!mips_vp_active(env)) { diff --git a/target/mips/kvm.c b/target/mips/kvm.c index ec53acb51a1..450947c3fa5 100644 --- a/target/mips/kvm.c +++ b/target/mips/kvm.c @@ -144,7 +144,7 @@ void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) =20 bql_lock(); =20 - if ((cs->interrupt_request & CPU_INTERRUPT_HARD) && + if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_mips_io_interrupts_pending(cpu)) { intr.cpu =3D -1; intr.irq =3D 2; diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c index dfbb2df643a..9bbfe22ed3a 100644 --- a/target/openrisc/cpu.c +++ b/target/openrisc/cpu.c @@ -78,8 +78,7 @@ static void openrisc_restore_state_to_opc(CPUState *cs, #ifndef CONFIG_USER_ONLY static bool openrisc_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | - CPU_INTERRUPT_TIMER); + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_TIMER= ); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index a0e77f2673e..db841f12603 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7225,7 +7225,7 @@ static int ppc_cpu_mmu_index(CPUState *cs, bool ifetc= h) #ifndef CONFIG_USER_ONLY static bool ppc_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & CPU_INTERRUPT_HARD; + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 015658049e6..d145774b09a 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1354,7 +1354,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu) CPUState *cs =3D CPU(cpu); CPUPPCState *env =3D &cpu->env; =20 - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && + if (!cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && FIELD_EX64(env->msr, MSR, EE)) { cs->halted =3D 1; cs->exception_index =3D EXCP_HLT; diff --git a/target/rx/cpu.c b/target/rx/cpu.c index c6dd5d6f832..da02ae7bf88 100644 --- a/target/rx/cpu.c +++ b/target/rx/cpu.c @@ -75,8 +75,7 @@ static void rx_restore_state_to_opc(CPUState *cs, =20 static bool rx_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & - (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); } =20 static int rx_cpu_mmu_index(CPUState *cs, bool ifunc) diff --git a/target/rx/helper.c b/target/rx/helper.c index 0640ab322b5..ce003af4219 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -44,7 +44,7 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int= rte) void rx_cpu_do_interrupt(CPUState *cs) { CPURXState *env =3D cpu_env(cs); - int do_irq =3D cs->interrupt_request & INT_FLAGS; + int do_irq =3D cpu_test_interrupt(cs, INT_FLAGS); uint32_t save_psw; =20 env->in_sleep =3D 0; diff --git a/target/s390x/cpu-system.c b/target/s390x/cpu-system.c index 709ccd52992..f3a9ffb2a27 100644 --- a/target/s390x/cpu-system.c +++ b/target/s390x/cpu-system.c @@ -49,7 +49,7 @@ bool s390_cpu_has_work(CPUState *cs) return false; } =20 - if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { + if (!cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { return false; } =20 diff --git a/target/sh4/cpu.c b/target/sh4/cpu.c index 4f561e8c912..21ccb86df48 100644 --- a/target/sh4/cpu.c +++ b/target/sh4/cpu.c @@ -108,7 +108,7 @@ static bool superh_io_recompile_replay_branch(CPUState = *cs, =20 static bool superh_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & CPU_INTERRUPT_HARD; + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); } #endif /* !CONFIG_USER_ONLY */ =20 diff --git a/target/sh4/helper.c b/target/sh4/helper.c index fb7642bda1b..1744ef0e6d8 100644 --- a/target/sh4/helper.c +++ b/target/sh4/helper.c @@ -58,7 +58,7 @@ int cpu_sh4_is_cached(CPUSH4State *env, target_ulong addr) void superh_cpu_do_interrupt(CPUState *cs) { CPUSH4State *env =3D cpu_env(cs); - int do_irq =3D cs->interrupt_request & CPU_INTERRUPT_HARD; + int do_irq =3D cpu_test_interrupt(cs, CPU_INTERRUPT_HARD); int do_exp, irq_vector =3D cs->exception_index; =20 /* prioritize exceptions over interrupts */ diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 245caf2de02..c9773f15401 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -783,7 +783,7 @@ static void sparc_restore_state_to_opc(CPUState *cs, #ifndef CONFIG_USER_ONLY static bool sparc_cpu_has_work(CPUState *cs) { - return (cs->interrupt_request & CPU_INTERRUPT_HARD) && + return cpu_test_interrupt(cs, CPU_INTERRUPT_HARD) && cpu_interrupts_enabled(cpu_env(cs)); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/sparc/int64_helper.c b/target/sparc/int64_helper.c index bd14c7a0db9..49e4e51c6dc 100644 --- a/target/sparc/int64_helper.c +++ b/target/sparc/int64_helper.c @@ -89,7 +89,7 @@ void cpu_check_irqs(CPUSPARCState *env) * the next bit is (2 << psrpil). */ if (pil < (2 << env->psrpil)) { - if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); env->interrupt_index =3D 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -120,7 +120,7 @@ void cpu_check_irqs(CPUSPARCState *env) break; } } - } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { + } else if (cpu_test_interrupt(cs, CPU_INTERRUPT_HARD)) { trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softi= nt, env->interrupt_index); env->interrupt_index =3D 0; --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756568328; cv=none; d=zohomail.com; s=zohoarc; b=Cz2NFvzm5wOJbFd2mfB5rGeRm64zDiwNd44UbtqjEZvgjqi51ADCZLESWqgbk5uQV/gzAkj9L1HxAt7qHqkV1utt+snmNqPBcFKDJP4X1W8CPjy6aW7Yw7EwY/gqJkfo2ZMdQcucVR6vCs+HjPdl1JZ1F17DNethdG0CvEC/c48= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 06:00:50 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFl/yq7DKUacBbEGNQMFu2WNmfyJ0yh1gJONhbfuoGUwZhUI52suGzBzk5YsZVXsm/iFYS0KQ== X-Received: by 2002:a05:600c:35c9:b0:459:d821:a45b with SMTP id 5b1f17b1804b1-45b5179e76dmr233551485e9.9.1756472450190; Fri, 29 Aug 2025 06:00:50 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Igor Mammedov , Peter Xu Subject: [PULL 22/28] memory: reintroduce BQL-free fine-grained PIO/MMIO Date: Fri, 29 Aug 2025 14:59:29 +0200 Message-ID: <20250829125935.1526984-23-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756568331307124100 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov This patch brings back Jan's idea [1] of BQL-free IO access This will let us make access to ACPI PM/HPET timers cheaper, and prevent BQL contention in case of workload that heavily uses the timers with a lot of vCPUs. 1) 196ea13104f (memory: Add global-locking property to memory regions) ... de7ea885c539 (kvm: Switch to unlocked MMIO) Signed-off-by: Igor Mammedov Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/20250814160600.2327672-2-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- include/system/memory.h | 12 ++++++++++++ system/memory.c | 15 +++++++++++++++ system/physmem.c | 2 +- 3 files changed, 28 insertions(+), 1 deletion(-) diff --git a/include/system/memory.h b/include/system/memory.h index e2cd6ed1261..aa85fc27a10 100644 --- a/include/system/memory.h +++ b/include/system/memory.h @@ -833,6 +833,7 @@ struct MemoryRegion { bool nonvolatile; bool rom_device; bool flush_coalesced_mmio; + bool lockless_io; bool unmergeable; uint8_t dirty_log_mask; bool is_iommu; @@ -2341,6 +2342,17 @@ void memory_region_set_flush_coalesced(MemoryRegion = *mr); */ void memory_region_clear_flush_coalesced(MemoryRegion *mr); =20 +/** + * memory_region_enable_lockless_io: Enable lockless (BQL free) acceess. + * + * Enable BQL-free access for devices that are well prepared to handle + * locking during I/O themselves: either by doing fine grained locking or + * by providing lock-free I/O schemes. + * + * @mr: the memory region to be updated. + */ +void memory_region_enable_lockless_io(MemoryRegion *mr); + /** * memory_region_add_eventfd: Request an eventfd to be triggered when a wo= rd * is written to a location. diff --git a/system/memory.c b/system/memory.c index 56465479406..44701c465c1 100644 --- a/system/memory.c +++ b/system/memory.c @@ -2546,6 +2546,21 @@ void memory_region_clear_flush_coalesced(MemoryRegio= n *mr) } } =20 +void memory_region_enable_lockless_io(MemoryRegion *mr) +{ + mr->lockless_io =3D true; + /* + * reentrancy_guard has per device scope, that when enabled + * will effectively prevent concurrent access to device's IO + * MemoryRegion(s) by not calling accessor callback. + * + * Turn it off for lock-less IO enabled devices, to allow + * concurrent IO. + * TODO: remove this when reentrancy_guard becomes per transaction. + */ + mr->disable_reentrancy_guard =3D true; +} + void memory_region_add_eventfd(MemoryRegion *mr, hwaddr addr, unsigned size, diff --git a/system/physmem.c b/system/physmem.c index e5dd760e0bc..f498572fc82 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -2900,7 +2900,7 @@ bool prepare_mmio_access(MemoryRegion *mr) { bool release_lock =3D false; =20 - if (!bql_locked()) { + if (!bql_locked() && !mr->lockless_io) { bql_lock(); release_lock =3D true; } --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 29 Aug 2025 06:00:53 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGdGjxsOOQTmODX/yZn9S7o0GsDaexHFAVVO/87hJ0D90AUqtnb/U2S1+h/BoufocZvx4EpZw== X-Received: by 2002:a05:600c:4f12:b0:459:dde3:1a37 with SMTP id 5b1f17b1804b1-45b66343ea2mr120076775e9.25.1756472453487; Fri, 29 Aug 2025 06:00:53 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Igor Mammedov , Peter Xu , "Michael S. Tsirkin" Subject: [PULL 23/28] acpi: mark PMTIMER as unlocked Date: Fri, 29 Aug 2025 14:59:30 +0200 Message-ID: <20250829125935.1526984-24-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756569400775116600 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Reading QEMU_CLOCK_VIRTUAL is thread-safe, write access is NOP. This makes possible to boot Windows with large vCPUs count when hv-time is not used. Reproducer: -M q35,hpet=3Doff -cpu host -enable-kvm -smp 240,sockets=3D4 -m 8G WS2025= .img fails to boot within 30min. With this fix it boots within 2-1min. Signed-off-by: Igor Mammedov Reviewed-by: Peter Xu Acked-by: Michael S. Tsirkin Link: https://lore.kernel.org/r/20250814160600.2327672-3-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- hw/acpi/core.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/acpi/core.c b/hw/acpi/core.c index 58f8964e130..ff165828033 100644 --- a/hw/acpi/core.c +++ b/hw/acpi/core.c @@ -547,6 +547,7 @@ void acpi_pm_tmr_init(ACPIREGS *ar, acpi_update_sci_fn = update_sci, ar->tmr.timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, acpi_pm_tmr_timer, = ar); memory_region_init_io(&ar->tmr.io, memory_region_owner(parent), &acpi_pm_tmr_ops, ar, "acpi-tmr", 4); + memory_region_enable_lockless_io(&ar->tmr.io); memory_region_add_subregion(parent, 8, &ar->tmr.io); } =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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Fri, 29 Aug 2025 06:00:59 -0700 (PDT) X-Google-Smtp-Source: AGHT+IHSAjb7hyifQXIMNGh5s3fBnPMSLDF3TFTYmDsxKKRWgZuXq0AB1WHRhKxIW+o3MWszv4TWkQ== X-Received: by 2002:a5d:5887:0:b0:3b7:88f5:eaae with SMTP id ffacd0b85a97d-3c5dc542ac7mr20824998f8f.39.1756472458477; Fri, 29 Aug 2025 06:00:58 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Igor Mammedov , Peter Xu Subject: [PULL 24/28] hpet: switch to fine-grained device locking Date: Fri, 29 Aug 2025 14:59:31 +0200 Message-ID: <20250829125935.1526984-25-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; 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Signed-off-by: Igor Mammedov Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/20250814160600.2327672-4-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index cb48cc151f1..ab5aa59ae4e 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -38,6 +38,7 @@ #include "hw/timer/i8254.h" #include "system/address-spaces.h" #include "qom/object.h" +#include "qemu/lockable.h" #include "trace.h" =20 struct hpet_fw_config hpet_fw_cfg =3D {.count =3D UINT8_MAX}; @@ -69,6 +70,7 @@ struct HPETState { SysBusDevice parent_obj; /*< public >*/ =20 + QemuMutex lock; MemoryRegion iomem; uint64_t hpet_offset; bool hpet_offset_saved; @@ -428,6 +430,7 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr addr, trace_hpet_ram_read(addr); addr &=3D ~4; =20 + QEMU_LOCK_GUARD(&s->lock); /*address range of all global regs*/ if (addr <=3D 0xff) { switch (addr) { @@ -482,6 +485,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, int len =3D MIN(size * 8, 64 - shift); uint64_t old_val, new_val, cleared; =20 + QEMU_LOCK_GUARD(&s->lock); trace_hpet_ram_write(addr, value); addr &=3D ~4; =20 @@ -679,8 +683,10 @@ static void hpet_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); HPETState *s =3D HPET(obj); =20 + qemu_mutex_init(&s->lock); /* HPET Area */ memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_L= EN); + memory_region_enable_lockless_io(&s->iomem); sysbus_init_mmio(sbd, &s->iomem); } =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:09 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756574629; cv=none; d=zohomail.com; s=zohoarc; b=JdaebszX0oX1QddkFdZ/jAQzP1SwWsoBhAUFqPYApDPRT2qgtqk+KcBHt6FLBq3D5AiIUyFZGtqmAanxKDJO6jpWjbnP40CBn1+rbTUIbQ7lAF/UuH3LxE3Y3rVTEEriS5T8JBaClJcIyQ9i+pP+5TyamCilvRuYtpy3sotSx1w= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 06:01:02 -0700 (PDT) X-Google-Smtp-Source: AGHT+IFzpbmdD6NQq2vTFnKGN/6cnfNrrjKpUuP6QPaxbVk3vlZCOKff2eDDKni4SzcCXYOaw4fUvw== X-Received: by 2002:a05:600c:1d26:b0:45b:7c20:5709 with SMTP id 5b1f17b1804b1-45b7c205c14mr51129975e9.12.1756472461632; Fri, 29 Aug 2025 06:01:01 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Igor Mammedov , Peter Xu Subject: [PULL 25/28] hpet: move out main counter read into a separate block Date: Fri, 29 Aug 2025 14:59:32 +0200 Message-ID: <20250829125935.1526984-26-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756574630713116600 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Follow up patche will switch main counter read to lock-less mode. As preparation for that move relevant branch into a separate top level block to make followup patch cleaner/simplier by reducing contextual noise when lock-less read is introduced. no functional changes. Signed-off-by: Igor Mammedov Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/20250814160600.2327672-5-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index ab5aa59ae4e..c776afc0f2d 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -431,6 +431,16 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr add= r, addr &=3D ~4; =20 QEMU_LOCK_GUARD(&s->lock); + if (addr =3D=3D HPET_COUNTER) { + if (hpet_enabled(s)) { + cur_tick =3D hpet_get_ticks(s); + } else { + cur_tick =3D s->hpet_counter; + } + trace_hpet_ram_read_reading_counter(addr & 4, cur_tick); + return cur_tick >> shift; + } + /*address range of all global regs*/ if (addr <=3D 0xff) { switch (addr) { @@ -438,14 +448,6 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr add= r, return s->capability >> shift; case HPET_CFG: return s->config >> shift; - case HPET_COUNTER: - if (hpet_enabled(s)) { - cur_tick =3D hpet_get_ticks(s); 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Fri, 29 Aug 2025 06:01:07 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF8Yv6xglzILBEpowjUqr6BdN0rB6z6cY37+FPkiEMRwvy3C3MmejApndDCueeE0XWKUSgM8Q== X-Received: by 2002:a05:600c:4590:b0:45b:47e1:ef67 with SMTP id 5b1f17b1804b1-45b517e8d46mr198626105e9.34.1756472466806; Fri, 29 Aug 2025 06:01:06 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Igor Mammedov , Peter Xu Subject: [PULL 26/28] hpet: make main counter read lock-less Date: Fri, 29 Aug 2025 14:59:33 +0200 Message-ID: <20250829125935.1526984-27-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756571799082116600 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov Make access to main HPET counter lock-less. In unlikely event of an update in progress, readers will busy wait untill update is finished. As result micro benchmark of concurrent reading of HPET counter with large number of vCPU shows over 80% better (less) latency. Signed-off-by: Igor Mammedov Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/20250814160600.2327672-6-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- hw/timer/hpet.c | 26 ++++++++++++++++++++------ 1 file changed, 20 insertions(+), 6 deletions(-) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index c776afc0f2d..789a31d0a08 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -39,6 +39,7 @@ #include "system/address-spaces.h" #include "qom/object.h" #include "qemu/lockable.h" +#include "qemu/seqlock.h" #include "trace.h" =20 struct hpet_fw_config hpet_fw_cfg =3D {.count =3D UINT8_MAX}; @@ -74,6 +75,7 @@ struct HPETState { MemoryRegion iomem; uint64_t hpet_offset; bool hpet_offset_saved; + QemuSeqLock state_version; qemu_irq irqs[HPET_NUM_IRQ_ROUTES]; uint32_t flags; uint8_t rtc_irq_level; @@ -430,17 +432,25 @@ static uint64_t hpet_ram_read(void *opaque, hwaddr ad= dr, trace_hpet_ram_read(addr); addr &=3D ~4; =20 - QEMU_LOCK_GUARD(&s->lock); if (addr =3D=3D HPET_COUNTER) { - if (hpet_enabled(s)) { - cur_tick =3D hpet_get_ticks(s); - } else { - cur_tick =3D s->hpet_counter; - } + unsigned version; + + /* + * Write update is rare, so busywait here is unlikely to happen + */ + do { + version =3D seqlock_read_begin(&s->state_version); + if (unlikely(!hpet_enabled(s))) { + cur_tick =3D s->hpet_counter; + } else { + cur_tick =3D hpet_get_ticks(s); + } + } while (seqlock_read_retry(&s->state_version, version)); trace_hpet_ram_read_reading_counter(addr & 4, cur_tick); return cur_tick >> shift; } =20 + QEMU_LOCK_GUARD(&s->lock); /*address range of all global regs*/ if (addr <=3D 0xff) { switch (addr) { @@ -500,6 +510,7 @@ static void hpet_ram_write(void *opaque, hwaddr addr, old_val =3D s->config; new_val =3D deposit64(old_val, shift, len, value); new_val =3D hpet_fixup_reg(new_val, old_val, HPET_CFG_WRITE_MA= SK); + seqlock_write_begin(&s->state_version); s->config =3D new_val; if (activating_bit(old_val, new_val, HPET_CFG_ENABLE)) { /* Enable main counter and interrupt generation. */ @@ -518,6 +529,8 @@ static void hpet_ram_write(void *opaque, hwaddr addr, hpet_del_timer(&s->timer[i]); } } + seqlock_write_end(&s->state_version); + /* i8254 and RTC output pins are disabled * when HPET is in legacy mode */ if (activating_bit(old_val, new_val, HPET_CFG_LEGACY)) { @@ -686,6 +699,7 @@ static void hpet_init(Object *obj) HPETState *s =3D HPET(obj); =20 qemu_mutex_init(&s->lock); + seqlock_init(&s->state_version); /* HPET Area */ memory_region_init_io(&s->iomem, obj, &hpet_ram_ops, s, "hpet", HPET_L= EN); memory_region_enable_lockless_io(&s->iomem); --=20 2.51.0 From nobody Sun Sep 28 16:28:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1756569692; cv=none; d=zohomail.com; s=zohoarc; b=Lc62uYfoDK+QrapgvDZGoJXoGUm4eJLekfoBl5wWp05Z3meCxi8f6F2bgmb6iLMNQpGFnNHNHNPL1XkaADVCm5GeqZaohwjmOTgmmESv9xSb6y+pC+Wp2irupP+/stV8D0JhW/9YMCL3gryZFYE+4MdQRS0j6R9Ii9AOXdl9tkE= ARC-Message-Signature: i=1; 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Fri, 29 Aug 2025 06:01:21 -0700 (PDT) X-Google-Smtp-Source: AGHT+IGSBuU5yy7Mbc2ZujWUqM7uq+Zevh2Of9cZsRwLKDJSP0n7lyT5LILB49ctQmqQ6g17DxWDlw== X-Received: by 2002:a5d:5d87:0:b0:3c8:f348:7882 with SMTP id ffacd0b85a97d-3c8f34887d8mr15009694f8f.54.1756472479781; Fri, 29 Aug 2025 06:01:19 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: Igor Mammedov , Peter Xu Subject: [PULL 27/28] kvm: i386: irqchip: take BQL only if there is an interrupt Date: Fri, 29 Aug 2025 14:59:34 +0200 Message-ID: <20250829125935.1526984-28-pbonzini@redhat.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250829125935.1526984-1-pbonzini@redhat.com> References: <20250829125935.1526984-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756569694948124100 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov when kernel-irqchip=3Dsplit is used, QEMU still hits BQL contention issue when reading ACPI PM/HPET timers (despite of timer[s] access being lock-less). So Windows with more than 255 cpus is still not able to boot (since it requires iommu -> split irqchip). Problematic path is in kvm_arch_pre_run() where BQL is taken unconditionally when split irqchip is in use. There are a few parts that BQL protects there: 1. interrupt check and injecting however we do not take BQL when checking for pending interrupt (even within the same function), so the patch takes the same approach for cpu->interrupt_request checks and takes BQL only if there is a job to do. 2. request_interrupt_window access CPUState::kvm_run::request_interrupt_window doesn't need BQL as it's accessed by its own vCPU thread. 3. cr8/cpu_get_apic_tpr access the same (as #2) applies to CPUState::kvm_run::cr8, and APIC registers are also cached/synced (get/put) within the vCPU thread it belongs to. Taking BQL only when is necessary, eleminates BQL bottleneck on IO/MMIO only exit path, improoving latency by 80% on HPET micro benchmark. This lets Windows to boot succesfully (in case hv-time isn't used) when more than 255 vCPUs are in use. Signed-off-by: Igor Mammedov Reviewed-by: Peter Xu Link: https://lore.kernel.org/r/20250814160600.2327672-8-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- target/i386/kvm/kvm.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index a7b5c8f81bc..306430a0521 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -5478,9 +5478,6 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) } } =20 - if (!kvm_pic_in_kernel()) { - bql_lock(); - } =20 /* Force the VCPU out of its inner loop to process any INIT requests * or (for userspace APIC, but it is cheap to combine the checks here) @@ -5489,10 +5486,10 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run= *run) if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR)) { if (cpu_test_interrupt(cpu, CPU_INTERRUPT_INIT) && !(env->hflags & HF_SMM_MASK)) { - cpu->exit_request =3D 1; + qatomic_set(&cpu->exit_request, 1); } if (cpu_test_interrupt(cpu, CPU_INTERRUPT_TPR)) { - cpu->exit_request =3D 1; + qatomic_set(&cpu->exit_request, 1); } } =20 @@ -5503,6 +5500,8 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) (env->eflags & IF_MASK)) { int irq; =20 + bql_lock(); + cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; irq =3D cpu_get_pic_interrupt(env); if (irq >=3D 0) { @@ -5517,6 +5516,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) strerror(-ret)); } } + bql_unlock(); } =20 /* If we have an interrupt but the guest is not ready to receive an @@ -5531,8 +5531,6 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) =20 DPRINTF("setting tpr\n"); run->cr8 =3D cpu_get_apic_tpr(x86_cpu->apic_state); - - bql_unlock(); } } =20 --=20 2.51.0 From nobody Sun Sep 28 16:28:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=quarantine dis=none) header.from=redhat.com ARC-Seal: i=1; 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envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1756570287070116600 Content-Type: text/plain; charset="utf-8" From: Igor Mammedov in cpu_handle_interrupt() the only place where cached interrupt_request might have effect is when CPU_INTERRUPT_SSTEP_MASK applied and cached interrupt_request handed over to cpu_exec_interrupt() and need_replay_interrupt(). Simplify code by moving interrupt_request caching and CPU_INTERRUPT_SSTEP_M= ASK masking into the block where it actually matters and drop reloading cached = value from CPUState:interrupt_request as the rest of the code directly uses CPUState:interrupt_request. Signed-off-by: Igor Mammedov Link: https://lore.kernel.org/r/20250814160600.2327672-9-imammedo@redhat.com Signed-off-by: Paolo Bonzini --- accel/tcg/cpu-exec.c | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index 96c124aa720..8491e5badd1 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -782,13 +782,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, assert(!cpu_test_interrupt(cpu, ~0)); #else if (unlikely(cpu_test_interrupt(cpu, ~0))) { - int interrupt_request; bql_lock(); - interrupt_request =3D cpu->interrupt_request; - if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) { - /* Mask out external interrupts for this step. */ - interrupt_request &=3D ~CPU_INTERRUPT_SSTEP_MASK; - } if (cpu_test_interrupt(cpu, CPU_INTERRUPT_DEBUG)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_DEBUG; cpu->exception_index =3D EXCP_DEBUG; @@ -806,6 +800,7 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, return true; } else { const TCGCPUOps *tcg_ops =3D cpu->cc->tcg_ops; + int interrupt_request =3D cpu->interrupt_request; =20 if (cpu_test_interrupt(cpu, CPU_INTERRUPT_RESET)) { replay_interrupt(); @@ -814,6 +809,11 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, return true; } =20 + if (unlikely(cpu->singlestep_enabled & SSTEP_NOIRQ)) { + /* Mask out external interrupts for this step. */ + interrupt_request &=3D ~CPU_INTERRUPT_SSTEP_MASK; + } + /* * The target hook has 3 exit conditions: * False when the interrupt isn't processed, @@ -838,9 +838,6 @@ static inline bool cpu_handle_interrupt(CPUState *cpu, cpu->exception_index =3D -1; *last_tb =3D NULL; } - /* The target hook may have updated the 'cpu->interrupt_reques= t'; - * reload the 'interrupt_request' value */ - interrupt_request =3D cpu->interrupt_request; } if (cpu_test_interrupt(cpu, CPU_INTERRUPT_EXITTB)) { cpu->interrupt_request &=3D ~CPU_INTERRUPT_EXITTB; --=20 2.51.0