From nobody Sun Sep 28 16:35:53 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175656627468580.25834313522853; Sat, 30 Aug 2025 08:04:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1usN3Z-0001ge-5G; Sat, 30 Aug 2025 10:59:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urpGx-0008MV-HG for qemu-devel@nongnu.org; Thu, 28 Aug 2025 22:55:27 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1urpGr-000798-Fj for qemu-devel@nongnu.org; Thu, 28 Aug 2025 22:55:26 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxSNGVFrFoqm4EAA--.9038S3; Fri, 29 Aug 2025 10:55:17 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxbMGMFrFoKstvAA--.33085S7; Fri, 29 Aug 2025 10:55:17 +0800 (CST) From: Bibo Mao To: qemu-devel@nongnu.org Cc: Richard Henderson Subject: [PULL 05/14] target/loongarch: Add enum type TLBRet definition Date: Fri, 29 Aug 2025 10:54:58 +0800 Message-Id: <20250829025507.2315073-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250829025507.2315073-1-maobibo@loongson.cn> References: <20250829025507.2315073-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxbMGMFrFoKstvAA--.33085S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756566275551124100 Content-Type: text/plain; charset="utf-8" There is mixed usage between enum variable TLBRET_xxx and int type, here add enum type TLBRet definition and replace int type variable with enum type TLBRet in some functions. Signed-off-by: Bibo Mao Reviewed-by: Richard Henderson --- target/loongarch/cpu-mmu.h | 27 ++++++++++++++------------- target/loongarch/cpu_helper.c | 26 ++++++++++++++------------ target/loongarch/tcg/tcg_loongarch.h | 7 ++++--- target/loongarch/tcg/tlb_helper.c | 16 ++++++++-------- 4 files changed, 40 insertions(+), 36 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 4c5cbd7425..cbe6f37773 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -8,21 +8,22 @@ #ifndef LOONGARCH_CPU_MMU_H #define LOONGARCH_CPU_MMU_H =20 -enum { - TLBRET_MATCH =3D 0, - TLBRET_BADADDR =3D 1, - TLBRET_NOMATCH =3D 2, - TLBRET_INVALID =3D 3, - TLBRET_DIRTY =3D 4, - TLBRET_RI =3D 5, - TLBRET_XI =3D 6, - TLBRET_PE =3D 7, -}; +typedef enum TLBRet { + TLBRET_MATCH, + TLBRET_BADADDR, + TLBRET_NOMATCH, + TLBRET_INVALID, + TLBRET_DIRTY, + TLBRET_RI, + TLBRET_XI, + TLBRET_PE, +} TLBRet; =20 bool check_ps(CPULoongArchState *ent, uint8_t ps); -int get_physical_address(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx, int is_de= bug); +TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx, + int is_debug); void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, target_ulong level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 418122f447..17a0735f5c 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -44,8 +44,9 @@ void get_dir_base_width(CPULoongArchState *env, uint64_t = *dir_base, } } =20 -static int loongarch_page_table_walker(CPULoongArchState *env, hwaddr *phy= sical, - int *prot, target_ulong address) +static TLBRet loongarch_page_table_walker(CPULoongArchState *env, + hwaddr *physical, + int *prot, target_ulong address) { CPUState *cs =3D env_cpu(env); target_ulong index, phys; @@ -116,15 +117,15 @@ static int loongarch_page_table_walker(CPULoongArchSt= ate *env, hwaddr *physical, /* mask other attribute bits */ *physical =3D base & TARGET_PAGE_MASK; =20 - return 0; + return TLBRET_MATCH; } =20 -static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx, - int is_debug) +static TLBRet loongarch_map_address(CPULoongArchState *env, hwaddr *physic= al, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx, + int is_debug) { - int ret; + TLBRet ret; =20 if (tcg_enabled()) { ret =3D loongarch_get_addr_from_tlb(env, physical, prot, address, @@ -158,9 +159,10 @@ static hwaddr dmw_va2pa(CPULoongArchState *env, target= _ulong va, } } =20 -int get_physical_address(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx, int is_de= bug) +TLBRet get_physical_address(CPULoongArchState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx, + int is_debug) { int user_mode =3D mmu_idx =3D=3D MMU_USER_IDX; int kernel_mode =3D mmu_idx =3D=3D MMU_KERNEL_IDX; @@ -214,7 +216,7 @@ hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cs, = vaddr addr) int prot; =20 if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(cs, false), 1) !=3D 0) { + cpu_mmu_index(cs, false), 1) !=3D TLBRET_MATC= H) { return -1; } return phys_addr; diff --git a/target/loongarch/tcg/tcg_loongarch.h b/target/loongarch/tcg/tc= g_loongarch.h index fd4e116022..488700c3c3 100644 --- a/target/loongarch/tcg/tcg_loongarch.h +++ b/target/loongarch/tcg/tcg_loongarch.h @@ -7,6 +7,7 @@ #ifndef TARGET_LOONGARCH_TCG_LOONGARCH_H #define TARGET_LOONGARCH_TCG_LOONGARCH_H #include "cpu.h" +#include "cpu-mmu.h" =20 void loongarch_csr_translate_init(void); =20 @@ -14,8 +15,8 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 -int loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx); +TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physica= l, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx); =20 #endif /* TARGET_LOONGARCH_TCG_LOONGARCH_H */ diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 1f49619e7f..4a2a565985 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -30,7 +30,7 @@ bool check_ps(CPULoongArchState *env, uint8_t tlb_ps) } =20 static void raise_mmu_exception(CPULoongArchState *env, target_ulong addre= ss, - MMUAccessType access_type, int tlb_error) + MMUAccessType access_type, TLBRet tlb_erro= r) { CPUState *cs =3D env_cpu(env); =20 @@ -517,7 +517,7 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, CPULoongArchState *env =3D cpu_env(cs); hwaddr physical; int prot; - int ret; + TLBRet ret; =20 /* Data access */ ret =3D get_physical_address(env, &physical, &prot, address, @@ -648,9 +648,9 @@ void helper_ldpte(CPULoongArchState *env, target_ulong = base, target_ulong odd, env->CSR_TLBREHI =3D FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, PS, ps); } =20 -static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physica= l, - int *prot, target_ulong address, - int access_type, int index, int mmu_idx) +static TLBRet loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *phys= ical, + int *prot, target_ulong address, + int access_type, int index, int mmu_= idx) { LoongArchTLB *tlb =3D &env->tlb[index]; uint64_t plv =3D mmu_idx; @@ -713,9 +713,9 @@ static int loongarch_map_tlb_entry(CPULoongArchState *e= nv, hwaddr *physical, return TLBRET_MATCH; } =20 -int loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physical, - int *prot, target_ulong address, - MMUAccessType access_type, int mmu_idx) +TLBRet loongarch_get_addr_from_tlb(CPULoongArchState *env, hwaddr *physica= l, + int *prot, target_ulong address, + MMUAccessType access_type, int mmu_idx) { int index, match; =20 --=20 2.43.5