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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b79799c33sm28691015e9.5.2025.08.28.04.34.37 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 04:34:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756380879; x=1756985679; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=rh690dxt7d9YAOfCnBE3P+AaRyL65K9p7Ens+Z41Pjc=; b=uOGfye/mw9iHtH49OCMMvJA1kn7aNH55ZxX58MEBpVkjroFEeAr4wJAmVXRTjAnZlr +hwOcvSaS1lOFu1i8X92hEHK/yla17YRY5DXMpntNBr8m6jfDsyl8d5Jx4MjzxuroH/1 tGGcw19K+RVrQeh2BtjYHdyThcBdzXFO3ve/mZeG5kOiSEGC6Qiuf98W/h1I0pblxwsV 6VWVQKJjsdMxtZz8/6skVquVr6G4p58SyVXVRoPfewL2tAmK4FU8EYmH2M3jTHRmgCjJ PPS/Uj/lbOrTyUUj62gWk6oRjavfoljulLV9+ttnVSTB+q9TDf9g9wADBmejV8q/jwCM A0Kw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756380879; x=1756985679; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=rh690dxt7d9YAOfCnBE3P+AaRyL65K9p7Ens+Z41Pjc=; b=AzQqrKwKiagcxBCzxt/nBR7wEry4W9IguWN43vcYDa4vUw9gvGGtCyM3gzqkruDM9j 1qDVI9koArb5u0Q2fPK3fpF+oByidEGrsvMuo2luh6IRPtpAvcJSmcWbzoypp+9//Gq6 tvjqYSfc2QGXEnwhLpsVVn5pMz52uDBVPt4RYkCN8Bda0fqFSeILyXHPD7BzQePej6vX 2SqoogMMg/4gcx8RD2Mh52ZwFXPupYFA3ZF8IfRkLasvydzvotMjBZZ//vEPoHq7DHX9 lbv1aES9zb7gaCrbecXSHYU0NdwAudnUwL1ihFUh+/41bQPqXJOFgd0Unrvjeknw87An /o4Q== X-Gm-Message-State: AOJu0YwA3Iu4zTQprO2COqY94aRdP6k6WuxCPzO8HyqzyHAbBKH1YeU0 h9ZbnRBOBWT06ClyyUrnhhMhHZMJ+oHyH2ZYF9Iv7zmYOlajYnW2Rxelj7lCVHr64NX9PTtyjGT QNFY0 X-Gm-Gg: ASbGncvvkG5WGlSCTJCY/220eOIV1gCD1Nbf0PJ6eOfpYlaQo4w+eAAyowgGbhrgXB2 ql6TSAkptK4FfNWMk0QBz5m2Mnv+aM4pc67sq3gSgfSU+xeuP4du9sW2dV9uPMoRKOHOTmB1KOp bRaupn61l6cHSe/ay1yCYVNKMdmMaQGO82dQAqPOMi5QoTI4k0QTiZZx10Kjait0M9NoeW/L5KL ngx1dYRImzcRfWnwdaoJHdDGLFUCtYb4Ws8BY1FmoQFnbXXocDZt+RPU7CoK9QgeGtzQEr0r4Zr z/u+/sfY60r5h0gGGbA1QLy5V7I6h9CkHx27v7OR1GPF4a/GSATfsErAyap1ruUrzUieIgbIZrX +o8j9DHdZC1UPq6z0S5+TxR0QlWFl1sZNWRFI3GQ= X-Google-Smtp-Source: AGHT+IGNgBysGFYSXBcnPRxZ4qw5fctSgFEyBlxLNinbrdUm4adieXv9faOCx9KN8xH0HXH1KSCGcA== X-Received: by 2002:a05:600c:5491:b0:456:1d4e:c127 with SMTP id 5b1f17b1804b1-45b5179cdf4mr211284145e9.8.1756380878939; Thu, 28 Aug 2025 04:34:38 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/32] target/arm: Implement FEAT_TCR2 and enable with -cpu max Date: Thu, 28 Aug 2025 12:34:02 +0100 Message-ID: <20250828113430.3214314-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828113430.3214314-1-peter.maydell@linaro.org> References: <20250828113430.3214314-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756381385312116600 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Add FEAT_TCR2, which introduces the TCR2_EL1 and TCR2_EL2 registers. These registers are extensions of the TCR_ELx registers and provide top-level control of the EL10 and EL20 translation regimes. Signed-off-by: Gustavo Romero Signed-off-by: Richard Henderson Reviewed-by: Richard Henderson Message-id: 20250727074202.83141-5-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-5-gustavo.romero@linaro.org> Reviewed-by: Richard Henderson [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 +++ target/arm/cpu.h | 2 + target/arm/internals.h | 19 ++++++++++ target/arm/cpu.c | 3 ++ target/arm/helper.c | 71 +++++++++++++++++++++++++++++++++++ target/arm/tcg/cpu64.c | 1 + 7 files changed, 102 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 66043b0747a..1c597d86738 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -149,6 +149,7 @@ the following architecture extensions: - FEAT_SPECRES (Speculation restriction instructions) - FEAT_SSBS (Speculative Store Bypass Safe) - FEAT_SSBS2 (MRS and MSR instructions for SSBS version 2) +- FEAT_TCR2 (Support for TCR2_ELx) - FEAT_TGran16K (Support for 16KB memory translation granule size at stage= 1) - FEAT_TGran4K (Support for 4KB memory translation granule size at stage 1) - FEAT_TGran64K (Support for 64KB memory translation granule size at stage= 1) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e372543bf35..8ec8c3feb3d 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_tcr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, TCRX) !=3D 0; +} + static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 08a29802e13..c15d79a106b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -366,6 +366,7 @@ typedef struct CPUArchState { uint64_t vsttbr_el2; /* Secure Virtualization Translation Table. */ /* MMU translation table base control. */ uint64_t tcr_el[4]; + uint64_t tcr2_el[3]; uint64_t vtcr_el2; /* Virtualization Translation Control. */ uint64_t vstcr_el2; /* Secure Virtualization Translation Control. = */ uint32_t c2_data; /* MPU data cacheable bits. */ @@ -1726,6 +1727,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_TCR2EN (1ULL << 43) #define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) diff --git a/target/arm/internals.h b/target/arm/internals.h index fb722362551..f5a1e75db37 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -196,6 +196,24 @@ FIELD(CPTR_EL3, TCPAC, 31, 1) #define TTBCR_SH1 (1U << 28) #define TTBCR_EAE (1U << 31) =20 +#define TCR2_PNCH (1ULL << 0) +#define TCR2_PIE (1ULL << 1) +#define TCR2_E0POE (1ULL << 2) +#define TCR2_POE (1ULL << 3) +#define TCR2_AIE (1ULL << 4) +#define TCR2_D128 (1ULL << 5) +#define TCR2_PTTWI (1ULL << 10) +#define TCR2_HAFT (1ULL << 11) +#define TCR2_AMEC0 (1ULL << 12) +#define TCR2_AMEC1 (1ULL << 13) +#define TCR2_DISCH0 (1ULL << 14) +#define TCR2_DISCH1 (1ULL << 15) +#define TCR2_A2 (1ULL << 16) +#define TCR2_FNG0 (1ULL << 17) +#define TCR2_FNG1 (1ULL << 18) +#define TCR2_FNGNA0 (1ULL << 20) +#define TCR2_FNGNA1 (1ULL << 21) + FIELD(VTCR, T0SZ, 0, 6) FIELD(VTCR, SL0, 6, 2) FIELD(VTCR, IRGN0, 8, 2) @@ -230,6 +248,7 @@ FIELD(VSTCR, SA, 30, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_TCR2EN (1ULL << 14) #define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2ab04cb5f7c..27a4610da59 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -644,6 +644,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + env->cp15.scr_el3 |=3D SCR_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { env->cp15.scr_el3 |=3D SCR_SCTLR2EN; } diff --git a/target/arm/helper.c b/target/arm/helper.c index 11ddeabb132..5a219703aed 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -741,6 +741,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + valid_mask |=3D SCR_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D SCR_SCTLR2EN; } @@ -3922,6 +3925,9 @@ static void hcrx_write(CPUARMState *env, const ARMCPR= egInfo *ri, if (cpu_isar_feature(aa64_xs, cpu)) { valid_mask |=3D HCRX_FGTNXS | HCRX_FNXS; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + valid_mask |=3D HCRX_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { valid_mask |=3D HCRX_SCTLR2EN; } @@ -3989,6 +3995,9 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) if (cpu_isar_feature(aa64_mops, cpu)) { hcrx |=3D HCRX_MSCEN; } + if (cpu_isar_feature(aa64_tcr2, cpu)) { + hcrx |=3D HCRX_TCR2EN; + } if (cpu_isar_feature(aa64_sctlr2, cpu)) { hcrx |=3D HCRX_SCTLR2EN; } @@ -4529,6 +4538,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), "TCR_EL1", "TCR_EL2", "TCR_EL12" }, + { K(3, 0, 2, 0, 3), K(3, 4, 2, 0, 3), K(3, 5, 2, 0, 3), + "TCR2_EL1", "TCR2_EL2", "TCR2_EL12", isar_feature_aa64_tcr2 }, { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), @@ -6073,6 +6084,62 @@ static const ARMCPRegInfo sctlr2_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, }; =20 +static CPAccessResult tcr2_el2_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_TCR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult tcr2_el1_access(CPUARMState *env, const ARMCPRegInfo= *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_TCR2EN))= { + return CP_ACCESS_TRAP_EL2; + } + return tcr2_el2_access(env, ri, isread); +} + +static void tcr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void tcr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo tcr2_reginfo[] =3D { + { .name =3D "TCR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D tcr2_el1_access, + .writefn =3D tcr2_el1_write, .fgt =3D FGT_TCR_EL1, + .nv2_redirect_offset =3D 0x270 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[1]) }, + { .name =3D "TCR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 2, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D tcr2_el2_access, + .writefn =3D tcr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.tcr2_el[2]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7306,6 +7373,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, sctlr2_reginfo); } =20 + if (cpu_isar_feature(aa64_tcr2, cpu)) { + define_arm_cp_regs(cpu, tcr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index f4efff03a59..4eb51420ef6 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1248,6 +1248,7 @@ void aarch64_max_tcg_initfn(Object *obj) SET_IDREG(isar, ID_AA64MMFR2, t); =20 t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, TCRX, 1); /* FEAT_TCR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ SET_IDREG(isar, ID_AA64MMFR3, t); --=20 2.43.0