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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-45b79799c33sm28691015e9.5.2025.08.28.04.34.36 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Aug 2025 04:34:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756380878; x=1756985678; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to; bh=n8ApJz7RXENElQplzIs6M0aQR9sbG/YlsiM6m/0WkJo=; b=LnS3hImseAeeWbebIeo8Ya+eXsCxnCAw2LHHowXp12G+l1NLazr9obT2XILHcfXSO9 r90Hn7nSLLxGsStlOr2zt/63fX8N9+HAL3w0M8qCCLMdbr78OVGEl1F0uQyfMmUmSwfZ JUikKbuubqkEqtWBOqmeMciUuO8XLk1P8WDrKQoxDbCtlXav3UFtcmiQbm4Kiqm6jgBt p20Y5uvddKXPqTh9FzJi8VC1QjMdYUGYSdtMscm8siIH8gTUL2s23lwGJaYfDaQ0VsQp EI+38PstFg0Og1cVneil8rSslFIDnBSycpQcbZB1RBCILY1w6DH1XN3gsjJa5H4iviHn ZtCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756380878; x=1756985678; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=n8ApJz7RXENElQplzIs6M0aQR9sbG/YlsiM6m/0WkJo=; b=e3+2DVapr0NUcfq8ztYPdiiWSQ4pEhD28FRnoCcIYYtcCac9FplNojlXsSJPwV64R/ OeO8SXz3RrUoS/HBKLg1leNZUyoCqibtAPuNQhVlXLr02eWKxiH1ONKrqyIP1GVJA/OO aLyoRDMDKUryRMTCy5GxyTXf8UDWPtSGwBqxaR1qQKIt/hTXZ208aIL2IpZu0wn8d29n 11Kl0QnhJUBgN9hImlQix0T+OYVHgYgAPy3pouYuFfDPW2B1MFG0tEikPzdOSyp5iXtk Slyb/x51pXrglOKamWt91f8qVLRpMAyed+CbmqHe3bH50aVIfLNp87M50SERVWVsG5J8 dAEA== X-Gm-Message-State: AOJu0Yz9V0bT58cUSEdlYL3XCgyEwUSeB6Dp/QTsJz0WHSKPcnwhDoUY izOHcciIH2XLdhuRl9rWIj16UmJiLyMB48W1c6aB2O/DKL4VQf87smeeiZ8umSUFrhW66W51kRi Uw3oV X-Gm-Gg: ASbGnctthEDiI52a+uatZo18463gtU6PcaqmzqzA50hwi/AcmN61nqJeVl72Hiwd34A OpS2oE4BeUhMkiJxIFqlp8qJv44/K2WU9JtbV0bIELhFCnEAZvPwnmWHs9xqzT6IDbFVqtLtIEO FD8CkiOTnL9htWJuEiuQa1+CPj9nzCT7IZIZe0pKvPDyXp0q6XOSoiwRYY7HDkf6w0lPubnB9QN mf7rrPW392PWW3kXKOh5TdrgTB2dfrXu9O4WLsSZllWDLREpJTitnJrgguA709aoWbbP3/Lkrf3 8EULULfuMapm4WcSwN5yVszD2+U2lxQTZNNoaWSYvxUs88SPjet9hVU5oO/d9+2v+YxsaBK3m+m 26me9zr4b/cO83HhDyh0InzQJk14d5W9zTwrwIIs= X-Google-Smtp-Source: AGHT+IEOz2p7rnKKTgIHjEvc3sga9Wg98UY8v4VDDUiHfF3vep+6TPdHf9CjifvbpmQ4b0v+Rg6BAQ== X-Received: by 2002:a05:6000:310e:b0:3cd:16b0:dbad with SMTP id ffacd0b85a97d-3cd16b0de9emr3866444f8f.15.1756380877736; Thu, 28 Aug 2025 04:34:37 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/32] target/arm: Implement FEAT_SCTLR2 and enable with -cpu max Date: Thu, 28 Aug 2025 12:34:01 +0100 Message-ID: <20250828113430.3214314-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250828113430.3214314-1-peter.maydell@linaro.org> References: <20250828113430.3214314-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756381003196124100 Content-Type: text/plain; charset="utf-8" From: Gustavo Romero Add FEAT_SCTLR2, which introduces the SCTLR2_EL1, SCTLR2_EL2, and SCTLR2_EL3 registers. These registers are extensions of the SCTLR_ELx ones. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson Signed-off-by: Richard Henderson Message-id: 20250727074202.83141-4-richard.henderson@linaro.org Message-ID: <20250711140828.1714666-4-gustavo.romero@linaro.org> [rth: Remove FEAT_MEC code; handle SCR and HCRX enable bits.] Signed-off-by: Richard Henderson Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu-features.h | 5 ++ target/arm/cpu.h | 15 ++++++ target/arm/internals.h | 1 + target/arm/cpu.c | 3 ++ target/arm/helper.c | 97 ++++++++++++++++++++++++++++++++--- target/arm/tcg/cpu64.c | 5 +- 7 files changed, 119 insertions(+), 8 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 890dc6fee21..66043b0747a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -121,6 +121,7 @@ the following architecture extensions: - FEAT_RPRES (Increased precision of FRECPE and FRSQRTE) - FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) +- FEAT_SCTLR2 (Extension to SCTLR_ELx) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) - FEAT_SHA256 (SHA256 instructions) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index 5876162428a..e372543bf35 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -904,6 +904,11 @@ static inline bool isar_feature_aa64_nv2(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64MMFR2, NV) >=3D 2; } =20 +static inline bool isar_feature_aa64_sctlr2(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64MMFR3, SCTLRX) !=3D 0; +} + static inline bool isar_feature_aa64_pmuv3p1(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64DFR0, PMUVER) >=3D 4 && diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dc9b6dce4c9..08a29802e13 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -337,6 +337,7 @@ typedef struct CPUArchState { }; uint64_t sctlr_el[4]; }; + uint64_t sctlr2_el[4]; /* Extension to System control register. */ uint64_t vsctlr; /* Virtualization System control register. */ uint64_t cpacr_el1; /* Architectural feature access control regist= er */ uint64_t cptr_el[4]; /* ARMv8 feature trap registers */ @@ -1420,6 +1421,19 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 +#define SCTLR2_EMEC (1ULL << 1) /* FEAT_MEC */ +#define SCTLR2_NMEA (1ULL << 2) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENADERR (1ULL << 3) /* FEAT_ADERR */ +#define SCTLR2_ENANERR (1ULL << 4) /* FEAT_ANERR */ +#define SCTLR2_EASE (1ULL << 5) /* FEAT_DoubleFault2 */ +#define SCTLR2_ENIDCP128 (1ULL << 6) /* FEAT_SYSREG128 */ +#define SCTLR2_ENPACM (1ULL << 7) /* FEAT_PAuth_LR */ +#define SCTLR2_ENPACM0 (1ULL << 8) /* FEAT_PAuth_LR */ +#define SCTLR2_CPTA (1ULL << 9) /* FEAT_CPA2 */ +#define SCTLR2_CPTA0 (1ULL << 10) /* FEAT_CPA2 */ +#define SCTLR2_CPTM (1ULL << 11) /* FEAT_CPA2 */ +#define SCTLR2_CPTM0 (1ULL << 12) /* FEAT_CAP2 */ + #define CPSR_M (0x1fU) #define CPSR_T (1U << 5) #define CPSR_F (1U << 6) @@ -1712,6 +1726,7 @@ static inline void xpsr_write(CPUARMState *env, uint3= 2_t val, uint32_t mask) #define SCR_HXEN (1ULL << 38) #define SCR_TRNDR (1ULL << 40) #define SCR_ENTP2 (1ULL << 41) +#define SCR_SCTLR2EN (1ULL << 44) #define SCR_GPF (1ULL << 48) #define SCR_NSE (1ULL << 62) =20 diff --git a/target/arm/internals.h b/target/arm/internals.h index 3f86b070447..fb722362551 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -230,6 +230,7 @@ FIELD(VSTCR, SA, 30, 1) #define HCRX_CMOW (1ULL << 9) #define HCRX_MCE2 (1ULL << 10) #define HCRX_MSCEN (1ULL << 11) +#define HCRX_SCTLR2EN (1ULL << 15) =20 #define HPFAR_NS (1ULL << 63) =20 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e2b2337399c..2ab04cb5f7c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -644,6 +644,9 @@ void arm_emulate_firmware_reset(CPUState *cpustate, int= target_el) if (cpu_isar_feature(aa64_fgt, cpu)) { env->cp15.scr_el3 |=3D SCR_FGTEN; } + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + env->cp15.scr_el3 |=3D SCR_SCTLR2EN; + } } =20 if (target_el =3D=3D 2) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 0c1299ff841..11ddeabb132 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -741,6 +741,9 @@ static void scr_write(CPUARMState *env, const ARMCPRegI= nfo *ri, uint64_t value) if (cpu_isar_feature(aa64_ecv, cpu)) { valid_mask |=3D SCR_ECVEN; } + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + valid_mask |=3D SCR_SCTLR2EN; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -3907,23 +3910,21 @@ static void hcrx_write(CPUARMState *env, const ARMC= PRegInfo *ri, ARMCPU *cpu =3D env_archcpu(env); uint64_t valid_mask =3D 0; =20 - /* FEAT_MOPS adds MSCEn and MCE2 */ if (cpu_isar_feature(aa64_mops, cpu)) { valid_mask |=3D HCRX_MSCEN | HCRX_MCE2; } - - /* FEAT_NMI adds TALLINT, VINMI and VFNMI */ if (cpu_isar_feature(aa64_nmi, cpu)) { valid_mask |=3D HCRX_TALLINT | HCRX_VINMI | HCRX_VFNMI; } - /* FEAT_CMOW adds CMOW */ if (cpu_isar_feature(aa64_cmow, cpu)) { valid_mask |=3D HCRX_CMOW; } - /* FEAT_XS adds FGTnXS, FnXS */ if (cpu_isar_feature(aa64_xs, cpu)) { valid_mask |=3D HCRX_FGTNXS | HCRX_FNXS; } + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + valid_mask |=3D HCRX_SCTLR2EN; + } =20 /* Clear RES0 bits. */ env->cp15.hcrx_el2 =3D value & valid_mask; @@ -3981,11 +3982,16 @@ uint64_t arm_hcrx_el2_eff(CPUARMState *env) * This may need to be revisited for future bits. */ if (!arm_is_el2_enabled(env)) { + ARMCPU *cpu =3D env_archcpu(env); uint64_t hcrx =3D 0; - if (cpu_isar_feature(aa64_mops, env_archcpu(env))) { - /* MSCEn behaves as 1 if EL2 is not enabled */ + + /* Bits which whose effective value is 1 if el2 not enabled. */ + if (cpu_isar_feature(aa64_mops, cpu)) { hcrx |=3D HCRX_MSCEN; } + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + hcrx |=3D HCRX_SCTLR2EN; + } return hcrx; } if (arm_feature(env, ARM_FEATURE_EL3) && !(env->cp15.scr_el3 & SCR_HXE= N)) { @@ -4513,6 +4519,8 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), "SCTLR", "SCTLR_EL2", "SCTLR_EL12" }, + { K(3, 0, 1, 0, 3), K(3, 4, 1, 0, 3), K(3, 5, 1, 0, 3), + "SCTLR2_EL1", "SCTLR2_EL2", "SCTLR2_EL12", isar_feature_aa64_sct= lr2 }, { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), "CPACR", "CPTR_EL2", "CPACR_EL12" }, { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), @@ -5994,6 +6002,77 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .resetvalue =3D 0 }, }; =20 +static CPAccessResult sctlr2_el2_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_SCTLR2EN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static CPAccessResult sctlr2_el1_access(CPUARMState *env, + const ARMCPRegInfo *ri, + bool isread) +{ + CPAccessResult ret =3D access_tvm_trvm(env, ri, isread); + if (ret !=3D CP_ACCESS_OK) { + return ret; + } + if (arm_current_el(env) < 2 && !(arm_hcrx_el2_eff(env) & HCRX_SCTLR2EN= )) { + return CP_ACCESS_TRAP_EL2; + } + return sctlr2_el2_access(env, ri, isread); +} + +static void sctlr2_el1_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void sctlr2_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static void sctlr2_el3_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + value &=3D valid_mask; + raw_write(env, ri, value); +} + +static const ARMCPRegInfo sctlr2_reginfo[] =3D { + { .name =3D "SCTLR2_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL1_RW, .accessfn =3D sctlr2_el1_access, + .writefn =3D sctlr2_el1_write, .fgt =3D FGT_SCTLR_EL1, + .nv2_redirect_offset =3D 0x278 | NV2_REDIR_NV1, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[1]) }, + { .name =3D "SCTLR2_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL2_RW, .accessfn =3D sctlr2_el2_access, + .writefn =3D sctlr2_el2_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[2]) }, + { .name =3D "SCTLR2_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .opc2 =3D 3, .crn =3D 1, .crm =3D 0, + .access =3D PL3_RW, .writefn =3D sctlr2_el3_write, + .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr2_el[3]) }, +}; + void register_cp_regs_for_features(ARMCPU *cpu) { /* Register all the coprocessor registers based on feature bits */ @@ -7223,6 +7302,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, nmi_reginfo); } =20 + if (cpu_isar_feature(aa64_sctlr2, cpu)) { + define_arm_cp_regs(cpu, sctlr2_reginfo); + } + if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); } diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 35cddbafa4c..f4efff03a59 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -1247,7 +1247,10 @@ void aarch64_max_tcg_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, E0PD, 1); /* FEAT_E0PD */ SET_IDREG(isar, ID_AA64MMFR2, t); =20 - FIELD_DP64_IDREG(isar, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPE= C */ + t =3D GET_IDREG(isar, ID_AA64MMFR3); + t =3D FIELD_DP64(t, ID_AA64MMFR3, SCTLRX, 1); /* FEAT_SCTLR2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR3, SPEC_FPACC, 1); /* FEAT_FPACC_SPEC */ + SET_IDREG(isar, ID_AA64MMFR3, t); =20 t =3D GET_IDREG(isar, ID_AA64ZFR0); t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 2); /* FEAT_SVE2p1 */ --=20 2.43.0