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We must do these targets at the same time because of the ifdef dependency between TARGET_AARCH64 and TARGET_ARM. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- linux-user/aarch64/target_elf.h | 3 + linux-user/arm/target_elf.h | 3 + linux-user/arm/target_proc.h | 4 +- linux-user/loader.h | 10 +- linux-user/aarch64/elfload.c | 333 +++++++++++++++++++++ linux-user/arm/elfload.c | 161 ++++++++++ linux-user/elfload.c | 505 +------------------------------- 7 files changed, 510 insertions(+), 509 deletions(-) diff --git a/linux-user/aarch64/target_elf.h b/linux-user/aarch64/target_el= f.h index d955b3d07f..77108f3cb0 100644 --- a/linux-user/aarch64/target_elf.h +++ b/linux-user/aarch64/target_elf.h @@ -8,4 +8,7 @@ #ifndef AARCH64_TARGET_ELF_H #define AARCH64_TARGET_ELF_H =20 +#define HAVE_ELF_HWCAP 1 +#define HAVE_ELF_HWCAP2 1 + #endif diff --git a/linux-user/arm/target_elf.h b/linux-user/arm/target_elf.h index 2abb27a733..90470bd87b 100644 --- a/linux-user/arm/target_elf.h +++ b/linux-user/arm/target_elf.h @@ -8,4 +8,7 @@ #ifndef ARM_TARGET_ELF_H #define ARM_TARGET_ELF_H =20 +#define HAVE_ELF_HWCAP 1 +#define HAVE_ELF_HWCAP2 1 + #endif diff --git a/linux-user/arm/target_proc.h b/linux-user/arm/target_proc.h index ac75af9ca6..a4cd6948c6 100644 --- a/linux-user/arm/target_proc.h +++ b/linux-user/arm/target_proc.h @@ -10,8 +10,8 @@ static int open_cpuinfo(CPUArchState *cpu_env, int fd) { ARMCPU *cpu =3D env_archcpu(cpu_env); int arch, midr_rev, midr_part, midr_var, midr_impl; - target_ulong elf_hwcap =3D get_elf_hwcap(); - target_ulong elf_hwcap2 =3D get_elf_hwcap2(); + target_ulong elf_hwcap =3D get_elf_hwcap(env_cpu(cpu_env)); + target_ulong elf_hwcap2 =3D get_elf_hwcap2(env_cpu(cpu_env)); const char *elf_name; int num_cpus, len_part, len_var; =20 diff --git a/linux-user/loader.h b/linux-user/loader.h index 457bb36daa..151a06f5db 100644 --- a/linux-user/loader.h +++ b/linux-user/loader.h @@ -101,16 +101,14 @@ extern unsigned long guest_stack_size; /* Note that Elf32 and Elf64 use uint32_t for e_flags. */ const char *get_elf_cpu_model(uint32_t eflags); =20 -#if defined(TARGET_I386) || defined(TARGET_X86_64) +#if defined(TARGET_I386) || defined(TARGET_X86_64) || defined(TARGET_ARM) abi_ulong get_elf_hwcap(CPUState *cs); +abi_ulong get_elf_hwcap2(CPUState *cs); #endif -#if defined(TARGET_S390X) || defined(TARGET_AARCH64) || defined(TARGET_ARM) +#if defined(TARGET_S390X) uint32_t get_elf_hwcap(void); +#endif const char *elf_hwcap_str(uint32_t bit); -#endif -#if defined(TARGET_AARCH64) || defined(TARGET_ARM) -uint64_t get_elf_hwcap2(void); const char *elf_hwcap2_str(uint32_t bit); -#endif =20 #endif /* LINUX_USER_LOADER_H */ diff --git a/linux-user/aarch64/elfload.c b/linux-user/aarch64/elfload.c index b92442dfeb..92c8ea62c6 100644 --- a/linux-user/aarch64/elfload.c +++ b/linux-user/aarch64/elfload.c @@ -3,9 +3,342 @@ #include "qemu/osdep.h" #include "qemu.h" #include "loader.h" +#include "target/arm/cpu-features.h" =20 =20 const char *get_elf_cpu_model(uint32_t eflags) { return "any"; } + +enum { + ARM_HWCAP_A64_FP =3D 1 << 0, + ARM_HWCAP_A64_ASIMD =3D 1 << 1, + ARM_HWCAP_A64_EVTSTRM =3D 1 << 2, + ARM_HWCAP_A64_AES =3D 1 << 3, + ARM_HWCAP_A64_PMULL =3D 1 << 4, + ARM_HWCAP_A64_SHA1 =3D 1 << 5, + ARM_HWCAP_A64_SHA2 =3D 1 << 6, + ARM_HWCAP_A64_CRC32 =3D 1 << 7, + ARM_HWCAP_A64_ATOMICS =3D 1 << 8, + ARM_HWCAP_A64_FPHP =3D 1 << 9, + ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, + ARM_HWCAP_A64_CPUID =3D 1 << 11, + ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, + ARM_HWCAP_A64_JSCVT =3D 1 << 13, + ARM_HWCAP_A64_FCMA =3D 1 << 14, + ARM_HWCAP_A64_LRCPC =3D 1 << 15, + ARM_HWCAP_A64_DCPOP =3D 1 << 16, + ARM_HWCAP_A64_SHA3 =3D 1 << 17, + ARM_HWCAP_A64_SM3 =3D 1 << 18, + ARM_HWCAP_A64_SM4 =3D 1 << 19, + ARM_HWCAP_A64_ASIMDDP =3D 1 << 20, + ARM_HWCAP_A64_SHA512 =3D 1 << 21, + ARM_HWCAP_A64_SVE =3D 1 << 22, + ARM_HWCAP_A64_ASIMDFHM =3D 1 << 23, + ARM_HWCAP_A64_DIT =3D 1 << 24, + ARM_HWCAP_A64_USCAT =3D 1 << 25, + ARM_HWCAP_A64_ILRCPC =3D 1 << 26, + ARM_HWCAP_A64_FLAGM =3D 1 << 27, + ARM_HWCAP_A64_SSBS =3D 1 << 28, + ARM_HWCAP_A64_SB =3D 1 << 29, + ARM_HWCAP_A64_PACA =3D 1 << 30, + ARM_HWCAP_A64_PACG =3D 1ULL << 31, + ARM_HWCAP_A64_GCS =3D 1ULL << 32, + ARM_HWCAP_A64_CMPBR =3D 1ULL << 33, + ARM_HWCAP_A64_FPRCVT =3D 1ULL << 34, + ARM_HWCAP_A64_F8MM8 =3D 1ULL << 35, + ARM_HWCAP_A64_F8MM4 =3D 1ULL << 36, + ARM_HWCAP_A64_SVE_F16MM =3D 1ULL << 37, + ARM_HWCAP_A64_SVE_ELTPERM =3D 1ULL << 38, + ARM_HWCAP_A64_SVE_AES2 =3D 1ULL << 39, + ARM_HWCAP_A64_SVE_BFSCALE =3D 1ULL << 40, + ARM_HWCAP_A64_SVE2P2 =3D 1ULL << 41, + ARM_HWCAP_A64_SME2P2 =3D 1ULL << 42, + ARM_HWCAP_A64_SME_SBITPERM =3D 1ULL << 43, + ARM_HWCAP_A64_SME_AES =3D 1ULL << 44, + ARM_HWCAP_A64_SME_SFEXPA =3D 1ULL << 45, + ARM_HWCAP_A64_SME_STMOP =3D 1ULL << 46, + ARM_HWCAP_A64_SME_SMOP4 =3D 1ULL << 47, + + ARM_HWCAP2_A64_DCPODP =3D 1 << 0, + ARM_HWCAP2_A64_SVE2 =3D 1 << 1, + ARM_HWCAP2_A64_SVEAES =3D 1 << 2, + ARM_HWCAP2_A64_SVEPMULL =3D 1 << 3, + ARM_HWCAP2_A64_SVEBITPERM =3D 1 << 4, + ARM_HWCAP2_A64_SVESHA3 =3D 1 << 5, + ARM_HWCAP2_A64_SVESM4 =3D 1 << 6, + ARM_HWCAP2_A64_FLAGM2 =3D 1 << 7, + ARM_HWCAP2_A64_FRINT =3D 1 << 8, + ARM_HWCAP2_A64_SVEI8MM =3D 1 << 9, + ARM_HWCAP2_A64_SVEF32MM =3D 1 << 10, + ARM_HWCAP2_A64_SVEF64MM =3D 1 << 11, + ARM_HWCAP2_A64_SVEBF16 =3D 1 << 12, + ARM_HWCAP2_A64_I8MM =3D 1 << 13, + ARM_HWCAP2_A64_BF16 =3D 1 << 14, + ARM_HWCAP2_A64_DGH =3D 1 << 15, + ARM_HWCAP2_A64_RNG =3D 1 << 16, + ARM_HWCAP2_A64_BTI =3D 1 << 17, + ARM_HWCAP2_A64_MTE =3D 1 << 18, + ARM_HWCAP2_A64_ECV =3D 1 << 19, + ARM_HWCAP2_A64_AFP =3D 1 << 20, + ARM_HWCAP2_A64_RPRES =3D 1 << 21, + ARM_HWCAP2_A64_MTE3 =3D 1 << 22, + ARM_HWCAP2_A64_SME =3D 1 << 23, + ARM_HWCAP2_A64_SME_I16I64 =3D 1 << 24, + ARM_HWCAP2_A64_SME_F64F64 =3D 1 << 25, + ARM_HWCAP2_A64_SME_I8I32 =3D 1 << 26, + ARM_HWCAP2_A64_SME_F16F32 =3D 1 << 27, + ARM_HWCAP2_A64_SME_B16F32 =3D 1 << 28, + ARM_HWCAP2_A64_SME_F32F32 =3D 1 << 29, + ARM_HWCAP2_A64_SME_FA64 =3D 1 << 30, + ARM_HWCAP2_A64_WFXT =3D 1ULL << 31, + ARM_HWCAP2_A64_EBF16 =3D 1ULL << 32, + ARM_HWCAP2_A64_SVE_EBF16 =3D 1ULL << 33, + ARM_HWCAP2_A64_CSSC =3D 1ULL << 34, + ARM_HWCAP2_A64_RPRFM =3D 1ULL << 35, + ARM_HWCAP2_A64_SVE2P1 =3D 1ULL << 36, + ARM_HWCAP2_A64_SME2 =3D 1ULL << 37, + ARM_HWCAP2_A64_SME2P1 =3D 1ULL << 38, + ARM_HWCAP2_A64_SME_I16I32 =3D 1ULL << 39, + ARM_HWCAP2_A64_SME_BI32I32 =3D 1ULL << 40, + ARM_HWCAP2_A64_SME_B16B16 =3D 1ULL << 41, + ARM_HWCAP2_A64_SME_F16F16 =3D 1ULL << 42, + ARM_HWCAP2_A64_MOPS =3D 1ULL << 43, + ARM_HWCAP2_A64_HBC =3D 1ULL << 44, + ARM_HWCAP2_A64_SVE_B16B16 =3D 1ULL << 45, + ARM_HWCAP2_A64_LRCPC3 =3D 1ULL << 46, + ARM_HWCAP2_A64_LSE128 =3D 1ULL << 47, + ARM_HWCAP2_A64_FPMR =3D 1ULL << 48, + ARM_HWCAP2_A64_LUT =3D 1ULL << 49, + ARM_HWCAP2_A64_FAMINMAX =3D 1ULL << 50, + ARM_HWCAP2_A64_F8CVT =3D 1ULL << 51, + ARM_HWCAP2_A64_F8FMA =3D 1ULL << 52, + ARM_HWCAP2_A64_F8DP4 =3D 1ULL << 53, + ARM_HWCAP2_A64_F8DP2 =3D 1ULL << 54, + ARM_HWCAP2_A64_F8E4M3 =3D 1ULL << 55, + ARM_HWCAP2_A64_F8E5M2 =3D 1ULL << 56, + ARM_HWCAP2_A64_SME_LUTV2 =3D 1ULL << 57, + ARM_HWCAP2_A64_SME_F8F16 =3D 1ULL << 58, + ARM_HWCAP2_A64_SME_F8F32 =3D 1ULL << 59, + ARM_HWCAP2_A64_SME_SF8FMA =3D 1ULL << 60, + ARM_HWCAP2_A64_SME_SF8DP4 =3D 1ULL << 61, + ARM_HWCAP2_A64_SME_SF8DP2 =3D 1ULL << 62, + ARM_HWCAP2_A64_POE =3D 1ULL << 63, +}; + +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) + +abi_ulong get_elf_hwcap(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + abi_ulong hwcaps =3D 0; + + hwcaps |=3D ARM_HWCAP_A64_FP; + hwcaps |=3D ARM_HWCAP_A64_ASIMD; + hwcaps |=3D ARM_HWCAP_A64_CPUID; + + /* probe for the extra features */ + + GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES); + GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL); + GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1); + GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2); + GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512); + GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32); + GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3); + GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3); + GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4); + GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); + GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS); + GET_FEATURE_ID(aa64_lse2, ARM_HWCAP_A64_USCAT); + GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM); + GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP); + GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); + GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); + GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); + GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); + GET_FEATURE_ID(aa64_dit, ARM_HWCAP_A64_DIT); + GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); + GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); + GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); + GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); + GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); + GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); + + return hwcaps; +} + +abi_ulong get_elf_hwcap2(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + abi_ulong hwcaps =3D 0; + + GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); + GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); + GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES); + GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL); + GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); + GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); + GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); + GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); + GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); + GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); + GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM); + GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM); + GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16); + GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM); + GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16); + GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); + GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); + GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); + GET_FEATURE_ID(aa64_mte3, ARM_HWCAP2_A64_MTE3); + GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | + ARM_HWCAP2_A64_SME_F32F32 | + ARM_HWCAP2_A64_SME_B16F32 | + ARM_HWCAP2_A64_SME_F16F32 | + ARM_HWCAP2_A64_SME_I8I32)); + GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); + GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); + GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); + GET_FEATURE_ID(aa64_hbc, ARM_HWCAP2_A64_HBC); + GET_FEATURE_ID(aa64_mops, ARM_HWCAP2_A64_MOPS); + GET_FEATURE_ID(aa64_sve2p1, ARM_HWCAP2_A64_SVE2P1); + GET_FEATURE_ID(aa64_sme2, (ARM_HWCAP2_A64_SME2 | + ARM_HWCAP2_A64_SME_I16I32 | + ARM_HWCAP2_A64_SME_BI32I32)); + GET_FEATURE_ID(aa64_sme2p1, ARM_HWCAP2_A64_SME2P1); + GET_FEATURE_ID(aa64_sme_b16b16, ARM_HWCAP2_A64_SME_B16B16); + GET_FEATURE_ID(aa64_sme_f16f16, ARM_HWCAP2_A64_SME_F16F16); + GET_FEATURE_ID(aa64_sve_b16b16, ARM_HWCAP2_A64_SVE_B16B16); + + return hwcaps; +} + +const char *elf_hwcap_str(uint32_t bit) +{ + static const char * const hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP_A64_FP )] =3D "fp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMD )] =3D "asimd", + [__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] =3D "evtstrm", + [__builtin_ctz(ARM_HWCAP_A64_AES )] =3D "aes", + [__builtin_ctz(ARM_HWCAP_A64_PMULL )] =3D "pmull", + [__builtin_ctz(ARM_HWCAP_A64_SHA1 )] =3D "sha1", + [__builtin_ctz(ARM_HWCAP_A64_SHA2 )] =3D "sha2", + [__builtin_ctz(ARM_HWCAP_A64_CRC32 )] =3D "crc32", + [__builtin_ctz(ARM_HWCAP_A64_ATOMICS )] =3D "atomics", + [__builtin_ctz(ARM_HWCAP_A64_FPHP )] =3D "fphp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDHP )] =3D "asimdhp", + [__builtin_ctz(ARM_HWCAP_A64_CPUID )] =3D "cpuid", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDRDM)] =3D "asimdrdm", + [__builtin_ctz(ARM_HWCAP_A64_JSCVT )] =3D "jscvt", + [__builtin_ctz(ARM_HWCAP_A64_FCMA )] =3D "fcma", + [__builtin_ctz(ARM_HWCAP_A64_LRCPC )] =3D "lrcpc", + [__builtin_ctz(ARM_HWCAP_A64_DCPOP )] =3D "dcpop", + [__builtin_ctz(ARM_HWCAP_A64_SHA3 )] =3D "sha3", + [__builtin_ctz(ARM_HWCAP_A64_SM3 )] =3D "sm3", + [__builtin_ctz(ARM_HWCAP_A64_SM4 )] =3D "sm4", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDDP )] =3D "asimddp", + [__builtin_ctz(ARM_HWCAP_A64_SHA512 )] =3D "sha512", + [__builtin_ctz(ARM_HWCAP_A64_SVE )] =3D "sve", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDFHM)] =3D "asimdfhm", + [__builtin_ctz(ARM_HWCAP_A64_DIT )] =3D "dit", + [__builtin_ctz(ARM_HWCAP_A64_USCAT )] =3D "uscat", + [__builtin_ctz(ARM_HWCAP_A64_ILRCPC )] =3D "ilrcpc", + [__builtin_ctz(ARM_HWCAP_A64_FLAGM )] =3D "flagm", + [__builtin_ctz(ARM_HWCAP_A64_SSBS )] =3D "ssbs", + [__builtin_ctz(ARM_HWCAP_A64_SB )] =3D "sb", + [__builtin_ctz(ARM_HWCAP_A64_PACA )] =3D "paca", + [__builtin_ctz(ARM_HWCAP_A64_PACG )] =3D "pacg", + [__builtin_ctzll(ARM_HWCAP_A64_GCS )] =3D "gcs", + [__builtin_ctzll(ARM_HWCAP_A64_CMPBR )] =3D "cmpbr", + [__builtin_ctzll(ARM_HWCAP_A64_FPRCVT)] =3D "fprcvt", + [__builtin_ctzll(ARM_HWCAP_A64_F8MM8 )] =3D "f8mm8", + [__builtin_ctzll(ARM_HWCAP_A64_F8MM4 )] =3D "f8mm4", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_F16MM)] =3D "svef16mm", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_ELTPERM)] =3D "sveeltperm", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_AES2)] =3D "sveaes2", + [__builtin_ctzll(ARM_HWCAP_A64_SVE_BFSCALE)] =3D "svebfscale", + [__builtin_ctzll(ARM_HWCAP_A64_SVE2P2)] =3D "sve2p2", + [__builtin_ctzll(ARM_HWCAP_A64_SME2P2)] =3D "sme2p2", + [__builtin_ctzll(ARM_HWCAP_A64_SME_SBITPERM)] =3D "smesbitperm", + [__builtin_ctzll(ARM_HWCAP_A64_SME_AES)] =3D "smeaes", + [__builtin_ctzll(ARM_HWCAP_A64_SME_SFEXPA)] =3D "smesfexpa", + [__builtin_ctzll(ARM_HWCAP_A64_SME_STMOP)] =3D "smestmop", + [__builtin_ctzll(ARM_HWCAP_A64_SME_SMOP4)] =3D "smesmop4", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char * const hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] =3D "dcpodp", + [__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] =3D "sve2", + [__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] =3D "sveaes", + [__builtin_ctz(ARM_HWCAP2_A64_SVEPMULL )] =3D "svepmull", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBITPERM )] =3D "svebitperm", + [__builtin_ctz(ARM_HWCAP2_A64_SVESHA3 )] =3D "svesha3", + [__builtin_ctz(ARM_HWCAP2_A64_SVESM4 )] =3D "svesm4", + [__builtin_ctz(ARM_HWCAP2_A64_FLAGM2 )] =3D "flagm2", + [__builtin_ctz(ARM_HWCAP2_A64_FRINT )] =3D "frint", + [__builtin_ctz(ARM_HWCAP2_A64_SVEI8MM )] =3D "svei8mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF32MM )] =3D "svef32mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF64MM )] =3D "svef64mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBF16 )] =3D "svebf16", + [__builtin_ctz(ARM_HWCAP2_A64_I8MM )] =3D "i8mm", + [__builtin_ctz(ARM_HWCAP2_A64_BF16 )] =3D "bf16", + [__builtin_ctz(ARM_HWCAP2_A64_DGH )] =3D "dgh", + [__builtin_ctz(ARM_HWCAP2_A64_RNG )] =3D "rng", + [__builtin_ctz(ARM_HWCAP2_A64_BTI )] =3D "bti", + [__builtin_ctz(ARM_HWCAP2_A64_MTE )] =3D "mte", + [__builtin_ctz(ARM_HWCAP2_A64_ECV )] =3D "ecv", + [__builtin_ctz(ARM_HWCAP2_A64_AFP )] =3D "afp", + [__builtin_ctz(ARM_HWCAP2_A64_RPRES )] =3D "rpres", + [__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] =3D "mte3", + [__builtin_ctz(ARM_HWCAP2_A64_SME )] =3D "sme", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] =3D "smei16i64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] =3D "smef64f64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] =3D "smei8i32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] =3D "smef16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] =3D "smeb16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] =3D "smef32f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] =3D "smefa64", + [__builtin_ctz(ARM_HWCAP2_A64_WFXT )] =3D "wfxt", + [__builtin_ctzll(ARM_HWCAP2_A64_EBF16 )] =3D "ebf16", + [__builtin_ctzll(ARM_HWCAP2_A64_SVE_EBF16 )] =3D "sveebf16", + [__builtin_ctzll(ARM_HWCAP2_A64_CSSC )] =3D "cssc", + [__builtin_ctzll(ARM_HWCAP2_A64_RPRFM )] =3D "rprfm", + [__builtin_ctzll(ARM_HWCAP2_A64_SVE2P1 )] =3D "sve2p1", + [__builtin_ctzll(ARM_HWCAP2_A64_SME2 )] =3D "sme2", + [__builtin_ctzll(ARM_HWCAP2_A64_SME2P1 )] =3D "sme2p1", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_I16I32 )] =3D "smei16i32", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_BI32I32)] =3D "smebi32i32", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_B16B16 )] =3D "smeb16b16", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] =3D "smef16f16", + [__builtin_ctzll(ARM_HWCAP2_A64_MOPS )] =3D "mops", + [__builtin_ctzll(ARM_HWCAP2_A64_HBC )] =3D "hbc", + [__builtin_ctzll(ARM_HWCAP2_A64_SVE_B16B16 )] =3D "sveb16b16", + [__builtin_ctzll(ARM_HWCAP2_A64_LRCPC3 )] =3D "lrcpc3", + [__builtin_ctzll(ARM_HWCAP2_A64_LSE128 )] =3D "lse128", + [__builtin_ctzll(ARM_HWCAP2_A64_FPMR )] =3D "fpmr", + [__builtin_ctzll(ARM_HWCAP2_A64_LUT )] =3D "lut", + [__builtin_ctzll(ARM_HWCAP2_A64_FAMINMAX )] =3D "faminmax", + [__builtin_ctzll(ARM_HWCAP2_A64_F8CVT )] =3D "f8cvt", + [__builtin_ctzll(ARM_HWCAP2_A64_F8FMA )] =3D "f8fma", + [__builtin_ctzll(ARM_HWCAP2_A64_F8DP4 )] =3D "f8dp4", + [__builtin_ctzll(ARM_HWCAP2_A64_F8DP2 )] =3D "f8dp2", + [__builtin_ctzll(ARM_HWCAP2_A64_F8E4M3 )] =3D "f8e4m3", + [__builtin_ctzll(ARM_HWCAP2_A64_F8E5M2 )] =3D "f8e5m2", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_LUTV2 )] =3D "smelutv2", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F16 )] =3D "smef8f16", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F32 )] =3D "smef8f32", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP4 )] =3D "smesf8dp4", + [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP2 )] =3D "smesf8dp2", + [__builtin_ctzll(ARM_HWCAP2_A64_POE )] =3D "poe", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} diff --git a/linux-user/arm/elfload.c b/linux-user/arm/elfload.c index b92442dfeb..c7561b005b 100644 --- a/linux-user/arm/elfload.c +++ b/linux-user/arm/elfload.c @@ -3,9 +3,170 @@ #include "qemu/osdep.h" #include "qemu.h" #include "loader.h" +#include "target/arm/cpu-features.h" =20 =20 const char *get_elf_cpu_model(uint32_t eflags) { return "any"; } + +enum +{ + ARM_HWCAP_ARM_SWP =3D 1 << 0, + ARM_HWCAP_ARM_HALF =3D 1 << 1, + ARM_HWCAP_ARM_THUMB =3D 1 << 2, + ARM_HWCAP_ARM_26BIT =3D 1 << 3, + ARM_HWCAP_ARM_FAST_MULT =3D 1 << 4, + ARM_HWCAP_ARM_FPA =3D 1 << 5, + ARM_HWCAP_ARM_VFP =3D 1 << 6, + ARM_HWCAP_ARM_EDSP =3D 1 << 7, + ARM_HWCAP_ARM_JAVA =3D 1 << 8, + ARM_HWCAP_ARM_IWMMXT =3D 1 << 9, + ARM_HWCAP_ARM_CRUNCH =3D 1 << 10, + ARM_HWCAP_ARM_THUMBEE =3D 1 << 11, + ARM_HWCAP_ARM_NEON =3D 1 << 12, + ARM_HWCAP_ARM_VFPv3 =3D 1 << 13, + ARM_HWCAP_ARM_VFPv3D16 =3D 1 << 14, + ARM_HWCAP_ARM_TLS =3D 1 << 15, + ARM_HWCAP_ARM_VFPv4 =3D 1 << 16, + ARM_HWCAP_ARM_IDIVA =3D 1 << 17, + ARM_HWCAP_ARM_IDIVT =3D 1 << 18, + ARM_HWCAP_ARM_VFPD32 =3D 1 << 19, + ARM_HWCAP_ARM_LPAE =3D 1 << 20, + ARM_HWCAP_ARM_EVTSTRM =3D 1 << 21, + ARM_HWCAP_ARM_FPHP =3D 1 << 22, + ARM_HWCAP_ARM_ASIMDHP =3D 1 << 23, + ARM_HWCAP_ARM_ASIMDDP =3D 1 << 24, + ARM_HWCAP_ARM_ASIMDFHM =3D 1 << 25, + ARM_HWCAP_ARM_ASIMDBF16 =3D 1 << 26, + ARM_HWCAP_ARM_I8MM =3D 1 << 27, +}; + +enum { + ARM_HWCAP2_ARM_AES =3D 1 << 0, + ARM_HWCAP2_ARM_PMULL =3D 1 << 1, + ARM_HWCAP2_ARM_SHA1 =3D 1 << 2, + ARM_HWCAP2_ARM_SHA2 =3D 1 << 3, + ARM_HWCAP2_ARM_CRC32 =3D 1 << 4, + ARM_HWCAP2_ARM_SB =3D 1 << 5, + ARM_HWCAP2_ARM_SSBS =3D 1 << 6, +}; + +abi_ulong get_elf_hwcap(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + abi_ulong hwcaps =3D 0; + + hwcaps |=3D ARM_HWCAP_ARM_SWP; + hwcaps |=3D ARM_HWCAP_ARM_HALF; + hwcaps |=3D ARM_HWCAP_ARM_THUMB; + hwcaps |=3D ARM_HWCAP_ARM_FAST_MULT; + + /* probe for the extra features */ +#define GET_FEATURE(feat, hwcap) \ + do { if (arm_feature(&cpu->env, feat)) { hwcaps |=3D hwcap; } } while = (0) + +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) + + /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ + GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); + GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); + GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); + GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); + GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); + GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); + GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); + GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); + GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP); + + if (cpu_isar_feature(aa32_fpsp_v3, cpu) || + cpu_isar_feature(aa32_fpdp_v3, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3; + if (cpu_isar_feature(aa32_simd_r32, cpu)) { + hwcaps |=3D ARM_HWCAP_ARM_VFPD32; + } else { + hwcaps |=3D ARM_HWCAP_ARM_VFPv3D16; + } + } + GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); + /* + * MVFR1.FPHP and .SIMDHP must be in sync, and QEMU uses the same + * isar_feature function for both. The kernel reports them as two hwca= ps. + */ + GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_FPHP); + GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_ASIMDHP); + GET_FEATURE_ID(aa32_dp, ARM_HWCAP_ARM_ASIMDDP); + GET_FEATURE_ID(aa32_fhm, ARM_HWCAP_ARM_ASIMDFHM); + GET_FEATURE_ID(aa32_bf16, ARM_HWCAP_ARM_ASIMDBF16); + GET_FEATURE_ID(aa32_i8mm, ARM_HWCAP_ARM_I8MM); + + return hwcaps; +} + +abi_ulong get_elf_hwcap2(CPUState *cs) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + abi_ulong hwcaps =3D 0; + + GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES); + GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL); + GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1); + GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2); + GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32); + GET_FEATURE_ID(aa32_sb, ARM_HWCAP2_ARM_SB); + GET_FEATURE_ID(aa32_ssbs, ARM_HWCAP2_ARM_SSBS); + return hwcaps; +} + +const char *elf_hwcap_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP_ARM_SWP )] =3D "swp", + [__builtin_ctz(ARM_HWCAP_ARM_HALF )] =3D "half", + [__builtin_ctz(ARM_HWCAP_ARM_THUMB )] =3D "thumb", + [__builtin_ctz(ARM_HWCAP_ARM_26BIT )] =3D "26bit", + [__builtin_ctz(ARM_HWCAP_ARM_FAST_MULT)] =3D "fast_mult", + [__builtin_ctz(ARM_HWCAP_ARM_FPA )] =3D "fpa", + [__builtin_ctz(ARM_HWCAP_ARM_VFP )] =3D "vfp", + [__builtin_ctz(ARM_HWCAP_ARM_EDSP )] =3D "edsp", + [__builtin_ctz(ARM_HWCAP_ARM_JAVA )] =3D "java", + [__builtin_ctz(ARM_HWCAP_ARM_IWMMXT )] =3D "iwmmxt", + [__builtin_ctz(ARM_HWCAP_ARM_CRUNCH )] =3D "crunch", + [__builtin_ctz(ARM_HWCAP_ARM_THUMBEE )] =3D "thumbee", + [__builtin_ctz(ARM_HWCAP_ARM_NEON )] =3D "neon", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3 )] =3D "vfpv3", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3D16 )] =3D "vfpv3d16", + [__builtin_ctz(ARM_HWCAP_ARM_TLS )] =3D "tls", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv4 )] =3D "vfpv4", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVA )] =3D "idiva", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVT )] =3D "idivt", + [__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] =3D "vfpd32", + [__builtin_ctz(ARM_HWCAP_ARM_LPAE )] =3D "lpae", + [__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] =3D "evtstrm", + [__builtin_ctz(ARM_HWCAP_ARM_FPHP )] =3D "fphp", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDHP )] =3D "asimdhp", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDDP )] =3D "asimddp", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDFHM )] =3D "asimdfhm", + [__builtin_ctz(ARM_HWCAP_ARM_ASIMDBF16)] =3D "asimdbf16", + [__builtin_ctz(ARM_HWCAP_ARM_I8MM )] =3D "i8mm", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char *hwcap_str[] =3D { + [__builtin_ctz(ARM_HWCAP2_ARM_AES )] =3D "aes", + [__builtin_ctz(ARM_HWCAP2_ARM_PMULL)] =3D "pmull", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] =3D "sha1", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] =3D "sha2", + [__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] =3D "crc32", + [__builtin_ctz(ARM_HWCAP2_ARM_SB )] =3D "sb", + [__builtin_ctz(ARM_HWCAP2_ARM_SSBS )] =3D "ssbs", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 0c62c249e9..149d1313c0 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -401,48 +401,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *r= egs, const CPUARMState *en #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 =20 -enum -{ - ARM_HWCAP_ARM_SWP =3D 1 << 0, - ARM_HWCAP_ARM_HALF =3D 1 << 1, - ARM_HWCAP_ARM_THUMB =3D 1 << 2, - ARM_HWCAP_ARM_26BIT =3D 1 << 3, - ARM_HWCAP_ARM_FAST_MULT =3D 1 << 4, - ARM_HWCAP_ARM_FPA =3D 1 << 5, - ARM_HWCAP_ARM_VFP =3D 1 << 6, - ARM_HWCAP_ARM_EDSP =3D 1 << 7, - ARM_HWCAP_ARM_JAVA =3D 1 << 8, - ARM_HWCAP_ARM_IWMMXT =3D 1 << 9, - ARM_HWCAP_ARM_CRUNCH =3D 1 << 10, - ARM_HWCAP_ARM_THUMBEE =3D 1 << 11, - ARM_HWCAP_ARM_NEON =3D 1 << 12, - ARM_HWCAP_ARM_VFPv3 =3D 1 << 13, - ARM_HWCAP_ARM_VFPv3D16 =3D 1 << 14, - ARM_HWCAP_ARM_TLS =3D 1 << 15, - ARM_HWCAP_ARM_VFPv4 =3D 1 << 16, - ARM_HWCAP_ARM_IDIVA =3D 1 << 17, - ARM_HWCAP_ARM_IDIVT =3D 1 << 18, - ARM_HWCAP_ARM_VFPD32 =3D 1 << 19, - ARM_HWCAP_ARM_LPAE =3D 1 << 20, - ARM_HWCAP_ARM_EVTSTRM =3D 1 << 21, - ARM_HWCAP_ARM_FPHP =3D 1 << 22, - ARM_HWCAP_ARM_ASIMDHP =3D 1 << 23, - ARM_HWCAP_ARM_ASIMDDP =3D 1 << 24, - ARM_HWCAP_ARM_ASIMDFHM =3D 1 << 25, - ARM_HWCAP_ARM_ASIMDBF16 =3D 1 << 26, - ARM_HWCAP_ARM_I8MM =3D 1 << 27, -}; - -enum { - ARM_HWCAP2_ARM_AES =3D 1 << 0, - ARM_HWCAP2_ARM_PMULL =3D 1 << 1, - ARM_HWCAP2_ARM_SHA1 =3D 1 << 2, - ARM_HWCAP2_ARM_SHA2 =3D 1 << 3, - ARM_HWCAP2_ARM_CRC32 =3D 1 << 4, - ARM_HWCAP2_ARM_SB =3D 1 << 5, - ARM_HWCAP2_ARM_SSBS =3D 1 << 6, -}; - /* The commpage only exists for 32 bit kernels */ =20 #define HI_COMMPAGE (intptr_t)0xffff0f00u @@ -491,129 +449,8 @@ static bool init_guest_commpage(void) return true; } =20 -#define ELF_HWCAP get_elf_hwcap() -#define ELF_HWCAP2 get_elf_hwcap2() - -uint32_t get_elf_hwcap(void) -{ - ARMCPU *cpu =3D ARM_CPU(thread_cpu); - uint32_t hwcaps =3D 0; - - hwcaps |=3D ARM_HWCAP_ARM_SWP; - hwcaps |=3D ARM_HWCAP_ARM_HALF; - hwcaps |=3D ARM_HWCAP_ARM_THUMB; - hwcaps |=3D ARM_HWCAP_ARM_FAST_MULT; - - /* probe for the extra features */ -#define GET_FEATURE(feat, hwcap) \ - do { if (arm_feature(&cpu->env, feat)) { hwcaps |=3D hwcap; } } while = (0) - -#define GET_FEATURE_ID(feat, hwcap) \ - do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) - - /* EDSP is in v5TE and above, but all our v5 CPUs are v5TE */ - GET_FEATURE(ARM_FEATURE_V5, ARM_HWCAP_ARM_EDSP); - GET_FEATURE(ARM_FEATURE_IWMMXT, ARM_HWCAP_ARM_IWMMXT); - GET_FEATURE(ARM_FEATURE_THUMB2EE, ARM_HWCAP_ARM_THUMBEE); - GET_FEATURE(ARM_FEATURE_NEON, ARM_HWCAP_ARM_NEON); - GET_FEATURE(ARM_FEATURE_V6K, ARM_HWCAP_ARM_TLS); - GET_FEATURE(ARM_FEATURE_LPAE, ARM_HWCAP_ARM_LPAE); - GET_FEATURE_ID(aa32_arm_div, ARM_HWCAP_ARM_IDIVA); - GET_FEATURE_ID(aa32_thumb_div, ARM_HWCAP_ARM_IDIVT); - GET_FEATURE_ID(aa32_vfp, ARM_HWCAP_ARM_VFP); - - if (cpu_isar_feature(aa32_fpsp_v3, cpu) || - cpu_isar_feature(aa32_fpdp_v3, cpu)) { - hwcaps |=3D ARM_HWCAP_ARM_VFPv3; - if (cpu_isar_feature(aa32_simd_r32, cpu)) { - hwcaps |=3D ARM_HWCAP_ARM_VFPD32; - } else { - hwcaps |=3D ARM_HWCAP_ARM_VFPv3D16; - } - } - GET_FEATURE_ID(aa32_simdfmac, ARM_HWCAP_ARM_VFPv4); - /* - * MVFR1.FPHP and .SIMDHP must be in sync, and QEMU uses the same - * isar_feature function for both. The kernel reports them as two hwca= ps. - */ - GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_FPHP); - GET_FEATURE_ID(aa32_fp16_arith, ARM_HWCAP_ARM_ASIMDHP); - GET_FEATURE_ID(aa32_dp, ARM_HWCAP_ARM_ASIMDDP); - GET_FEATURE_ID(aa32_fhm, ARM_HWCAP_ARM_ASIMDFHM); - GET_FEATURE_ID(aa32_bf16, ARM_HWCAP_ARM_ASIMDBF16); - GET_FEATURE_ID(aa32_i8mm, ARM_HWCAP_ARM_I8MM); - - return hwcaps; -} - -uint64_t get_elf_hwcap2(void) -{ - ARMCPU *cpu =3D ARM_CPU(thread_cpu); - uint64_t hwcaps =3D 0; - - GET_FEATURE_ID(aa32_aes, ARM_HWCAP2_ARM_AES); - GET_FEATURE_ID(aa32_pmull, ARM_HWCAP2_ARM_PMULL); - GET_FEATURE_ID(aa32_sha1, ARM_HWCAP2_ARM_SHA1); - GET_FEATURE_ID(aa32_sha2, ARM_HWCAP2_ARM_SHA2); - GET_FEATURE_ID(aa32_crc32, ARM_HWCAP2_ARM_CRC32); - GET_FEATURE_ID(aa32_sb, ARM_HWCAP2_ARM_SB); - GET_FEATURE_ID(aa32_ssbs, ARM_HWCAP2_ARM_SSBS); - return hwcaps; -} - -const char *elf_hwcap_str(uint32_t bit) -{ - static const char *hwcap_str[] =3D { - [__builtin_ctz(ARM_HWCAP_ARM_SWP )] =3D "swp", - [__builtin_ctz(ARM_HWCAP_ARM_HALF )] =3D "half", - [__builtin_ctz(ARM_HWCAP_ARM_THUMB )] =3D "thumb", - [__builtin_ctz(ARM_HWCAP_ARM_26BIT )] =3D "26bit", - [__builtin_ctz(ARM_HWCAP_ARM_FAST_MULT)] =3D "fast_mult", - [__builtin_ctz(ARM_HWCAP_ARM_FPA )] =3D "fpa", - [__builtin_ctz(ARM_HWCAP_ARM_VFP )] =3D "vfp", - [__builtin_ctz(ARM_HWCAP_ARM_EDSP )] =3D "edsp", - [__builtin_ctz(ARM_HWCAP_ARM_JAVA )] =3D "java", - [__builtin_ctz(ARM_HWCAP_ARM_IWMMXT )] =3D "iwmmxt", - [__builtin_ctz(ARM_HWCAP_ARM_CRUNCH )] =3D "crunch", - [__builtin_ctz(ARM_HWCAP_ARM_THUMBEE )] =3D "thumbee", - [__builtin_ctz(ARM_HWCAP_ARM_NEON )] =3D "neon", - [__builtin_ctz(ARM_HWCAP_ARM_VFPv3 )] =3D "vfpv3", - [__builtin_ctz(ARM_HWCAP_ARM_VFPv3D16 )] =3D "vfpv3d16", - [__builtin_ctz(ARM_HWCAP_ARM_TLS )] =3D "tls", - [__builtin_ctz(ARM_HWCAP_ARM_VFPv4 )] =3D "vfpv4", - [__builtin_ctz(ARM_HWCAP_ARM_IDIVA )] =3D "idiva", - [__builtin_ctz(ARM_HWCAP_ARM_IDIVT )] =3D "idivt", - [__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] =3D "vfpd32", - [__builtin_ctz(ARM_HWCAP_ARM_LPAE )] =3D "lpae", - [__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] =3D "evtstrm", - [__builtin_ctz(ARM_HWCAP_ARM_FPHP )] =3D "fphp", - [__builtin_ctz(ARM_HWCAP_ARM_ASIMDHP )] =3D "asimdhp", - [__builtin_ctz(ARM_HWCAP_ARM_ASIMDDP )] =3D "asimddp", - [__builtin_ctz(ARM_HWCAP_ARM_ASIMDFHM )] =3D "asimdfhm", - [__builtin_ctz(ARM_HWCAP_ARM_ASIMDBF16)] =3D "asimdbf16", - [__builtin_ctz(ARM_HWCAP_ARM_I8MM )] =3D "i8mm", - }; - - return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; -} - -const char *elf_hwcap2_str(uint32_t bit) -{ - static const char *hwcap_str[] =3D { - [__builtin_ctz(ARM_HWCAP2_ARM_AES )] =3D "aes", - [__builtin_ctz(ARM_HWCAP2_ARM_PMULL)] =3D "pmull", - [__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] =3D "sha1", - [__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] =3D "sha2", - [__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] =3D "crc32", - [__builtin_ctz(ARM_HWCAP2_ARM_SB )] =3D "sb", - [__builtin_ctz(ARM_HWCAP2_ARM_SSBS )] =3D "ssbs", - }; - - return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; -} - -#undef GET_FEATURE -#undef GET_FEATURE_ID +#define ELF_HWCAP get_elf_hwcap(thread_cpu) +#define ELF_HWCAP2 get_elf_hwcap2(thread_cpu) =20 #define ELF_PLATFORM get_elf_platform() =20 @@ -702,342 +539,8 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, #define USE_ELF_CORE_DUMP #define ELF_EXEC_PAGESIZE 4096 =20 -enum { - ARM_HWCAP_A64_FP =3D 1 << 0, - ARM_HWCAP_A64_ASIMD =3D 1 << 1, - ARM_HWCAP_A64_EVTSTRM =3D 1 << 2, - ARM_HWCAP_A64_AES =3D 1 << 3, - ARM_HWCAP_A64_PMULL =3D 1 << 4, - ARM_HWCAP_A64_SHA1 =3D 1 << 5, - ARM_HWCAP_A64_SHA2 =3D 1 << 6, - ARM_HWCAP_A64_CRC32 =3D 1 << 7, - ARM_HWCAP_A64_ATOMICS =3D 1 << 8, - ARM_HWCAP_A64_FPHP =3D 1 << 9, - ARM_HWCAP_A64_ASIMDHP =3D 1 << 10, - ARM_HWCAP_A64_CPUID =3D 1 << 11, - ARM_HWCAP_A64_ASIMDRDM =3D 1 << 12, - ARM_HWCAP_A64_JSCVT =3D 1 << 13, - ARM_HWCAP_A64_FCMA =3D 1 << 14, - ARM_HWCAP_A64_LRCPC =3D 1 << 15, - ARM_HWCAP_A64_DCPOP =3D 1 << 16, - ARM_HWCAP_A64_SHA3 =3D 1 << 17, - ARM_HWCAP_A64_SM3 =3D 1 << 18, - ARM_HWCAP_A64_SM4 =3D 1 << 19, - ARM_HWCAP_A64_ASIMDDP =3D 1 << 20, - ARM_HWCAP_A64_SHA512 =3D 1 << 21, - ARM_HWCAP_A64_SVE =3D 1 << 22, - ARM_HWCAP_A64_ASIMDFHM =3D 1 << 23, - ARM_HWCAP_A64_DIT =3D 1 << 24, - ARM_HWCAP_A64_USCAT =3D 1 << 25, - ARM_HWCAP_A64_ILRCPC =3D 1 << 26, - ARM_HWCAP_A64_FLAGM =3D 1 << 27, - ARM_HWCAP_A64_SSBS =3D 1 << 28, - ARM_HWCAP_A64_SB =3D 1 << 29, - ARM_HWCAP_A64_PACA =3D 1 << 30, - ARM_HWCAP_A64_PACG =3D 1ULL << 31, - ARM_HWCAP_A64_GCS =3D 1ULL << 32, - ARM_HWCAP_A64_CMPBR =3D 1ULL << 33, - ARM_HWCAP_A64_FPRCVT =3D 1ULL << 34, - ARM_HWCAP_A64_F8MM8 =3D 1ULL << 35, - ARM_HWCAP_A64_F8MM4 =3D 1ULL << 36, - ARM_HWCAP_A64_SVE_F16MM =3D 1ULL << 37, - ARM_HWCAP_A64_SVE_ELTPERM =3D 1ULL << 38, - ARM_HWCAP_A64_SVE_AES2 =3D 1ULL << 39, - ARM_HWCAP_A64_SVE_BFSCALE =3D 1ULL << 40, - ARM_HWCAP_A64_SVE2P2 =3D 1ULL << 41, - ARM_HWCAP_A64_SME2P2 =3D 1ULL << 42, - ARM_HWCAP_A64_SME_SBITPERM =3D 1ULL << 43, - ARM_HWCAP_A64_SME_AES =3D 1ULL << 44, - ARM_HWCAP_A64_SME_SFEXPA =3D 1ULL << 45, - ARM_HWCAP_A64_SME_STMOP =3D 1ULL << 46, - ARM_HWCAP_A64_SME_SMOP4 =3D 1ULL << 47, - - ARM_HWCAP2_A64_DCPODP =3D 1 << 0, - ARM_HWCAP2_A64_SVE2 =3D 1 << 1, - ARM_HWCAP2_A64_SVEAES =3D 1 << 2, - ARM_HWCAP2_A64_SVEPMULL =3D 1 << 3, - ARM_HWCAP2_A64_SVEBITPERM =3D 1 << 4, - ARM_HWCAP2_A64_SVESHA3 =3D 1 << 5, - ARM_HWCAP2_A64_SVESM4 =3D 1 << 6, - ARM_HWCAP2_A64_FLAGM2 =3D 1 << 7, - ARM_HWCAP2_A64_FRINT =3D 1 << 8, - ARM_HWCAP2_A64_SVEI8MM =3D 1 << 9, - ARM_HWCAP2_A64_SVEF32MM =3D 1 << 10, - ARM_HWCAP2_A64_SVEF64MM =3D 1 << 11, - ARM_HWCAP2_A64_SVEBF16 =3D 1 << 12, - ARM_HWCAP2_A64_I8MM =3D 1 << 13, - ARM_HWCAP2_A64_BF16 =3D 1 << 14, - ARM_HWCAP2_A64_DGH =3D 1 << 15, - ARM_HWCAP2_A64_RNG =3D 1 << 16, - ARM_HWCAP2_A64_BTI =3D 1 << 17, - ARM_HWCAP2_A64_MTE =3D 1 << 18, - ARM_HWCAP2_A64_ECV =3D 1 << 19, - ARM_HWCAP2_A64_AFP =3D 1 << 20, - ARM_HWCAP2_A64_RPRES =3D 1 << 21, - ARM_HWCAP2_A64_MTE3 =3D 1 << 22, - ARM_HWCAP2_A64_SME =3D 1 << 23, - ARM_HWCAP2_A64_SME_I16I64 =3D 1 << 24, - ARM_HWCAP2_A64_SME_F64F64 =3D 1 << 25, - ARM_HWCAP2_A64_SME_I8I32 =3D 1 << 26, - ARM_HWCAP2_A64_SME_F16F32 =3D 1 << 27, - ARM_HWCAP2_A64_SME_B16F32 =3D 1 << 28, - ARM_HWCAP2_A64_SME_F32F32 =3D 1 << 29, - ARM_HWCAP2_A64_SME_FA64 =3D 1 << 30, - ARM_HWCAP2_A64_WFXT =3D 1ULL << 31, - ARM_HWCAP2_A64_EBF16 =3D 1ULL << 32, - ARM_HWCAP2_A64_SVE_EBF16 =3D 1ULL << 33, - ARM_HWCAP2_A64_CSSC =3D 1ULL << 34, - ARM_HWCAP2_A64_RPRFM =3D 1ULL << 35, - ARM_HWCAP2_A64_SVE2P1 =3D 1ULL << 36, - ARM_HWCAP2_A64_SME2 =3D 1ULL << 37, - ARM_HWCAP2_A64_SME2P1 =3D 1ULL << 38, - ARM_HWCAP2_A64_SME_I16I32 =3D 1ULL << 39, - ARM_HWCAP2_A64_SME_BI32I32 =3D 1ULL << 40, - ARM_HWCAP2_A64_SME_B16B16 =3D 1ULL << 41, - ARM_HWCAP2_A64_SME_F16F16 =3D 1ULL << 42, - ARM_HWCAP2_A64_MOPS =3D 1ULL << 43, - ARM_HWCAP2_A64_HBC =3D 1ULL << 44, - ARM_HWCAP2_A64_SVE_B16B16 =3D 1ULL << 45, - ARM_HWCAP2_A64_LRCPC3 =3D 1ULL << 46, - ARM_HWCAP2_A64_LSE128 =3D 1ULL << 47, - ARM_HWCAP2_A64_FPMR =3D 1ULL << 48, - ARM_HWCAP2_A64_LUT =3D 1ULL << 49, - ARM_HWCAP2_A64_FAMINMAX =3D 1ULL << 50, - ARM_HWCAP2_A64_F8CVT =3D 1ULL << 51, - ARM_HWCAP2_A64_F8FMA =3D 1ULL << 52, - ARM_HWCAP2_A64_F8DP4 =3D 1ULL << 53, - ARM_HWCAP2_A64_F8DP2 =3D 1ULL << 54, - ARM_HWCAP2_A64_F8E4M3 =3D 1ULL << 55, - ARM_HWCAP2_A64_F8E5M2 =3D 1ULL << 56, - ARM_HWCAP2_A64_SME_LUTV2 =3D 1ULL << 57, - ARM_HWCAP2_A64_SME_F8F16 =3D 1ULL << 58, - ARM_HWCAP2_A64_SME_F8F32 =3D 1ULL << 59, - ARM_HWCAP2_A64_SME_SF8FMA =3D 1ULL << 60, - ARM_HWCAP2_A64_SME_SF8DP4 =3D 1ULL << 61, - ARM_HWCAP2_A64_SME_SF8DP2 =3D 1ULL << 62, - ARM_HWCAP2_A64_POE =3D 1ULL << 63, -}; - -#define ELF_HWCAP get_elf_hwcap() -#define ELF_HWCAP2 get_elf_hwcap2() - -#define GET_FEATURE_ID(feat, hwcap) \ - do { if (cpu_isar_feature(feat, cpu)) { hwcaps |=3D hwcap; } } while (= 0) - -uint32_t get_elf_hwcap(void) -{ - ARMCPU *cpu =3D ARM_CPU(thread_cpu); - uint32_t hwcaps =3D 0; - - hwcaps |=3D ARM_HWCAP_A64_FP; - hwcaps |=3D ARM_HWCAP_A64_ASIMD; - hwcaps |=3D ARM_HWCAP_A64_CPUID; - - /* probe for the extra features */ - - GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES); - GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL); - GET_FEATURE_ID(aa64_sha1, ARM_HWCAP_A64_SHA1); - GET_FEATURE_ID(aa64_sha256, ARM_HWCAP_A64_SHA2); - GET_FEATURE_ID(aa64_sha512, ARM_HWCAP_A64_SHA512); - GET_FEATURE_ID(aa64_crc32, ARM_HWCAP_A64_CRC32); - GET_FEATURE_ID(aa64_sha3, ARM_HWCAP_A64_SHA3); - GET_FEATURE_ID(aa64_sm3, ARM_HWCAP_A64_SM3); - GET_FEATURE_ID(aa64_sm4, ARM_HWCAP_A64_SM4); - GET_FEATURE_ID(aa64_fp16, ARM_HWCAP_A64_FPHP | ARM_HWCAP_A64_ASIMDHP); - GET_FEATURE_ID(aa64_atomics, ARM_HWCAP_A64_ATOMICS); - GET_FEATURE_ID(aa64_lse2, ARM_HWCAP_A64_USCAT); - GET_FEATURE_ID(aa64_rdm, ARM_HWCAP_A64_ASIMDRDM); - GET_FEATURE_ID(aa64_dp, ARM_HWCAP_A64_ASIMDDP); - GET_FEATURE_ID(aa64_fcma, ARM_HWCAP_A64_FCMA); - GET_FEATURE_ID(aa64_sve, ARM_HWCAP_A64_SVE); - GET_FEATURE_ID(aa64_pauth, ARM_HWCAP_A64_PACA | ARM_HWCAP_A64_PACG); - GET_FEATURE_ID(aa64_fhm, ARM_HWCAP_A64_ASIMDFHM); - GET_FEATURE_ID(aa64_dit, ARM_HWCAP_A64_DIT); - GET_FEATURE_ID(aa64_jscvt, ARM_HWCAP_A64_JSCVT); - GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); - GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); - GET_FEATURE_ID(aa64_dcpop, ARM_HWCAP_A64_DCPOP); - GET_FEATURE_ID(aa64_rcpc_8_3, ARM_HWCAP_A64_LRCPC); - GET_FEATURE_ID(aa64_rcpc_8_4, ARM_HWCAP_A64_ILRCPC); - - return hwcaps; -} - -uint64_t get_elf_hwcap2(void) -{ - ARMCPU *cpu =3D ARM_CPU(thread_cpu); - uint64_t hwcaps =3D 0; - - GET_FEATURE_ID(aa64_dcpodp, ARM_HWCAP2_A64_DCPODP); - GET_FEATURE_ID(aa64_sve2, ARM_HWCAP2_A64_SVE2); - GET_FEATURE_ID(aa64_sve2_aes, ARM_HWCAP2_A64_SVEAES); - GET_FEATURE_ID(aa64_sve2_pmull128, ARM_HWCAP2_A64_SVEPMULL); - GET_FEATURE_ID(aa64_sve2_bitperm, ARM_HWCAP2_A64_SVEBITPERM); - GET_FEATURE_ID(aa64_sve2_sha3, ARM_HWCAP2_A64_SVESHA3); - GET_FEATURE_ID(aa64_sve2_sm4, ARM_HWCAP2_A64_SVESM4); - GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); - GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); - GET_FEATURE_ID(aa64_sve_i8mm, ARM_HWCAP2_A64_SVEI8MM); - GET_FEATURE_ID(aa64_sve_f32mm, ARM_HWCAP2_A64_SVEF32MM); - GET_FEATURE_ID(aa64_sve_f64mm, ARM_HWCAP2_A64_SVEF64MM); - GET_FEATURE_ID(aa64_sve_bf16, ARM_HWCAP2_A64_SVEBF16); - GET_FEATURE_ID(aa64_i8mm, ARM_HWCAP2_A64_I8MM); - GET_FEATURE_ID(aa64_bf16, ARM_HWCAP2_A64_BF16); - GET_FEATURE_ID(aa64_rndr, ARM_HWCAP2_A64_RNG); - GET_FEATURE_ID(aa64_bti, ARM_HWCAP2_A64_BTI); - GET_FEATURE_ID(aa64_mte, ARM_HWCAP2_A64_MTE); - GET_FEATURE_ID(aa64_mte3, ARM_HWCAP2_A64_MTE3); - GET_FEATURE_ID(aa64_sme, (ARM_HWCAP2_A64_SME | - ARM_HWCAP2_A64_SME_F32F32 | - ARM_HWCAP2_A64_SME_B16F32 | - ARM_HWCAP2_A64_SME_F16F32 | - ARM_HWCAP2_A64_SME_I8I32)); - GET_FEATURE_ID(aa64_sme_f64f64, ARM_HWCAP2_A64_SME_F64F64); - GET_FEATURE_ID(aa64_sme_i16i64, ARM_HWCAP2_A64_SME_I16I64); - GET_FEATURE_ID(aa64_sme_fa64, ARM_HWCAP2_A64_SME_FA64); - GET_FEATURE_ID(aa64_hbc, ARM_HWCAP2_A64_HBC); - GET_FEATURE_ID(aa64_mops, ARM_HWCAP2_A64_MOPS); - GET_FEATURE_ID(aa64_sve2p1, ARM_HWCAP2_A64_SVE2P1); - GET_FEATURE_ID(aa64_sme2, (ARM_HWCAP2_A64_SME2 | - ARM_HWCAP2_A64_SME_I16I32 | - ARM_HWCAP2_A64_SME_BI32I32)); - GET_FEATURE_ID(aa64_sme2p1, ARM_HWCAP2_A64_SME2P1); - GET_FEATURE_ID(aa64_sme_b16b16, ARM_HWCAP2_A64_SME_B16B16); - GET_FEATURE_ID(aa64_sme_f16f16, ARM_HWCAP2_A64_SME_F16F16); - GET_FEATURE_ID(aa64_sve_b16b16, ARM_HWCAP2_A64_SVE_B16B16); - - return hwcaps; -} - -const char *elf_hwcap_str(uint32_t bit) -{ - static const char * const hwcap_str[] =3D { - [__builtin_ctz(ARM_HWCAP_A64_FP )] =3D "fp", - [__builtin_ctz(ARM_HWCAP_A64_ASIMD )] =3D "asimd", - [__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] =3D "evtstrm", - [__builtin_ctz(ARM_HWCAP_A64_AES )] =3D "aes", - [__builtin_ctz(ARM_HWCAP_A64_PMULL )] =3D "pmull", - [__builtin_ctz(ARM_HWCAP_A64_SHA1 )] =3D "sha1", - [__builtin_ctz(ARM_HWCAP_A64_SHA2 )] =3D "sha2", - [__builtin_ctz(ARM_HWCAP_A64_CRC32 )] =3D "crc32", - [__builtin_ctz(ARM_HWCAP_A64_ATOMICS )] =3D "atomics", - [__builtin_ctz(ARM_HWCAP_A64_FPHP )] =3D "fphp", - [__builtin_ctz(ARM_HWCAP_A64_ASIMDHP )] =3D "asimdhp", - [__builtin_ctz(ARM_HWCAP_A64_CPUID )] =3D "cpuid", - [__builtin_ctz(ARM_HWCAP_A64_ASIMDRDM)] =3D "asimdrdm", - [__builtin_ctz(ARM_HWCAP_A64_JSCVT )] =3D "jscvt", - [__builtin_ctz(ARM_HWCAP_A64_FCMA )] =3D "fcma", - [__builtin_ctz(ARM_HWCAP_A64_LRCPC )] =3D "lrcpc", - [__builtin_ctz(ARM_HWCAP_A64_DCPOP )] =3D "dcpop", - [__builtin_ctz(ARM_HWCAP_A64_SHA3 )] =3D "sha3", - [__builtin_ctz(ARM_HWCAP_A64_SM3 )] =3D "sm3", - [__builtin_ctz(ARM_HWCAP_A64_SM4 )] =3D "sm4", - [__builtin_ctz(ARM_HWCAP_A64_ASIMDDP )] =3D "asimddp", - [__builtin_ctz(ARM_HWCAP_A64_SHA512 )] =3D "sha512", - [__builtin_ctz(ARM_HWCAP_A64_SVE )] =3D "sve", - [__builtin_ctz(ARM_HWCAP_A64_ASIMDFHM)] =3D "asimdfhm", - [__builtin_ctz(ARM_HWCAP_A64_DIT )] =3D "dit", - [__builtin_ctz(ARM_HWCAP_A64_USCAT )] =3D "uscat", - [__builtin_ctz(ARM_HWCAP_A64_ILRCPC )] =3D "ilrcpc", - [__builtin_ctz(ARM_HWCAP_A64_FLAGM )] =3D "flagm", - [__builtin_ctz(ARM_HWCAP_A64_SSBS )] =3D "ssbs", - [__builtin_ctz(ARM_HWCAP_A64_SB )] =3D "sb", - [__builtin_ctz(ARM_HWCAP_A64_PACA )] =3D "paca", - [__builtin_ctz(ARM_HWCAP_A64_PACG )] =3D "pacg", - [__builtin_ctzll(ARM_HWCAP_A64_GCS )] =3D "gcs", - [__builtin_ctzll(ARM_HWCAP_A64_CMPBR )] =3D "cmpbr", - [__builtin_ctzll(ARM_HWCAP_A64_FPRCVT)] =3D "fprcvt", - [__builtin_ctzll(ARM_HWCAP_A64_F8MM8 )] =3D "f8mm8", - [__builtin_ctzll(ARM_HWCAP_A64_F8MM4 )] =3D "f8mm4", - [__builtin_ctzll(ARM_HWCAP_A64_SVE_F16MM)] =3D "svef16mm", - [__builtin_ctzll(ARM_HWCAP_A64_SVE_ELTPERM)] =3D "sveeltperm", - [__builtin_ctzll(ARM_HWCAP_A64_SVE_AES2)] =3D "sveaes2", - [__builtin_ctzll(ARM_HWCAP_A64_SVE_BFSCALE)] =3D "svebfscale", - [__builtin_ctzll(ARM_HWCAP_A64_SVE2P2)] =3D "sve2p2", - [__builtin_ctzll(ARM_HWCAP_A64_SME2P2)] =3D "sme2p2", - [__builtin_ctzll(ARM_HWCAP_A64_SME_SBITPERM)] =3D "smesbitperm", - [__builtin_ctzll(ARM_HWCAP_A64_SME_AES)] =3D "smeaes", - [__builtin_ctzll(ARM_HWCAP_A64_SME_SFEXPA)] =3D "smesfexpa", - [__builtin_ctzll(ARM_HWCAP_A64_SME_STMOP)] =3D "smestmop", - [__builtin_ctzll(ARM_HWCAP_A64_SME_SMOP4)] =3D "smesmop4", - }; - - return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; -} - -const char *elf_hwcap2_str(uint32_t bit) -{ - static const char * const hwcap_str[] =3D { - [__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] =3D "dcpodp", - [__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] =3D "sve2", - [__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] =3D "sveaes", - [__builtin_ctz(ARM_HWCAP2_A64_SVEPMULL )] =3D "svepmull", - [__builtin_ctz(ARM_HWCAP2_A64_SVEBITPERM )] =3D "svebitperm", - [__builtin_ctz(ARM_HWCAP2_A64_SVESHA3 )] =3D "svesha3", - [__builtin_ctz(ARM_HWCAP2_A64_SVESM4 )] =3D "svesm4", - [__builtin_ctz(ARM_HWCAP2_A64_FLAGM2 )] =3D "flagm2", - [__builtin_ctz(ARM_HWCAP2_A64_FRINT )] =3D "frint", - [__builtin_ctz(ARM_HWCAP2_A64_SVEI8MM )] =3D "svei8mm", - [__builtin_ctz(ARM_HWCAP2_A64_SVEF32MM )] =3D "svef32mm", - [__builtin_ctz(ARM_HWCAP2_A64_SVEF64MM )] =3D "svef64mm", - [__builtin_ctz(ARM_HWCAP2_A64_SVEBF16 )] =3D "svebf16", - [__builtin_ctz(ARM_HWCAP2_A64_I8MM )] =3D "i8mm", - [__builtin_ctz(ARM_HWCAP2_A64_BF16 )] =3D "bf16", - [__builtin_ctz(ARM_HWCAP2_A64_DGH )] =3D "dgh", - [__builtin_ctz(ARM_HWCAP2_A64_RNG )] =3D "rng", - [__builtin_ctz(ARM_HWCAP2_A64_BTI )] =3D "bti", - [__builtin_ctz(ARM_HWCAP2_A64_MTE )] =3D "mte", - [__builtin_ctz(ARM_HWCAP2_A64_ECV )] =3D "ecv", - [__builtin_ctz(ARM_HWCAP2_A64_AFP )] =3D "afp", - [__builtin_ctz(ARM_HWCAP2_A64_RPRES )] =3D "rpres", - [__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] =3D "mte3", - [__builtin_ctz(ARM_HWCAP2_A64_SME )] =3D "sme", - [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] =3D "smei16i64", - [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] =3D "smef64f64", - [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] =3D "smei8i32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] =3D "smef16f32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] =3D "smeb16f32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] =3D "smef32f32", - [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] =3D "smefa64", - [__builtin_ctz(ARM_HWCAP2_A64_WFXT )] =3D "wfxt", - [__builtin_ctzll(ARM_HWCAP2_A64_EBF16 )] =3D "ebf16", - [__builtin_ctzll(ARM_HWCAP2_A64_SVE_EBF16 )] =3D "sveebf16", - [__builtin_ctzll(ARM_HWCAP2_A64_CSSC )] =3D "cssc", - [__builtin_ctzll(ARM_HWCAP2_A64_RPRFM )] =3D "rprfm", - [__builtin_ctzll(ARM_HWCAP2_A64_SVE2P1 )] =3D "sve2p1", - [__builtin_ctzll(ARM_HWCAP2_A64_SME2 )] =3D "sme2", - [__builtin_ctzll(ARM_HWCAP2_A64_SME2P1 )] =3D "sme2p1", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_I16I32 )] =3D "smei16i32", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_BI32I32)] =3D "smebi32i32", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_B16B16 )] =3D "smeb16b16", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_F16F16 )] =3D "smef16f16", - [__builtin_ctzll(ARM_HWCAP2_A64_MOPS )] =3D "mops", - [__builtin_ctzll(ARM_HWCAP2_A64_HBC )] =3D "hbc", - [__builtin_ctzll(ARM_HWCAP2_A64_SVE_B16B16 )] =3D "sveb16b16", - [__builtin_ctzll(ARM_HWCAP2_A64_LRCPC3 )] =3D "lrcpc3", - [__builtin_ctzll(ARM_HWCAP2_A64_LSE128 )] =3D "lse128", - [__builtin_ctzll(ARM_HWCAP2_A64_FPMR )] =3D "fpmr", - [__builtin_ctzll(ARM_HWCAP2_A64_LUT )] =3D "lut", - [__builtin_ctzll(ARM_HWCAP2_A64_FAMINMAX )] =3D "faminmax", - [__builtin_ctzll(ARM_HWCAP2_A64_F8CVT )] =3D "f8cvt", - [__builtin_ctzll(ARM_HWCAP2_A64_F8FMA )] =3D "f8fma", - [__builtin_ctzll(ARM_HWCAP2_A64_F8DP4 )] =3D "f8dp4", - [__builtin_ctzll(ARM_HWCAP2_A64_F8DP2 )] =3D "f8dp2", - [__builtin_ctzll(ARM_HWCAP2_A64_F8E4M3 )] =3D "f8e4m3", - [__builtin_ctzll(ARM_HWCAP2_A64_F8E5M2 )] =3D "f8e5m2", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_LUTV2 )] =3D "smelutv2", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F16 )] =3D "smef8f16", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_F8F32 )] =3D "smef8f32", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP4 )] =3D "smesf8dp4", - [__builtin_ctzll(ARM_HWCAP2_A64_SME_SF8DP2 )] =3D "smesf8dp2", - [__builtin_ctzll(ARM_HWCAP2_A64_POE )] =3D "poe", - }; - - return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; -} - -#undef GET_FEATURE_ID +#define ELF_HWCAP get_elf_hwcap(thread_cpu) +#define ELF_HWCAP2 get_elf_hwcap2(thread_cpu) =20 #if TARGET_BIG_ENDIAN # define VDSO_HEADER "vdso-be.c.inc" --=20 2.43.0