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Tsirkin" , Igor Mammedov , Ani Sinha , Paolo Bonzini , Richard Henderson , Eduardo Habkost , Eric Blake , Markus Armbruster , Marcel Apfelbaum , Dmitry Fleytman Cc: Leonid Bloch , qemu-devel@nongnu.org Subject: [PATCH v3 1/4] hw/acpi: Support extended GPE handling for additional ACPI devices Date: Thu, 28 Aug 2025 01:00:47 +0300 Message-ID: <20250827220054.37268-2-lb.workbox@gmail.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20250827220054.37268-1-lb.workbox@gmail.com> References: <20250827220054.37268-1-lb.workbox@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=lb.workbox@gmail.com; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1756332182586116600 Content-Type: text/plain; charset="utf-8" This patch extends the GPE (General Purpose Event) handling to support the maximum number of interrupts available based on the machine's GPE register length, rather than being limited to the first 8 bits. This change is needed to support additional ACPI devices that will be introduced in subsequent patches (Battery, AC adapter, and button devices). These new devices require GPE event bits beyond the first 8, which were previously not being properly handled by the event sending and SCI (System Control Interrupt) update mechanisms. The actual number of available GPE interrupts varies by machine type: - PIIX4: GPE_LEN =3D 4 (32 bits total across status and enable registers) - ICH9: ICH9_PMIO_GPE0_LEN =3D 16 (128 bits total) The patch modifies: - acpi_send_gpe_event(): Now properly propagates status bits across all available GPE registers based on the machine's gpe.len value - acpi_update_sci(): Checks all GPE registers for pending interrupts, not just the first byte Note: A future enhancement could refactor the GPE handling to use the bitmap API from bitops.h instead of the current manual bit manipulation, which would provide a cleaner interface for these operations. Signed-off-by: Leonid Bloch --- hw/acpi/core.c | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/hw/acpi/core.c b/hw/acpi/core.c index 58f8964e13..3240ec185e 100644 --- a/hw/acpi/core.c +++ b/hw/acpi/core.c @@ -729,19 +729,32 @@ uint32_t acpi_gpe_ioport_readb(ACPIREGS *ar, uint32_t= addr) void acpi_send_gpe_event(ACPIREGS *ar, qemu_irq irq, AcpiEventStatusBits status) { - ar->gpe.sts[0] |=3D status; + int i; + AcpiEventStatusBits st =3D status; + + for (i =3D 0; i < ar->gpe.len / 2; i++) { + ar->gpe.sts[i] |=3D st; + st >>=3D TYPE_WIDTH(ar->gpe.sts[0]); + } + acpi_update_sci(ar, irq); } =20 void acpi_update_sci(ACPIREGS *regs, qemu_irq irq) { int sci_level, pm1a_sts; + bool gpe_sci =3D false; + int i; =20 pm1a_sts =3D acpi_pm1_evt_get_sts(regs); =20 + for (i =3D 0; i < regs->gpe.len / 2; i++) { + gpe_sci =3D gpe_sci || !!(regs->gpe.sts[i] & regs->gpe.en[i]); + } + sci_level =3D ((pm1a_sts & regs->pm1.evt.en & ACPI_BITMASK_PM1_COMMON_ENABLED) !=3D= 0) || - ((regs->gpe.sts[0] & regs->gpe.en[0]) !=3D 0); + gpe_sci; =20 qemu_set_irq(irq, sci_level); =20 --=20 2.51.0