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Wed, 27 Aug 2025 13:36:18 -0700 (PDT) From: stove To: qemu-devel@nongnu.org Cc: Liu Zhiwei , qemu-riscv@nongnu.org, Daniel Henrique Barboza , Alistair Francis , Weiwei Li , Palmer Dabbelt , stove Subject: [PATCH] target/riscv: use riscv_csrr in riscv_csr_read Date: Wed, 27 Aug 2025 13:36:17 -0700 Message-ID: <20250827203617.79947-1-stove@rivosinc.com> X-Mailer: git-send-email 2.50.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=stove@rivosinc.com; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @rivosinc.com) X-ZM-MESSAGEID: 1756327042921116600 Content-Type: text/plain; charset="utf-8" Commit 38c83e8d3a33 ("target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR") changed the behavior of riscv_csrrw, which would formerly be treated as read-only if the write mask were set to 0. Fixes an exception being raised when accessing read-only vector CSRs like vtype. Fixes: 38c83e8d3a33 ("target/riscv: raise an exception when CSRRS/CSRRC wri= tes a read-only CSR") Signed-off-by: stove Reviewed-by: Daniel Henrique Barboza --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 4a862da615..dca8edff6d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -873,7 +873,7 @@ static inline void riscv_csr_write(CPURISCVState *env, = int csrno, static inline target_ulong riscv_csr_read(CPURISCVState *env, int csrno) { target_ulong val =3D 0; - riscv_csrrw(env, csrno, &val, 0, 0, 0); + riscv_csrr(env, csrno, &val); return val; } =20 --=20 2.50.1