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Wed, 27 Aug 2025 20:03:29 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 5CE772698ED; Wed, 27 Aug 2025 20:03:56 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Richard Henderson , Fabiano Rosas , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Maydell , Michael Tokarev Subject: [Stable-7.2.20 05/18] target/arm/sme: Introduce aarch64_set_svcr() Date: Wed, 27 Aug 2025 20:03:40 +0300 Message-ID: <20250827170356.2698446-5-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756314357386116601 From: Richard Henderson Signed-off-by: Richard Henderson Reviewed-by: Fabiano Rosas Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20230112102436.1913-4-philmd@linaro.org Message-Id: <20230112004322.161330-1-richard.henderson@linaro.org> [PMD: Split patch in multiple tiny steps] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell (cherry picked from commit 2a8af3825958e5d8c98b3ca92ac42a10e25db9e1) Signed-off-by: Michael Tokarev diff --git a/linux-user/aarch64/cpu_loop.c b/linux-user/aarch64/cpu_loop.c index 9875d609a9..d53742e10b 100644 --- a/linux-user/aarch64/cpu_loop.c +++ b/linux-user/aarch64/cpu_loop.c @@ -93,8 +93,8 @@ void cpu_loop(CPUARMState *env) * On syscall, PSTATE.ZA is preserved, along with the ZA matri= x. * PSTATE.SM is cleared, per SMSTOP, which does ResetSVEState. */ + aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); if (FIELD_EX64(env->svcr, SVCR, SM)) { - env->svcr =3D FIELD_DP64(env->svcr, SVCR, SM, 0); arm_rebuild_hflags(env); arm_reset_sve_state(env); } diff --git a/linux-user/aarch64/signal.c b/linux-user/aarch64/signal.c index 6a2c6e06d2..b6e4dcb494 100644 --- a/linux-user/aarch64/signal.c +++ b/linux-user/aarch64/signal.c @@ -669,11 +669,11 @@ static void target_setup_frame(int usig, struct targe= t_sigaction *ka, * Invoke the signal handler with both SM and ZA disabled. * When clearing SM, ResetSVEState, per SMSTOP. */ + aarch64_set_svcr(env, 0, R_SVCR_SM_MASK | R_SVCR_ZA_MASK); if (FIELD_EX64(env->svcr, SVCR, SM)) { arm_reset_sve_state(env); } if (env->svcr) { - env->svcr =3D 0; arm_rebuild_hflags(env); } =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 32b0bf8e2d..8acfd3af4c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1118,6 +1118,7 @@ int aarch64_cpu_gdb_write_register(CPUState *cpu, uin= t8_t *buf, int reg); void aarch64_sve_narrow_vq(CPUARMState *env, unsigned vq); void aarch64_sve_change_el(CPUARMState *env, int old_el, int new_el, bool el0_a64); +void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask); void arm_reset_sve_state(CPUARMState *env); =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 6cffbcb276..86b97daf7e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6429,11 +6429,19 @@ static CPAccessResult access_esm(CPUARMState *env, = const ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +void aarch64_set_svcr(CPUARMState *env, uint64_t new, uint64_t mask) +{ + uint64_t change =3D (env->svcr ^ new) & mask; + + env->svcr ^=3D change; +} + static void svcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { helper_set_pstate_sm(env, FIELD_EX64(value, SVCR, SM)); helper_set_pstate_za(env, FIELD_EX64(value, SVCR, ZA)); + aarch64_set_svcr(env, value, -1); arm_rebuild_hflags(env); } =20 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index 8ba3f3a247..7717dab64f 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -43,7 +43,7 @@ void helper_set_pstate_sm(CPUARMState *env, uint32_t i) if (i =3D=3D FIELD_EX64(env->svcr, SVCR, SM)) { return; } - env->svcr ^=3D R_SVCR_SM_MASK; + aarch64_set_svcr(env, 0, R_SVCR_SM_MASK); arm_reset_sve_state(env); arm_rebuild_hflags(env); } @@ -53,7 +53,7 @@ void helper_set_pstate_za(CPUARMState *env, uint32_t i) if (i =3D=3D FIELD_EX64(env->svcr, SVCR, ZA)) { return; } - env->svcr ^=3D R_SVCR_ZA_MASK; + aarch64_set_svcr(env, 0, R_SVCR_ZA_MASK); =20 /* * ResetSMEState. --=20 2.47.2