From nobody Sun Sep 28 15:58:45 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756307665837278.90854855040095; Wed, 27 Aug 2025 08:14:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1urHnB-0005AP-4Q; Wed, 27 Aug 2025 11:10:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHkx-0000JI-67; Wed, 27 Aug 2025 11:08:12 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHkp-0005of-Ad; Wed, 27 Aug 2025 11:08:09 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id E234614C55B; Wed, 27 Aug 2025 18:02:59 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id D0909269862; Wed, 27 Aug 2025 18:03:26 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Klaus Jensen , Alan Adamson , Michael Tokarev Subject: [Stable-10.0.4 50/59] hw/nvme: revert CMIC behavior Date: Wed, 27 Aug 2025 18:02:55 +0300 Message-ID: <20250827150323.2694101-50-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756307667296116600 Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Commit cd59f50ab017 ("hw/nvme: always initialize a subsystem") causes the controller to always set the CMIC.MCTRS ("Multiple Controllers") bit. While spec-compliant, this is a deviation from the previous behavior where this was only set if an nvme-subsys device was explicitly created (to configure a subsystem with multiple controllers/namespaces). Revert the behavior to only set CMIC.MCTRS if an nvme-subsys device is created explicitly. Reported-by: Alan Adamson Fixes: cd59f50ab017 ("hw/nvme: always initialize a subsystem") Reviewed-by: Alan Adamson Tested-by: Alan Adamson Signed-off-by: Klaus Jensen (cherry picked from commit bc0c24fdb157b014932a5012fe4ccbeba7617f17) Signed-off-by: Michael Tokarev diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index 669fff41c7..f34bd68c04 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8780,7 +8780,7 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pc= i_dev) uint8_t *pci_conf =3D pci_dev->config; uint64_t cap =3D ldq_le_p(&n->bar.cap); NvmeSecCtrlEntry *sctrl =3D nvme_sctrl(n); - uint32_t ctratt; + uint32_t ctratt =3D le32_to_cpu(id->ctratt); uint16_t oacs; =20 memcpy(n->cse.acs, nvme_cse_acs_default, sizeof(n->cse.acs)); @@ -8798,10 +8798,11 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *= pci_dev) =20 id->oaes =3D cpu_to_le32(NVME_OAES_NS_ATTR); =20 - ctratt =3D NVME_CTRATT_ELBAS; + ctratt |=3D NVME_CTRATT_ELBAS; if (n->params.ctratt.mem) { ctratt |=3D NVME_CTRATT_MEM; } + id->ctratt =3D cpu_to_le32(ctratt); =20 id->rab =3D 6; =20 @@ -8884,17 +8885,6 @@ static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *p= ci_dev) id->psd[0].enlat =3D cpu_to_le32(0x10); id->psd[0].exlat =3D cpu_to_le32(0x4); =20 - id->cmic |=3D NVME_CMIC_MULTI_CTRL; - ctratt |=3D NVME_CTRATT_ENDGRPS; - - id->endgidmax =3D cpu_to_le16(0x1); - - if (n->subsys->endgrp.fdp.enabled) { - ctratt |=3D NVME_CTRATT_FDPS; - } - - id->ctratt =3D cpu_to_le32(ctratt); - NVME_CAP_SET_MQES(cap, n->params.mqes); NVME_CAP_SET_CQR(cap, 1); NVME_CAP_SET_TO(cap, 0xf); @@ -8927,6 +8917,20 @@ static int nvme_init_subsys(NvmeCtrl *n, Error **err= p) } =20 n->subsys =3D NVME_SUBSYS(dev); + } else { + NvmeIdCtrl *id =3D &n->id_ctrl; + uint32_t ctratt =3D le32_to_cpu(id->ctratt); + + id->cmic |=3D NVME_CMIC_MULTI_CTRL; + ctratt |=3D NVME_CTRATT_ENDGRPS; + + id->endgidmax =3D cpu_to_le16(0x1); + + if (n->subsys->endgrp.fdp.enabled) { + ctratt |=3D NVME_CTRATT_FDPS; + } + + id->ctratt =3D cpu_to_le32(ctratt); } =20 cntlid =3D nvme_subsys_register_ctrl(n, errp); --=20 2.47.2