From nobody Sun Sep 28 16:32:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756308200179463.2263323159923; Wed, 27 Aug 2025 08:23:20 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1urHlu-000283-Ij; Wed, 27 Aug 2025 11:09:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHjp-0007Ev-Eg; Wed, 27 Aug 2025 11:07:02 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHjm-0005Wf-D0; Wed, 27 Aug 2025 11:07:01 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 2717C14C550; Wed, 27 Aug 2025 18:02:59 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 10087269858; Wed, 27 Aug 2025 18:03:26 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Glenn Miles , Nicholas Piggin , Michael Kowal , Caleb Schlossin , Gautam Menghani , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Michael Tokarev Subject: [Stable-10.0.4 40/59] ppc/xive2: Fix calculation of END queue sizes Date: Wed, 27 Aug 2025 18:02:45 +0300 Message-ID: <20250827150323.2694101-40-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: References: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756308201376116600 From: Glenn Miles The queue size of an Event Notification Descriptor (END) is determined by the 'cl' and QsZ fields of the END. If the cl field is 1, then the queue size (in bytes) will be the size of a cache line 128B * 2^QsZ and QsZ is limited to 4. Otherwise, it will be 4096B * 2^QsZ with QsZ limited to 12. Fixes: f8a233dedf2 ("ppc/xive2: Introduce a XIVE2 core framework") Signed-off-by: Glenn Miles Reviewed-by: Nicholas Piggin Reviewed-by: Michael Kowal Reviewed-by: Caleb Schlossin Tested-by: Gautam Menghani Link: https://lore.kernel.org/qemu-devel/20250512031100.439842-4-npiggin@gm= ail.com Signed-off-by: C=C3=A9dric Le Goater (cherry picked from commit f16697292add6c3c15014a20fd5fce70b8c56734) Signed-off-by: Michael Tokarev diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 7d584dfafa..790152a2a6 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -188,12 +188,27 @@ void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t= lisn, GString *buf) (uint32_t) xive_get_field64(EAS2_END_DATA, eas-= >w)); } =20 +#define XIVE2_QSIZE_CHUNK_CL 128 +#define XIVE2_QSIZE_CHUNK_4k 4096 +/* Calculate max number of queue entries for an END */ +static uint32_t xive2_end_get_qentries(Xive2End *end) +{ + uint32_t w3 =3D end->w3; + uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, w3); + if (xive_get_field32(END2_W3_CL, w3)) { + g_assert(qsize <=3D 4); + return (XIVE2_QSIZE_CHUNK_CL << qsize) / sizeof(uint32_t); + } else { + g_assert(qsize <=3D 12); + return (XIVE2_QSIZE_CHUNK_4k << qsize) / sizeof(uint32_t); + } +} + void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width, GString= *buf) { uint64_t qaddr_base =3D xive2_end_qaddr(end); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); int i; =20 /* @@ -223,8 +238,7 @@ void xive2_end_pic_print_info(Xive2End *end, uint32_t e= nd_idx, GString *buf) uint64_t qaddr_base =3D xive2_end_qaddr(end); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); =20 uint32_t nvx_blk =3D xive_get_field32(END2_W6_VP_BLOCK, end->w6); uint32_t nvx_idx =3D xive_get_field32(END2_W6_VP_OFFSET, end->w6); @@ -341,13 +355,12 @@ void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint3= 2_t nvgc_idx, GString *buf) static void xive2_end_enqueue(Xive2End *end, uint32_t data) { uint64_t qaddr_base =3D xive2_end_qaddr(end); - uint32_t qsize =3D xive_get_field32(END2_W3_QSIZE, end->w3); uint32_t qindex =3D xive_get_field32(END2_W1_PAGE_OFF, end->w1); uint32_t qgen =3D xive_get_field32(END2_W1_GENERATION, end->w1); =20 uint64_t qaddr =3D qaddr_base + (qindex << 2); uint32_t qdata =3D cpu_to_be32((qgen << 31) | (data & 0x7fffffff)); - uint32_t qentries =3D 1 << (qsize + 10); + uint32_t qentries =3D xive2_end_get_qentries(end); =20 if (dma_memory_write(&address_space_memory, qaddr, &qdata, sizeof(qdat= a), MEMTXATTRS_UNSPECIFIED)) { diff --git a/include/hw/ppc/xive2_regs.h b/include/hw/ppc/xive2_regs.h index b11395c563..3c28de8a30 100644 --- a/include/hw/ppc/xive2_regs.h +++ b/include/hw/ppc/xive2_regs.h @@ -87,6 +87,7 @@ typedef struct Xive2End { #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31) uint32_t w3; #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24) +#define END2_W3_CL PPC_BIT32(27) #define END2_W3_QSIZE PPC_BITMASK32(28, 31) uint32_t w4; #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7) --=20 2.47.2