From nobody Sun Sep 28 16:32:12 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756307253105133.60773348683313; Wed, 27 Aug 2025 08:07:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1urHi2-0004cC-0I; Wed, 27 Aug 2025 11:05:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHhe-0003vq-89; Wed, 27 Aug 2025 11:04:49 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHhb-0004tr-PX; Wed, 27 Aug 2025 11:04:45 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 81E4214C539; Wed, 27 Aug 2025 18:02:57 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 6D100269841; Wed, 27 Aug 2025 18:03:24 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Jay Chang , Frank Chang , Alistair Francis , Nutty Liu , Michael Tokarev Subject: [Stable-10.0.4 17/59] target/riscv: Restrict midelegh access to S-mode harts Date: Wed, 27 Aug 2025 18:02:22 +0300 Message-ID: <20250827150323.2694101-17-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756307254605116600 Content-Type: text/plain; charset="utf-8" From: Jay Chang RISC-V AIA Spec states: "For a machine-level environment, extension Smaia encompasses all added CSRs and all modifications to interrupt response behavior that the AIA specifies for a hart, over all privilege levels. For a supervisor-level environment, extension Ssaia is essentially the same as Smaia except excluding the machine-level CSRs and behavior not directly visible to supervisor level." Since midelegh is an AIA machine-mode CSR, add Smaia extension check in aia_smode32 predicate. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jay Chang Reviewed-by: Nutty Liu Message-ID: <20250701030021.99218-3-jay.chang@sifive.com> Signed-off-by: Alistair Francis (cherry picked from commit 86bc3a0abf10072081cddd8dff25aa72c60e67b8) Signed-off-by: Michael Tokarev diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7fe6ac7ea2..66d572af1f 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -372,8 +372,11 @@ static RISCVException aia_smode(CPURISCVState *env, in= t csrno) static RISCVException aia_smode32(CPURISCVState *env, int csrno) { int ret; + int csr_priv =3D get_field(csrno, 0x300); =20 - if (!riscv_cpu_cfg(env)->ext_ssaia) { + if (csr_priv =3D=3D PRV_M && !riscv_cpu_cfg(env)->ext_smaia) { + return RISCV_EXCP_ILLEGAL_INST; + } else if (!riscv_cpu_cfg(env)->ext_ssaia) { return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -5832,7 +5835,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MVIP] =3D { "mvip", aia_any, NULL, NULL, rmw_mvip }, =20 /* Machine-Level High-Half CSRs (AIA) */ - [CSR_MIDELEGH] =3D { "midelegh", aia_any32, NULL, NULL, rmw_midelegh }, + [CSR_MIDELEGH] =3D { "midelegh", aia_smode32, NULL, NULL, rmw_midelegh= }, [CSR_MIEH] =3D { "mieh", aia_any32, NULL, NULL, rmw_mieh }, [CSR_MVIENH] =3D { "mvienh", aia_any32, NULL, NULL, rmw_mvienh }, [CSR_MVIPH] =3D { "mviph", aia_any32, NULL, NULL, rmw_mviph }, --=20 2.47.2