From nobody Sun Sep 28 16:32:08 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756307353414325.104180898412; Wed, 27 Aug 2025 08:09:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1urHhS-0003VZ-6K; Wed, 27 Aug 2025 11:04:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHhH-00036J-FQ; Wed, 27 Aug 2025 11:04:23 -0400 Received: from isrv.corpit.ru ([212.248.84.144]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urHhF-0004tU-31; Wed, 27 Aug 2025 11:04:23 -0400 Received: from tsrv.corpit.ru (tsrv.tls.msk.ru [192.168.177.2]) by isrv.corpit.ru (Postfix) with ESMTP id 6F7E814C538; Wed, 27 Aug 2025 18:02:57 +0300 (MSK) Received: from think4mjt.tls.msk.ru (mjtthink.wg.tls.msk.ru [192.168.177.146]) by tsrv.corpit.ru (Postfix) with ESMTP id 5AA7D269840; Wed, 27 Aug 2025 18:03:24 +0300 (MSK) From: Michael Tokarev To: qemu-devel@nongnu.org Cc: qemu-stable@nongnu.org, Jay Chang , Frank Chang , Alistair Francis , Nutty Liu , Michael Tokarev Subject: [Stable-10.0.4 16/59] target/riscv: Restrict mideleg/medeleg/medelegh access to S-mode harts Date: Wed, 27 Aug 2025 18:02:21 +0300 Message-ID: <20250827150323.2694101-16-mjt@tls.msk.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=212.248.84.144; envelope-from=mjt@tls.msk.ru; helo=isrv.corpit.ru X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756307355644124100 Content-Type: text/plain; charset="utf-8" From: Jay Chang RISC-V Privileged Spec states: "In harts with S-mode, the medeleg and mideleg registers must exist, and setting a bit in medeleg or mideleg will delegate the corresponding trap , when occurring in S-mode or U-mode, to the S-mode trap handler. In harts without S-mode, the medeleg and mideleg registers should not exist." Add smode predicate to ensure these CSRs are only accessible when S-mode is supported. Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Signed-off-by: Jay Chang Reviewed-by: Nutty Liu Message-ID: <20250701030021.99218-2-jay.chang@sifive.com> Signed-off-by: Alistair Francis (cherry picked from commit e443ba03361b63218e6c3aa4f73d2cb5b9b1d372) Signed-off-by: Michael Tokarev diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f1c4c8c1b8..7fe6ac7ea2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -5783,8 +5783,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { NULL, read_mstatus_i128 = }, [CSR_MISA] =3D { "misa", any, read_misa, write_misa, NULL, read_misa_i128 = }, - [CSR_MIDELEG] =3D { "mideleg", any, NULL, NULL, rmw_mideleg= }, - [CSR_MEDELEG] =3D { "medeleg", any, read_medeleg, write_medel= eg }, + [CSR_MIDELEG] =3D { "mideleg", smode, NULL, NULL, rmw_midel= eg }, + [CSR_MEDELEG] =3D { "medeleg", smode, read_medeleg, write_med= eleg }, [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie = }, [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_mtvec= }, [CSR_MCOUNTEREN] =3D { "mcounteren", umode, read_mcounteren, @@ -5792,7 +5792,7 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_mstatush = }, - [CSR_MEDELEGH] =3D { "medelegh", any32, read_zero, write_ignore, + [CSR_MEDELEGH] =3D { "medelegh", smode32, read_zero, write_ignore, .min_priv_ver =3D PRIV_VERSION_1_13_0 = }, [CSR_HEDELEGH] =3D { "hedelegh", hmode32, read_hedelegh, write_he= delegh, .min_priv_ver =3D PRIV_VERSION_1_13_0 = }, --=20 2.47.2