From nobody Sun Sep 28 16:35:33 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756282346653358.35027119513836; Wed, 27 Aug 2025 01:12:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1urBFc-00043r-Tt; Wed, 27 Aug 2025 04:11:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1urBFb-0003zq-1Q for qemu-devel@nongnu.org; Wed, 27 Aug 2025 04:11:23 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1urBFV-0004kq-8v for qemu-devel@nongnu.org; Wed, 27 Aug 2025 04:11:22 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxqdE5va5oa7ADAA--.7192S3; Wed, 27 Aug 2025 16:09:29 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJCxXME4va5oWKVrAA--.18662S5; Wed, 27 Aug 2025 16:09:29 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v3 03/12] target/loongarch: Add present and write bit with pte entry Date: Wed, 27 Aug 2025 16:09:18 +0800 Message-Id: <20250827080927.1644016-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250827080927.1644016-1-maobibo@loongson.cn> References: <20250827080927.1644016-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJCxXME4va5oWKVrAA--.18662S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1756282347821116600 Content-Type: text/plain; charset="utf-8" With hardware PTW feature enabled, Present) bit and Write bit is checked by hardware, rather Valid bit and Dirty bit. Bit P means that the page is valid and present, and bit W means that the page is writable. The original V bit is treated as access bit, hardware sets this bit if there is read or write access. Bit D bit is updated by hardware if there is write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 2 ++ target/loongarch/cpu-mmu.h | 31 +++++++++++++++++++++++++++++++ target/loongarch/cpu_helper.c | 4 ++-- target/loongarch/tcg/tlb_helper.c | 14 +++++++------- 4 files changed, 42 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 043b2f14b9..345a51d04a 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -68,6 +68,8 @@ FIELD(TLBENTRY, PLV, 2, 2) FIELD(TLBENTRY, MAT, 4, 2) FIELD(TLBENTRY, G, 6, 1) FIELD(TLBENTRY, HUGE, 6, 1) +FIELD(TLBENTRY, P, 7, 1) +FIELD(TLBENTRY, W, 8, 1) FIELD(TLBENTRY, HGLOBAL, 12, 1) FIELD(TLBENTRY, LEVEL, 13, 2) FIELD(TLBENTRY_32, PPN, 8, 24) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 311bf7b2d7..e4f3199f44 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -29,6 +29,37 @@ typedef struct MMUContext { int mmu_index; } MMUContext; =20 +static inline bool cpu_has_ptw(CPULoongArchState *env) +{ + return !!FIELD_EX64(env->CSR_PWCH, CSR_PWCH, HPTW_EN); +} + +static inline bool pte_present(CPULoongArchState *env, uint64_t entry) +{ + uint8_t present; + + if (cpu_has_ptw(env)) { + present =3D FIELD_EX64(entry, TLBENTRY, P); + } else { + present =3D FIELD_EX64(entry, TLBENTRY, V); + } + + return !!present; +} + +static inline bool pte_write(CPULoongArchState *env, uint64_t entry) +{ + uint8_t writable; + + if (cpu_has_ptw(env)) { + writable =3D FIELD_EX64(entry, TLBENTRY, W); + } else { + writable =3D FIELD_EX64(entry, TLBENTRY, D); + } + + return !!writable; +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 6572d0a7cc..2e07049425 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -53,8 +53,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUCon= text *context, =20 tlb_entry =3D context->pte; tlb_ps =3D context->ps; - tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); - tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_v =3D pte_present(env, tlb_entry); + tlb_d =3D pte_write(env, tlb_entry); tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); if (is_la64(env)) { tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 7a4de7e566..10c01ead3f 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -119,11 +119,9 @@ static void raise_mmu_exception(CPULoongArchState *env= , vaddr address, static void invalidate_tlb_entry(CPULoongArchState *env, int index) { target_ulong addr, mask, pagesize; - uint8_t tlb_ps; + uint8_t tlb_ps, tlb_v; LoongArchTLB *tlb =3D &env->tlb[index]; int mmu_idx; - uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); - uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); uint8_t tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); =20 @@ -137,7 +135,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; addr =3D sextract64(addr, 0, TARGET_VIRT_ADDR_SPACE_BITS); =20 - if (tlb_v0) { + tlb_v =3D pte_present(env, tlb->tlb_entry0); + if (tlb_v) { mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry0, TLBENTRY, PLV)); /* Even page is accessed in kernel mode */ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW0) { @@ -147,7 +146,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) mmu_idx, TARGET_LONG_BITS); } =20 - if (tlb_v1) { + tlb_v =3D pte_present(env, tlb->tlb_entry1); + if (tlb_v) { mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry1, TLBENTRY, PLV)); /* Odd page is accessed in kernel mode */ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW1) { @@ -362,8 +362,8 @@ void helper_tlbwr(CPULoongArchState *env) /* Check whether ASID/VPPN is the same */ if (old->tlb_misc =3D=3D new.tlb_misc) { /* Check whether pte is the same or invalid */ - tlb_v0 =3D FIELD_EX64(old->tlb_entry0, TLBENTRY, V); - tlb_v1 =3D FIELD_EX64(old->tlb_entry1, TLBENTRY, V); + tlb_v0 =3D pte_present(env, old->tlb_entry0); + tlb_v1 =3D pte_present(env, old->tlb_entry1); if ((!tlb_v0 || new.tlb_entry0 =3D=3D old->tlb_entry0) && (!tlb_v1 || new.tlb_entry1 =3D=3D old->tlb_entry1)) { skip_inv =3D true; --=20 2.39.3