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Tue, 26 Aug 2025 18:11:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 51/61] target/arm: Implement MRRS, MSRR, SYSP Date: Wed, 27 Aug 2025 11:04:42 +1000 Message-ID: <20250827010453.4059782-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250827010453.4059782-1-richard.henderson@linaro.org> References: <20250827010453.4059782-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756257905714116600 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/tcg/translate-a64.c | 162 +++++++++++++++++++++++++-------- target/arm/tcg/a64.decode | 12 ++- 2 files changed, 132 insertions(+), 42 deletions(-) diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 7de8717056..2ec088b641 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2470,17 +2470,23 @@ redirect_cpreg(DisasContext *s, uint32_t key, bool = isread) =20 /* MRS - move from system register * MSR (register) - move to system register + * MRRS + * MSRR * SYS * SYSL + * SYSP * These are all essentially the same insn in 'read' and 'write' * versions, with varying op0 fields. + * + * RT2 is non-zero if and only if this is a 128-bit access. */ static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, - unsigned int crn, unsigned int crm, unsigned int rt) + unsigned int crn, unsigned int crm, unsigned int rt, + unsigned int rt2) { uint32_t key =3D ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2); - const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); + const ARMCPRegInfo *ri; bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; bool nv_redirect_reg =3D false; @@ -2488,7 +2494,16 @@ static void handle_sys(DisasContext *s, bool isread, bool nv2_mem_redirect =3D false; TCGv_ptr tcg_ri =3D NULL; TCGv_i64 tcg_rt; - uint32_t syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt,= isread); + uint32_t syndrome; + bool is128 =3D rt2 !=3D 0; + + if (is128) { + key |=3D CP_REG_AA64_128BIT_MASK; + syndrome =3D syn_aa64_sysreg128trap(op0, op1, op2, crn, crm, rt, i= sread); + } else { + syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); + } + ri =3D get_arm_cp_reginfo(s->cp_regs, key); =20 if (crn =3D=3D 11 || crn =3D=3D 15) { /* @@ -2508,12 +2523,14 @@ static void handle_sys(DisasContext *s, bool isread, } =20 if (!ri) { - /* Unknown register; this might be a guest error or a QEMU - * unimplemented feature. + /* + * Unknown register, or 128-bit access to a 64-bit register. + * This might be a guest error or a QEMU unimplemented feature. */ - qemu_log_mask(LOG_UNIMP, "%s access to unsupported AArch64 " + qemu_log_mask(LOG_UNIMP, "%s%s access to unsupported AArch64 " "system register op0:%d op1:%d crn:%d crm:%d op2:%d\= n", - isread ? "read" : "write", op0, op1, crn, crm, op2); + isread ? "read" : "write", is128 ? "128" : "", + op0, op1, crn, crm, op2); gen_sysreg_undef(s, isread, op0, op1, op2, crn, crm, rt); return; } @@ -2636,7 +2653,7 @@ static void handle_sys(DisasContext *s, bool isread, * We don't use the EL1 register's access function, and * fine-grained-traps on EL1 also do not apply here. */ - key =3D ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2); + key &=3D ~CP_REG_ARM64_SYSREG_OP1_MASK; ri =3D redirect_cpreg(s, key, isread); /* * We might not have done an update_pc earlier, so check we don't @@ -2651,32 +2668,44 @@ static void handle_sys(DisasContext *s, bool isread, * This means it is not an IO operation, doesn't change hflags, * and need not end the TB, because it has no side effects. * - * The access is 64-bit single copy atomic, guaranteed aligned bec= ause - * of the definition of VCNR_EL2. Its endianness depends on - * SCTLR_EL2.EE, not on the data endianness of EL1. - * It is done under either the EL2 translation regime or the EL2&0 - * translation regime, depending on HCR_EL2.E2H. It behaves as if - * PSTATE.PAN is 0. + * The access is 64-bit (R_VFMQB) or 128-bit (R_BSBZP) single copy + * atomic, guaranteed aligned because of the definition of VCNR_EL= 2. + * Its endianness depends on SCTLR_EL2.EE, not on the data endiann= ess + * of EL1. It is done under either the EL2 translation regime or + * the EL2&0 translation regime, depending on HCR_EL2.E2H. + * It behaves as if PSTATE.PAN is 0. */ TCGv_i64 ptr =3D tcg_temp_new_i64(); - MemOp mop =3D MO_64 | MO_ALIGN | MO_ATOM_IFALIGN; + MemOp mop =3D MO_ALIGN | MO_ATOM_IFALIGN; ARMMMUIdx armmemidx =3D s->nv2_mem_e20 ? ARMMMUIdx_E20_2 : ARMMMUI= dx_E2; int memidx =3D arm_to_core_mmu_idx(armmemidx); - uint32_t syn; =20 mop |=3D (s->nv2_mem_be ? MO_BE : MO_LE); + disas_set_insn_syndrome(s, syn_data_abort_vncr(0, !isread, 0)); =20 tcg_gen_ld_i64(ptr, tcg_env, offsetof(CPUARMState, cp15.vncr_el2)); tcg_gen_addi_i64(ptr, ptr, (ri->nv2_redirect_offset & ~NV2_REDIR_FLAG_MASK)); - tcg_rt =3D cpu_reg(s, rt); =20 - syn =3D syn_data_abort_vncr(0, !isread, 0); - disas_set_insn_syndrome(s, syn); - if (isread) { - tcg_gen_qemu_ld_i64(tcg_rt, ptr, memidx, mop); + if (is128) { + TCGv_i128 t128 =3D tcg_temp_new_i128(); + + mop |=3D MO_128; + if (isread) { + tcg_gen_qemu_ld_i128(t128, ptr, memidx, mop); + tcg_gen_extr_i128_i64(cpu_reg(s, rt), cpu_reg(s, rt2), t12= 8); + } else { + tcg_gen_concat_i64_i128(t128, cpu_reg(s, rt), cpu_reg(s, r= t2)); + tcg_gen_qemu_st_i128(t128, ptr, memidx, mop); + } } else { - tcg_gen_qemu_st_i64(tcg_rt, ptr, memidx, mop); + mop |=3D MO_64; + tcg_rt =3D cpu_reg(s, rt); + if (isread) { + tcg_gen_qemu_ld_i64(tcg_rt, ptr, memidx, mop); + } else { + tcg_gen_qemu_st_i64(tcg_rt, ptr, memidx, mop); + } } return; } @@ -2772,28 +2801,56 @@ static void handle_sys(DisasContext *s, bool isread, =20 tcg_rt =3D cpu_reg(s, rt); =20 - if (isread) { - if (ri->type & ARM_CP_CONST) { - tcg_gen_movi_i64(tcg_rt, ri->resetvalue); - } else if (ri->readfn) { - if (!tcg_ri) { - tcg_ri =3D gen_lookup_cp_reg(key); + if (is128) { + TCGv_i64 tcg_rt2 =3D cpu_reg(s, rt2); + TCGv_i128 t128 =3D tcg_temp_new_i128(); + + assert(!(ri->type & ARM_CP_CONST)); + if (isread) { + if (ri->read128fn) { + if (!tcg_ri) { + tcg_ri =3D gen_lookup_cp_reg(key); + } + gen_helper_get_cp_reg128(t128, tcg_env, tcg_ri); + } else { + tcg_gen_ld_i128(t128, tcg_env, ri->fieldoffset); } - gen_helper_get_cp_reg64(tcg_rt, tcg_env, tcg_ri); + tcg_gen_extr_i128_i64(tcg_rt, tcg_rt2, t128); } else { - tcg_gen_ld_i64(tcg_rt, tcg_env, ri->fieldoffset); + tcg_gen_concat_i64_i128(t128, tcg_rt, tcg_rt2); + if (ri->write128fn) { + if (!tcg_ri) { + tcg_ri =3D gen_lookup_cp_reg(key); + } + gen_helper_set_cp_reg128(tcg_env, tcg_ri, t128); + } else { + tcg_gen_st_i128(t128, tcg_env, ri->fieldoffset); + } } } else { - if (ri->type & ARM_CP_CONST) { - /* If not forbidden by access permissions, treat as WI */ - return; - } else if (ri->writefn) { - if (!tcg_ri) { - tcg_ri =3D gen_lookup_cp_reg(key); + if (isread) { + if (ri->type & ARM_CP_CONST) { + tcg_gen_movi_i64(tcg_rt, ri->resetvalue); + } else if (ri->readfn) { + if (!tcg_ri) { + tcg_ri =3D gen_lookup_cp_reg(key); + } + gen_helper_get_cp_reg64(tcg_rt, tcg_env, tcg_ri); + } else { + tcg_gen_ld_i64(tcg_rt, tcg_env, ri->fieldoffset); } - gen_helper_set_cp_reg64(tcg_env, tcg_ri, tcg_rt); } else { - tcg_gen_st_i64(tcg_rt, tcg_env, ri->fieldoffset); + if (ri->type & ARM_CP_CONST) { + /* If not forbidden by access permissions, treat as WI */ + return; + } else if (ri->writefn) { + if (!tcg_ri) { + tcg_ri =3D gen_lookup_cp_reg(key); + } + gen_helper_set_cp_reg64(tcg_env, tcg_ri, tcg_rt); + } else { + tcg_gen_st_i64(tcg_rt, tcg_env, ri->fieldoffset); + } } } =20 @@ -2817,7 +2874,34 @@ static void handle_sys(DisasContext *s, bool isread, =20 static bool trans_SYS(DisasContext *s, arg_SYS *a) { - handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt); + handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt, 0); + return true; +} + +static bool trans_SYS128(DisasContext *s, arg_sys *a) +{ + if (!dc_isar_feature(aa64_sysreg128, s) || (a->rt & 1)) { + return false; + } + handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, + a->rt, a->rt + 1); + return true; +} + +static bool trans_SYSP(DisasContext *s, arg_sys *a) +{ + int rt2; + if (!dc_isar_feature(aa64_sysinstr128, s)) { + return false; + } + if (a->rt =3D=3D 31) { + rt2 =3D 31; + } else if (a->rt & 1) { + return false; + } else { + rt2 =3D a->rt + 1; + } + handle_sys(s, a->l, a->op0, a->op1, a->op2, a->crn, a->crm, a->rt, rt2= ); return true; } =20 diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8c798cde2b..ef9086b6fe 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -290,9 +290,15 @@ MSR_i_SVCR 1101 0101 0000 0 011 0100 0 mask:2 imm= :1 011 11111 # same instruction as far as QEMU is concerned. # NB: op0 is bits [20:19], but op0=3D0b00 is other insns, so we have # to hand-decode it. -SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D1 -SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D2 -SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 op0=3D3 +&sys l op0 op1 op2 crn crm rt +SYS 1101 0101 00 l:1 01 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0= =3D1 +SYS 1101 0101 00 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0= =3D2 +SYS 1101 0101 00 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0= =3D3 + +# MRRS, MSRR +SYS128 1101 0101 01 l:1 10 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0= =3D2 +SYS128 1101 0101 01 l:1 11 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0= =3D3 +SYSP 1101 0101 01 0 01 op1:3 crn:4 crm:4 op2:3 rt:5 &sys op0= =3D1 l=3D0 =20 # Exception generation =20 --=20 2.43.0