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Clear the fields within add_cpreg_to_hashtable_aa32. Create the FOO_EL12 cpreg within add_cpreg_to_hashtable_aa64; add ARM_CP_NO_RAW. Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 6 +- target/arm/helper.c | 241 ++++++++++++++++++-------------------------- 2 files changed, 103 insertions(+), 144 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index f5d6a1c386..9818be4429 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -918,8 +918,10 @@ struct ARMCPRegInfo { uint32_t vhe_redir_to_el2; =20 /* - * With VHE, with E2H, at EL2+, access to this EL02/EL12 reg - * redirects to the EL0/EL1 reg with the specified key. + * For VHE. Before registration, this field holds the key for an + * EL02/EL12 reg to be created to point back to this EL0/EL1 reg. + * After registration, this field is set only on the EL02/EL12 reg + * and points back to the EL02/EL12 reg for redirection with E2H. */ uint32_t vhe_redir_to_el01; =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 255ca6fdcb..64a987d143 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -454,6 +454,8 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_CONTEXTIDR_EL1, .nv2_redirect_offset =3D 0x108 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 13, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 13, 0, 1), .secure =3D ARM_CP_SECSTATE_NS, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[1]), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, @@ -674,6 +676,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { { .name =3D "CPACR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .fgt =3D FGT_CPACR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 1, 2), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 2), .nv2_redirect_offset =3D 0x100 | NV2_REDIR_NV1, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, @@ -950,12 +954,16 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AFSR0_EL1, .nv2_redirect_offset =3D 0x128 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 1, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 1, 0), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "AFSR1_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AFSR1_EL1, .nv2_redirect_offset =3D 0x130 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 1, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 1, 1), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* * MAIR can just read-as-written because we don't implement caches @@ -966,6 +974,8 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_MAIR_EL1, .nv2_redirect_offset =3D 0x140 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 10, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 10, 2, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.mair_el[1]), .resetvalue =3D 0 }, { .name =3D "MAIR_EL3", .state =3D ARM_CP_STATE_AA64, @@ -2015,6 +2025,8 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { { .name =3D "CNTKCTL_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, .access =3D PL1_RW, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 14, 1, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 14, 1, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.c14_cntkctl), .resetvalue =3D 0, }, @@ -2805,6 +2817,8 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_FAR_EL1, .nv2_redirect_offset =3D 0x220 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 6, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 6, 0, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, }; @@ -2815,12 +2829,16 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_ESR_EL1, .nv2_redirect_offset =3D 0x138 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 2, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.esr_el[1]), .resetvalue = =3D 0, }, { .name =3D "TTBR0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR0_EL1, .nv2_redirect_offset =3D 0x200 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 0), .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr0_s), offsetof(CPUARMState, cp15.ttbr0_ns) } }, @@ -2829,6 +2847,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TTBR1_EL1, .nv2_redirect_offset =3D 0x210 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 1), .writefn =3D vmsa_ttbr_write, .resetvalue =3D 0, .raw_writefn =3D ra= w_write, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) } }, @@ -2837,6 +2857,8 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_TCR_EL1, .nv2_redirect_offset =3D 0x120 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 2, 0, 2), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 2, 0, 2), .writefn =3D vmsa_tcr_el12_write, .raw_writefn =3D raw_write, .resetvalue =3D 0, @@ -3077,6 +3099,8 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_AMAIR_EL1, .nv2_redirect_offset =3D 0x148 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 10, 3, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 10, 3, 0), .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, /* AMAIR1 is mapped to AMAIR_EL1[63:32] */ { .name =3D "AMAIR1", .cp =3D 15, .crn =3D 10, .crm =3D 3, .opc1 =3D 0= , .opc2 =3D 1, @@ -3602,12 +3626,16 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .accessfn =3D access_nv1, .nv2_redirect_offset =3D 0x230 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 4, 0, 1), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 4, 0, 1), .fieldoffset =3D offsetof(CPUARMState, elr_el[1]) }, { .name =3D "SPSR_EL1", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 4, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_nv1, .nv2_redirect_offset =3D 0x160 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 4, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 4, 0, 0), .fieldoffset =3D offsetof(CPUARMState, banked_spsr[BANK_SVC]) }, /* * We rely on the access checks not allowing the guest to write to the @@ -4440,138 +4468,6 @@ static CPAccessResult access_el1nvvct(CPUARMState *= env, const ARMCPRegInfo *ri, } return e2h_access(env, ri, isread); } - -static void define_arm_vh_e2h_redirects_aliases(ARMCPU *cpu) -{ - struct E2HAlias { - uint32_t src_key, dst_key, new_key; - const char *src_name, *dst_name, *new_name; - bool (*feature)(const ARMISARegisters *id); - }; - -#define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) - - static const struct E2HAlias aliases[] =3D { - { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), - "SCTLR_EL1", "SCTLR_EL2", "SCTLR_EL12" }, - { K(3, 0, 1, 0, 2), K(3, 4, 1, 1, 2), K(3, 5, 1, 0, 2), - "CPACR_EL1", "CPTR_EL2", "CPACR_EL12" }, - { K(3, 0, 2, 0, 0), K(3, 4, 2, 0, 0), K(3, 5, 2, 0, 0), - "TTBR0_EL1", "TTBR0_EL2", "TTBR0_EL12" }, - { K(3, 0, 2, 0, 1), K(3, 4, 2, 0, 1), K(3, 5, 2, 0, 1), - "TTBR1_EL1", "TTBR1_EL2", "TTBR1_EL12" }, - { K(3, 0, 2, 0, 2), K(3, 4, 2, 0, 2), K(3, 5, 2, 0, 2), - "TCR_EL1", "TCR_EL2", "TCR_EL12" }, - { K(3, 0, 4, 0, 0), K(3, 4, 4, 0, 0), K(3, 5, 4, 0, 0), - "SPSR_EL1", "SPSR_EL2", "SPSR_EL12" }, - { K(3, 0, 4, 0, 1), K(3, 4, 4, 0, 1), K(3, 5, 4, 0, 1), - "ELR_EL1", "ELR_EL2", "ELR_EL12" }, - { K(3, 0, 5, 1, 0), K(3, 4, 5, 1, 0), K(3, 5, 5, 1, 0), - "AFSR0_EL1", "AFSR0_EL2", "AFSR0_EL12" }, - { K(3, 0, 5, 1, 1), K(3, 4, 5, 1, 1), K(3, 5, 5, 1, 1), - "AFSR1_EL1", "AFSR1_EL2", "AFSR1_EL12" }, - { K(3, 0, 5, 2, 0), K(3, 4, 5, 2, 0), K(3, 5, 5, 2, 0), - "ESR_EL1", "ESR_EL2", "ESR_EL12" }, - { K(3, 0, 6, 0, 0), K(3, 4, 6, 0, 0), K(3, 5, 6, 0, 0), - "FAR_EL1", "FAR_EL2", "FAR_EL12" }, - { K(3, 0, 10, 2, 0), K(3, 4, 10, 2, 0), K(3, 5, 10, 2, 0), - "MAIR_EL1", "MAIR_EL2", "MAIR_EL12" }, - { K(3, 0, 10, 3, 0), K(3, 4, 10, 3, 0), K(3, 5, 10, 3, 0), - "AMAIR_EL1", "AMAIR_EL2", "AMAIR_EL12" }, - { K(3, 0, 12, 0, 0), K(3, 4, 12, 0, 0), K(3, 5, 12, 0, 0), - "VBAR_EL1", "VBAR_EL2", "VBAR_EL12" }, - { K(3, 0, 13, 0, 1), K(3, 4, 13, 0, 1), K(3, 5, 13, 0, 1), - "CONTEXTIDR_EL1", "CONTEXTIDR_EL2", "CONTEXTIDR_EL12" }, - { K(3, 0, 14, 1, 0), K(3, 4, 14, 1, 0), K(3, 5, 14, 1, 0), - "CNTKCTL_EL1", "CNTHCTL_EL2", "CNTKCTL_EL12" }, - - /* - * Note that redirection of ZCR is mentioned in the description - * of ZCR_EL2, and aliasing in the description of ZCR_EL1, but - * not in the summary table. - */ - { K(3, 0, 1, 2, 0), K(3, 4, 1, 2, 0), K(3, 5, 1, 2, 0), - "ZCR_EL1", "ZCR_EL2", "ZCR_EL12", isar_feature_aa64_sve }, - { K(3, 0, 1, 2, 6), K(3, 4, 1, 2, 6), K(3, 5, 1, 2, 6), - "SMCR_EL1", "SMCR_EL2", "SMCR_EL12", isar_feature_aa64_sme }, - - { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), - "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, - - { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), - "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", - isar_feature_aa64_scxtnum }, - - /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ - /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ - }; -#undef K - - size_t i; - - for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { - const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg, *new_reg; - bool ok; - - if (a->feature && !a->feature(&cpu->isar)) { - continue; - } - - src_reg =3D g_hash_table_lookup(cpu->cp_regs, - (gpointer)(uintptr_t)a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, - (gpointer)(uintptr_t)a->dst_key); - g_assert(src_reg !=3D NULL); - g_assert(dst_reg !=3D NULL); - - /* Cross-compare names to detect typos in the keys. */ - g_assert(strcmp(src_reg->name, a->src_name) =3D=3D 0); - g_assert(strcmp(dst_reg->name, a->dst_name) =3D=3D 0); - - /* Create alias before redirection so we dup the right data. */ - new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); - - new_reg->name =3D a->new_name; - new_reg->type |=3D ARM_CP_ALIAS; - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ - new_reg->access &=3D PL2_RW | PL3_RW; - /* The new_reg op fields are as per new_key, not the target reg */ - new_reg->crn =3D (a->new_key & CP_REG_ARM64_SYSREG_CRN_MASK) - >> CP_REG_ARM64_SYSREG_CRN_SHIFT; - new_reg->crm =3D (a->new_key & CP_REG_ARM64_SYSREG_CRM_MASK) - >> CP_REG_ARM64_SYSREG_CRM_SHIFT; - new_reg->opc0 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP0_MASK) - >> CP_REG_ARM64_SYSREG_OP0_SHIFT; - new_reg->opc1 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP1_MASK) - >> CP_REG_ARM64_SYSREG_OP1_SHIFT; - new_reg->opc2 =3D (a->new_key & CP_REG_ARM64_SYSREG_OP2_MASK) - >> CP_REG_ARM64_SYSREG_OP2_SHIFT; - new_reg->vhe_redir_to_el01 =3D a->src_key; - new_reg->readfn =3D NULL; - new_reg->writefn =3D NULL; - new_reg->accessfn =3D NULL; - new_reg->fieldoffset =3D 0; - - /* - * If the _EL1 register is redirected to memory by FEAT_NV2, - * then it shares the offset with the _EL12 register, - * and which one is redirected depends on HCR_EL2.NV1. - */ - if (new_reg->nv2_redirect_offset) { - assert(new_reg->nv2_redirect_offset & NV2_REDIR_NV1); - new_reg->nv2_redirect_offset &=3D ~NV2_REDIR_NV1; - new_reg->nv2_redirect_offset |=3D NV2_REDIR_NO_NV1; - } - - ok =3D g_hash_table_insert(cpu->cp_regs, - (gpointer)(uintptr_t)a->new_key, new_reg); - g_assert(ok); - - src_reg->vhe_redir_to_el2 =3D a->dst_key; - } -} #endif =20 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -4864,6 +4760,8 @@ static const ARMCPRegInfo zcr_reginfo[] =3D { { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, .nv2_redirect_offset =3D 0x1e0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 2, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 2, 0), .access =3D PL1_RW, .type =3D ARM_CP_SVE, .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), .writefn =3D zcr_write, .raw_writefn =3D raw_write }, @@ -5009,6 +4907,8 @@ static const ARMCPRegInfo sme_reginfo[] =3D { { .name =3D "SMCR_EL1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 6, .nv2_redirect_offset =3D 0x1f0 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 2, 6), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 2, 6), .access =3D PL1_RW, .type =3D ARM_CP_SME, .fieldoffset =3D offsetof(CPUARMState, vfp.smcr_el[1]), .writefn =3D smcr_write, .raw_writefn =3D raw_write }, @@ -5454,6 +5354,8 @@ static const ARMCPRegInfo mte_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 6, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tfsr_el1, .nv2_redirect_offset =3D 0x190 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 5, 6, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 5, 6, 0), .fieldoffset =3D offsetof(CPUARMState, cp15.tfsr_el[1]) }, { .name =3D "TFSR_EL2", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_NV2_REDIRECT, @@ -5629,6 +5531,8 @@ static const ARMCPRegInfo scxtnum_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_scxtnum_el1, .fgt =3D FGT_SCXTNUM_EL1, .nv2_redirect_offset =3D 0x188 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 13, 0, 7), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 13, 0, 7), .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, @@ -7005,6 +6909,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .accessfn =3D access_nv1, .fgt =3D FGT_VBAR_EL1, .nv2_redirect_offset =3D 0x250 | NV2_REDIR_NV1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 12, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 12, 0, 0), .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, @@ -7019,6 +6925,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fgt =3D FGT_SCTLR_EL1, + .vhe_redir_to_el2 =3D ENCODE_AA64_CP_REG(3, 4, 1, 0, 0), + .vhe_redir_to_el01 =3D ENCODE_AA64_CP_REG(3, 5, 1, 0, 0), .nv2_redirect_offset =3D 0x110 | NV2_REDIR_NV1, .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.sctlr_s), offsetof(CPUARMState, cp15.sctlr_ns) }, @@ -7153,16 +7061,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 define_pm_cpregs(cpu); - -#ifndef CONFIG_USER_ONLY - /* - * Register redirections and aliases must be done last, - * after the registers from the other extensions have been defined. - */ - if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { - define_arm_vh_e2h_redirects_aliases(cpu); - } -#endif } =20 /* @@ -7295,6 +7193,8 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, = ARMCPRegInfo *r) r->crm, r->opc1, r->opc2); =20 assert(!(r->type & ARM_CP_ADD_TLBI_NXS)); /* aa64 only */ + r->vhe_redir_to_el2 =3D 0; + r->vhe_redir_to_el01 =3D 0; =20 switch (r->secure) { case ARM_CP_SECSTATE_NS: @@ -7348,6 +7248,63 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu,= ARMCPRegInfo *r) ARM_CP_SECSTATE_NS, nxs_key); } =20 + if (!r->vhe_redir_to_el01) { + assert(!r->vhe_redir_to_el2); + } else if (!arm_feature(&cpu->env, ARM_FEATURE_EL2) || + !cpu_isar_feature(aa64_vh, cpu)) { + r->vhe_redir_to_el2 =3D 0; + r->vhe_redir_to_el01 =3D 0; + } else { + /* Create the FOO_EL12 alias. */ + ARMCPRegInfo *r2 =3D alloc_cpreg(r, "2"); + uint32_t key2 =3D r->vhe_redir_to_el01; + + /* + * Clear EL1 redirection on the FOO_EL1 reg; + * Clear EL2 redirection on the FOO_EL12 reg; + * Install redirection from FOO_EL12 back to FOO_EL1. + */ + r->vhe_redir_to_el01 =3D 0; + r2->vhe_redir_to_el2 =3D 0; + r2->vhe_redir_to_el01 =3D key; + + r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_RAW; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + r2->access &=3D PL2_RW | PL3_RW; + /* The new_reg op fields are as per new_key, not the target reg */ + r2->crn =3D (key2 & CP_REG_ARM64_SYSREG_CRN_MASK) + >> CP_REG_ARM64_SYSREG_CRN_SHIFT; + r2->crm =3D (key2 & CP_REG_ARM64_SYSREG_CRM_MASK) + >> CP_REG_ARM64_SYSREG_CRM_SHIFT; + r2->opc0 =3D (key2 & CP_REG_ARM64_SYSREG_OP0_MASK) + >> CP_REG_ARM64_SYSREG_OP0_SHIFT; + r2->opc1 =3D (key2 & CP_REG_ARM64_SYSREG_OP1_MASK) + >> CP_REG_ARM64_SYSREG_OP1_SHIFT; + r2->opc2 =3D (key2 & CP_REG_ARM64_SYSREG_OP2_MASK) + >> CP_REG_ARM64_SYSREG_OP2_SHIFT; + + /* Non-redirected access to this register will abort. */ + r2->readfn =3D NULL; + r2->writefn =3D NULL; + r2->raw_readfn =3D NULL; + r2->raw_writefn =3D NULL; + r2->accessfn =3D NULL; + r2->fieldoffset =3D 0; + + /* + * If the _EL1 register is redirected to memory by FEAT_NV2, + * then it shares the offset with the _EL12 register, + * and which one is redirected depends on HCR_EL2.NV1. + */ + if (r2->nv2_redirect_offset) { + assert(r2->nv2_redirect_offset & NV2_REDIR_NV1); + r2->nv2_redirect_offset &=3D ~NV2_REDIR_NV1; + r2->nv2_redirect_offset |=3D NV2_REDIR_NO_NV1; + } + add_cpreg_to_hashtable(cpu, r2, ARM_CP_STATE_AA64, + ARM_CP_SECSTATE_NS, key2); + } + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, key); } --=20 2.43.0