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([144.6.121.55]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7720274534esm1419241b3a.47.2025.08.26.18.07.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 18:07:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756256848; x=1756861648; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=0m53HPKD6Du3PeyFjN/hMU96ykTHL6/3IH+CJFSfXbY=; b=NzRwaF0OhR2SnatAesC5zsuJb7cIFdbx9O1ybyIor44R3i9YktDOQOL2wcku3zU/8b mSJVOl9Yur5E8z6S1WomRBT34DELyddYLyeHpqsN7VbwEyjT4s4ewyxIKvJaKOm9U+ED h3BWhr61xM3MddeDM98QxE8HltPYPj4FfA9W/fCrwYkrlGepJ149XubXM2hCHTJvnihN C+E7IUZ2TCCw/jyLNqETygnhgrpcq975UlJDOGB983KQnEcs5/wQ8AWRi1OIU2DyHH0h dRJAVKN1+27dpvWkV+LAjQIFHp2npsGR+39UgBuWMZSo40Ufso8zWe+mLLz4n4WPucZt k9Yw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756256848; x=1756861648; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0m53HPKD6Du3PeyFjN/hMU96ykTHL6/3IH+CJFSfXbY=; b=j8slGPBuapfFedzrdW6pGGn+PkUbM4zrUZM4+KXKpC9LVY1UINlo2ghceRBTeu2mQL CRTiPLk6FpQdFO7AMsZnX43ZhAjWcHhlAf1n7v6XhLFk0UEjShe45RUzyMU7W9o2mPWf DKwbDJIcHuJwSRif8lLy0lTcI+MvWkEGv1lUDBTLYzfCk+ZCxQqr2W4EsVKidrbfYlFk d2mn9ULWkz+pMaXsZTNftOjBXfu2rlUtSfttmm10dg4qaWTy6jnvtJFftRq0rtvc5X9L gEyOWYzKniBA4IUdpN16AUvNshHrdCO2p5B7WnVVckdm7yGVTyO1oVnXhB4pgY0MHI5X e2sw== X-Gm-Message-State: AOJu0YwYFusKW6TIpBhVtNFVUrRp4NunkSzRs9v6VdbtusRngDUN8zIR VAsl2adCnbAOE8akQwwO+6ceEvxlfjkBW8uiMIZwrerKZubfrl71EGW6r1TmpjgK+lwOygNtUXJ NYVqGkXo= X-Gm-Gg: ASbGnculaCTO9vH3BQc875cS0BQVcrS54V0No1sLv2LKRW3aOW1u2GYOcsO64DKo7z1 H9iuvPZKswK/fmFUX+HWoqXpiNh33Qw7LJLZ5MYjwKonARv3Uw3irrDuvq27E0CjXJ07I8daUEm a6zemmgvsA+Pe/TPsMUOXOlxV9+QhNU3DxAPFvhV5guD6h8LIRmnvFGfp+snAmazwd6Opb0I5F+ LVt8b50EH3ZwhfGBfxGBXXhGovdQkHz8LROFI90YAONUxusY/Qff/QRMrUQbyL8beIp2f29ZOZZ FDKqWBR6NFHtM9GUbLUfzvHfMla3JGYHGCU3bbjg86lE+5Y6ShFu0RwPEDaYsyZYqrKdXqB8s6y tSL+9RyKfF0AAAknhkCIXCtyogQ== X-Google-Smtp-Source: AGHT+IH0OFkMttbU+X7btvbDDLaBqLBq7hos/HyPoN7kSFGx0aCLM0R/kTGRuiOrs8FA+8GgOarKYg== X-Received: by 2002:a17:90b:3d89:b0:31e:f397:b5b4 with SMTP id 98e67ed59e1d1-3251744bd7amr21249738a91.22.1756256848166; Tue, 26 Aug 2025 18:07:28 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 26/61] target/arm: Hoist the allocation of ARMCPRegInfo Date: Wed, 27 Aug 2025 11:04:17 +1000 Message-ID: <20250827010453.4059782-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250827010453.4059782-1-richard.henderson@linaro.org> References: <20250827010453.4059782-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756257110684116601 Content-Type: text/plain; charset="utf-8" Pass in a newly allocated structure, rather than having to dance around allocation of the name and the structure. Since we no longer have two copies of the structure handy within add_cpreg_to_hashtable, delay the writeback of concrete values over wildcards until we're done querying the wildcards. Signed-off-by: Richard Henderson --- target/arm/helper.c | 97 ++++++++++++++++++++++----------------------- 1 file changed, 48 insertions(+), 49 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 0e4be14606..d9ac6a20a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7289,13 +7289,12 @@ static ARMCPRegInfo *alloc_cpreg(const ARMCPRegInfo= *in, * Private utility function for define_one_arm_cp_reg(): * add a single reginfo struct to the hash table. */ -static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable(ARMCPU *cpu, ARMCPRegInfo *r, CPState state, CPSecureState secstate, int cp, int crm, int opc1, int opc2, - const char *name, uint32_t key) + uint32_t key) { CPUARMState *env =3D &cpu->env; - ARMCPRegInfo *r2; bool ns =3D secstate & ARM_CP_SECSTATE_NS; =20 /* Overriding of an existing definition must be explicitly requested. = */ @@ -7306,19 +7305,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - r2 =3D alloc_cpreg(r, name, NULL); - - /* - * Update fields to match the instantiation, overwiting wildcards - * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. - */ - r2->cp =3D cp; - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; - r2->state =3D state; - r2->secure =3D secstate; - { bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 @@ -7328,7 +7314,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + r->fieldoffset =3D r->bank_fieldoffsets[ns]; } if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { @@ -7345,19 +7331,19 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, */ if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || (arm_feature(env, ARM_FEATURE_V8) && !ns)) { - r2->type |=3D ARM_CP_ALIAS; + r->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { /* * The register is not banked so we only want to allow * migration of the non-secure instance. */ - r2->type |=3D ARM_CP_ALIAS; + r->type |=3D ARM_CP_ALIAS; } =20 if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); + r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { + r->fieldoffset +=3D sizeof(uint32_t); } } } @@ -7369,35 +7355,46 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if (r2->type & ARM_CP_SPECIAL_MASK) { - r2->type |=3D ARM_CP_NO_RAW; + if (r->type & ARM_CP_SPECIAL_MASK) { + r->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { - r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; + r->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 + /* + * Update fields to match the instantiation, overwiting wildcards + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. + */ + r->cp =3D cp; + r->crm =3D crm; + r->opc1 =3D opc1; + r->opc2 =3D opc2; + r->state =3D state; + r->secure =3D secstate; + /* * Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. */ - if (!(r2->type & ARM_CP_NO_RAW)) { - assert(!raw_accessors_invalid(r2)); + if (!(r->type & ARM_CP_NO_RAW)) { + assert(!raw_accessors_invalid(r)); } =20 - g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r); } =20 -static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, ARMCPRegInfo *r, int cp, int crm, int opc1, int opc= 2) { /* * Under AArch32 CP registers can be common * (same for secure and non-secure world) or banked. */ - char *name; + ARMCPRegInfo *r_s; bool is64 =3D r->type & ARM_CP_64BIT; uint32_t key =3D ENCODE_CP_REG(cp, is64, 0, r->crn, crm, opc1, opc2); =20 @@ -7409,24 +7406,23 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, /* fall through */ case ARM_CP_SECSTATE_S: add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, - cp, crm, opc1, opc2, r->name, key); + cp, crm, opc1, opc2, key); break; case ARM_CP_SECSTATE_BOTH: - name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, - cp, crm, opc1, opc2, name, key); - g_free(name); + r_s =3D alloc_cpreg(r, r->name, "_S"); + add_cpreg_to_hashtable(cpu, r_s, ARM_CP_STATE_AA32, ARM_CP_SECSTAT= E_S, + cp, crm, opc1, opc2, key); =20 key |=3D CP_REG_AA32_NS_MASK; add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, - cp, crm, opc1, opc2, r->name, key); + cp, crm, opc1, opc2, key); break; default: g_assert_not_reached(); } } =20 -static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, const ARMCPRegInfo *r, +static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu, ARMCPRegInfo *r, int crm, int opc1, int opc2) { uint32_t key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); @@ -7443,24 +7439,23 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, * and name that it is passed, so it's OK to use * a local struct here. */ - ARMCPRegInfo nxs_ri =3D *r; - g_autofree char *name =3D g_strdup_printf("%sNXS", r->name); + ARMCPRegInfo *nxs_ri =3D alloc_cpreg(r, r->name, "NXS"); uint32_t nxs_key; =20 - assert(nxs_ri.crn < 0xf); - nxs_ri.crn++; + assert(nxs_ri->crn < 0xf); + nxs_ri->crn++; nxs_key =3D key + (1 << CP_REG_ARM64_SYSREG_CRN_SHIFT); - if (nxs_ri.fgt) { - nxs_ri.fgt |=3D R_FGT_NXS_MASK; + if (nxs_ri->fgt) { + nxs_ri->fgt |=3D R_FGT_NXS_MASK; } =20 - add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, + add_cpreg_to_hashtable(cpu, nxs_ri, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, - name, nxs_key); + nxs_key); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - 0, crm, opc1, opc2, r->name, key); + 0, crm, opc1, opc2, key); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7667,16 +7662,20 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) for (int crm =3D crmmin; crm <=3D crmmax; crm++) { for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { + ARMCPRegInfo *r2 =3D alloc_cpreg(r, r->name, NULL); + ARMCPRegInfo *r3; + switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); + add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); break; case ARM_CP_STATE_AA64: - add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa64(cpu, r2, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); - add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); + r3 =3D alloc_cpreg(r2, r2->name, NULL); + add_cpreg_to_hashtable_aa32(cpu, r2, cp, crm, opc1, op= c2); + add_cpreg_to_hashtable_aa64(cpu, r3, crm, opc1, opc2); break; default: g_assert_not_reached(); --=20 2.43.0