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Signed-off-by: Richard Henderson --- target/arm/helper.c | 123 +++++++++++++++++++++++--------------------- 1 file changed, 64 insertions(+), 59 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a9d6ed1270..02c155418b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7278,7 +7278,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; size_t name_len; - bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -7299,32 +7298,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 - /* - * Eliminate registers that are not present because the EL is missing. - * Doing this here makes it easier to put all registers for a given - * feature into the same ARMCPRegInfo array and define them all at onc= e. - */ - make_const =3D false; - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* - * An EL2 register without EL2 but with EL3 is (usually) RES0. - * See rule RJFFP in section D1.1.3 of DDI0487H.a. - */ - int min_el =3D ctz32(r->access) / 2; - if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { - if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { - return; - } - make_const =3D !(r->type & ARM_CP_EL3_NO_EL2_KEEP); - } - } else { - CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) - ? PL2_RW : PL1_RW); - if ((r->access & max_el) =3D=3D 0) { - return; - } - } - /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -7342,38 +7315,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, r2->state =3D state; r2->secure =3D secstate; =20 - if (make_const) { - /* This should not have been a very special register to begin. */ - int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; - assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_NOP); - /* - * Set the special function to CONST, retaining the other flags. - * This is important for e.g. ARM_CP_SVE so that we still - * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. - */ - r2->type =3D (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; - /* - * Usually, these registers become RES0, but there are a few - * special cases like VPIDR_EL2 which have a constant non-zero - * value with writes ignored. - */ - if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { - r2->resetvalue =3D 0; - } - /* - * ARM_CP_CONST has precedence, so removing the callbacks and - * offsets are not strictly necessary, but it is potentially - * less confusing to debug later. - */ - r2->readfn =3D NULL; - r2->writefn =3D NULL; - r2->raw_readfn =3D NULL; - r2->raw_writefn =3D NULL; - r2->resetfn =3D NULL; - r2->fieldoffset =3D 0; - r2->bank_fieldoffsets[0] =3D 0; - r2->bank_fieldoffsets[1] =3D 0; - } else { + { bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 if (isbanked) { @@ -7538,6 +7480,8 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; int cp =3D r->cp; + ARMCPRegInfo r_const; + CPUARMState *env =3D &cpu->env; =20 /* * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. @@ -7643,6 +7587,67 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPR= egInfo *r) } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * An EL2 register without EL2 but with EL3 is (usually) RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + int min_el =3D ctz32(r->access) / 2; + if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { + return; + } + if (!(r->type & ARM_CP_EL3_NO_EL2_KEEP)) { + /* This should not have been a very special register. */ + int old_special =3D r->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_N= OP); + + r_const =3D *r; + + /* + * Set the special function to CONST, retaining the other = flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. + */ + r_const.type =3D (r->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP= _CONST; + /* + * Usually, these registers become RES0, but there are a f= ew + * special cases like VPIDR_EL2 which have a constant non-= zero + * value with writes ignored. + */ + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { + r_const.resetvalue =3D 0; + } + /* + * ARM_CP_CONST has precedence, so removing the callbacks = and + * offsets are not strictly necessary, but it is potential= ly + * less confusing to debug later. + */ + r_const.readfn =3D NULL; + r_const.writefn =3D NULL; + r_const.raw_readfn =3D NULL; + r_const.raw_writefn =3D NULL; + r_const.resetfn =3D NULL; + r_const.fieldoffset =3D 0; + r_const.bank_fieldoffsets[0] =3D 0; + r_const.bank_fieldoffsets[1] =3D 0; + + r =3D &r_const; + } + } + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? PL2_RW : PL1_RW); + if ((r->access & max_el) =3D=3D 0) { + return; + } + } + for (int crm =3D crmmin; crm <=3D crmmax; crm++) { for (int opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { --=20 2.43.0