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([144.6.121.55]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7720274534esm1419241b3a.47.2025.08.26.18.06.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 18:07:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756256823; x=1756861623; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PiTlSDbl7ZE2Kdnr9r+qg6Y8XwHKnrFV6OAAtT3qX4s=; b=vaMCFL7+ZVFuuLoZeC3wFPiZXckN07/iN0qm9H36lTErZW2MaTk9HTg8HTaNLfrMAI LnckHPPm/gk2kwqRTfMDuetD1QULE8u5mjzosBKM/0svWS4KPRU39avCj2/r3mWRFly3 +r0v/Z4V2gl7TUBOBR64zTVxKQI7cAALRwA7bHcLIGpIims8Q3ZQ0NRQqJ7uvHjxERQA c7QyWA7feZ2VpgUUDMs7vdaPB3ZEgLUox68DGsg2Zl/6c66pc92Hu4g8zBZFpzwIpYle zMZ3pbSneuKi1NysSbJV4PEIxReQck9SAv7kunDcX2xAYV66UFFEFq3riKCqrSLiyVMm 0Ocg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756256823; x=1756861623; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PiTlSDbl7ZE2Kdnr9r+qg6Y8XwHKnrFV6OAAtT3qX4s=; b=nVFvlbsJ5DCGtc7ulOxUJ7xO+Hca790rJi3zBApcR9GeTqhjWT2yDV++xyFmrITs6j SRIBrkkOxO71HmGlnPPOwrBMVEk52mJDoiZjmnww1GHCpcXY0p4t/RcsR+V6kSjgb4WK zxsSaNxh31aJ96RMN4Q3ttNgtGeEhUo3W3h+7V3yTI7DBNRDRB2rp7OUVT7DbcRK4t7G vXcFi66oHEnERchNKvz5KY1kOhgYjoz3zvdPxCwIM5PmVs+Q64sLLhsvFgGEqIJ4i8e1 BqgaAbZlDpkk/MbpV14umo1ix6cQ04499TdoKdJ1/B0V4KKrg8eoiSwdT30gLKglRvcd DQVQ== X-Gm-Message-State: AOJu0Yxv8Q2KaMbIn/1FijOJKiv1GyBvUaDH4caMMr4z1F67nKGOgqqO 973E0+rfIY4w2ruaZMx3m/YqM+O/XZV++TDu4mPLjwjzhwcnirfPVqYeu9SSBBAWYUIvO42Qpwd a2XnW9nE= X-Gm-Gg: ASbGncsSpZJ0O81vXSliZ7w4DtPiDhfnc8Cd/jaqADRNfhqFuLzOprfocPEfKSNUUrz cqig5YIxppzyJbdG1DQpJWzeCeLlgE/Bn5DVJFEbpXaSMbn7S1HX4jrC41bYNUqDExp8EtpQAZI QOyKwzwr4MAuY5rzZPfoG5ThV0I+7k07RXqTrI1S0Drxt7ah+Vf/Q9pR6+V87KrT+3FjchJZvc8 zK1cW/L1hne27Igso/kdTOIyj+TaQwF7MHQKWYhJMWR4cw/+j6OrjZwIZfPHzL3mNE+Yd5sXPrl ZOp89PaEbhc+dRixEV/1ldVrDfr5U6Ufrvn5YUP1D3Mu70bEpVN2M/rptVoJPaayrJG3W15fTBD qhmYCA6XCAkRuyRXOwpU+22Zhs57SWsTCVeCOV9wxM9P81ZE= X-Google-Smtp-Source: AGHT+IH0iM1ygKOoU5r2kTMIxyLmtw73+6189p1IT7DGgLcP4y82qXYsjOF7Vl5WtssV+z+GIVmRkA== X-Received: by 2002:a05:6a00:14c7:b0:770:5987:5b3a with SMTP id d2e1a72fcca58-77059879144mr11624726b3a.16.1756256823287; Tue, 26 Aug 2025 18:07:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 22/61] target/arm: Move cp processing to define_one_arm_cp_reg Date: Wed, 27 Aug 2025 11:04:13 +1000 Message-ID: <20250827010453.4059782-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250827010453.4059782-1-richard.henderson@linaro.org> References: <20250827010453.4059782-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756257236154116600 Content-Type: text/plain; charset="utf-8" Processing of cp was split between add_cpreg_to_hashtable and define_one_arm_cp_reg. Unify it all to the top-level function. Signed-off-by: Richard Henderson --- target/arm/helper.c | 53 +++++++++++++++++++-------------------------- 1 file changed, 22 insertions(+), 31 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index da6a8f0a8f..a9d6ed1270 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7269,7 +7269,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, CPState state, CPSecureState secstate, - int crm, int opc1, int opc2, + int cp, int crm, int opc1, int opc2, const char *name) { CPUARMState *env =3D &cpu->env; @@ -7277,28 +7277,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; - int cp =3D r->cp; size_t name_len; bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: - /* We assume it is a cp15 register if the .cp field is left unset.= */ - if (cp =3D=3D 0 && r->state =3D=3D ARM_CP_STATE_BOTH) { - cp =3D 15; - } key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); break; case ARM_CP_STATE_AA64: - /* - * To allow abbreviation of ARMCPRegInfo definitions, we treat - * cp =3D=3D 0 as equivalent to the value for "standard guest-visi= ble - * sysreg". STATE_BOTH definitions are also always "standard sysr= eg" - * in their AArch64 view (the .cp value may be non-zero for the - * benefit of the AArch32 view). - */ - assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); - cp =3D 0; key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); break; default: @@ -7459,7 +7445,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu, const ARMCPRegInfo *r, - int crm, int opc1, int opc2) + int cp, int crm, int opc1, int opc= 2) { /* * Under AArch32 CP registers can be common @@ -7472,16 +7458,16 @@ static void add_cpreg_to_hashtable_aa32(ARMCPU *cpu= , const ARMCPRegInfo *r, switch (r->secure) { case ARM_CP_SECSTATE_S: case ARM_CP_SECSTATE_NS: - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - r->secure, crm, opc1, opc2, r->name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, r->secure, + cp, crm, opc1, opc2, r->name); break; case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - ARM_CP_SECSTATE_S, crm, opc1, opc2, name); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= S, + cp, crm, opc1, opc2, name); g_free(name); - add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, - ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); + add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA32, ARM_CP_SECSTATE_= NS, + cp, crm, opc1, opc2, r->name); break; default: g_assert_not_reached(); @@ -7512,11 +7498,11 @@ static void add_cpreg_to_hashtable_aa64(ARMCPU *cpu= , const ARMCPRegInfo *r, nxs_ri.fgt |=3D R_FGT_NXS_MASK; } add_cpreg_to_hashtable(cpu, &nxs_ri, ARM_CP_STATE_AA64, - ARM_CP_SECSTATE_NS, crm, opc1, opc2, name); + ARM_CP_SECSTATE_NS, 0, crm, opc1, opc2, nam= e); } =20 add_cpreg_to_hashtable(cpu, r, ARM_CP_STATE_AA64, ARM_CP_SECSTATE_NS, - crm, opc1, opc2, r->name); + 0, crm, opc1, opc2, r->name); } =20 void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *r) @@ -7551,6 +7537,7 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRe= gInfo *r) int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + int cp =3D r->cp; =20 /* * AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless. @@ -7573,21 +7560,25 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) */ switch (r->state) { case ARM_CP_STATE_BOTH: - /* 0 has a special meaning, but otherwise the same rules as AA32. = */ - if (r->cp =3D=3D 0) { + /* + * If the cp field is left unset, assume cp15. + * Otherwise apply the same rules as AA32. + */ + if (cp =3D=3D 0) { + cp =3D 15; break; } /* fall through */ case ARM_CP_STATE_AA32: if (arm_feature(&cpu->env, ARM_FEATURE_V8) && !arm_feature(&cpu->env, ARM_FEATURE_M)) { - assert(r->cp >=3D 14 && r->cp <=3D 15); + assert(cp >=3D 14 && cp <=3D 15); } else { - assert(r->cp < 8 || (r->cp >=3D 14 && r->cp <=3D 15)); + assert(cp < 8 || (cp >=3D 14 && cp <=3D 15)); } break; case ARM_CP_STATE_AA64: - assert(r->cp =3D=3D 0); + assert(cp =3D=3D 0); break; default: g_assert_not_reached(); @@ -7657,13 +7648,13 @@ void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCP= RegInfo *r) for (int opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { switch (r->state) { case ARM_CP_STATE_AA32: - add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); break; case ARM_CP_STATE_AA64: add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); break; case ARM_CP_STATE_BOTH: - add_cpreg_to_hashtable_aa32(cpu, r, crm, opc1, opc2); + add_cpreg_to_hashtable_aa32(cpu, r, cp, crm, opc1, opc= 2); add_cpreg_to_hashtable_aa64(cpu, r, crm, opc1, opc2); break; default: --=20 2.43.0