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([144.6.121.55]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7720274534esm1419241b3a.47.2025.08.26.18.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 18:06:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1756256804; x=1756861604; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=xm+DiQK3QPrsWhspwKpORtvyMvoqamrQ0zoWrs8mIIg=; b=UD76AQ8cMaHTg5s1d0d3NXo6BJRRAwlL3TehQuq+fE9+QinvRcjwiJv/g5jtFVDGiO CjzKFw89ZSW9PAE6Yx4cypjX/AxSS4Tl25vUgzoyuSY0lRLMwlws5SHzyd1qSKWsuIUw jr3xijRBUCSk1D8xBHvgbWnpYtTUax0c57Qm0nZmsR8NFjy5rKFZW04bKNNHihsUDE56 DKyVZufDAqh731z74C7Vx0k1KrMBwRJl8oUMPa8UvxUpKjnUg+FgmTnzTk4zIIEHCWTI MGT5RONEQsCOqsuhgwSD10G9rRcBeUydonJ4rba6FAzbLE6+B/LZZ7sdadJMAst8QAMT Z9UA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756256804; x=1756861604; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=xm+DiQK3QPrsWhspwKpORtvyMvoqamrQ0zoWrs8mIIg=; b=Td+lBRr1TSh+efE8o8jGFEFFbXEp6FZnczB0s+E5gNtS8os5PpA9lCXLec1gblLD8a 7p7ksDn0u/26kWnSWyXu4JEOZtiaf2mrGQchM+q4nDsfkYjhb6My55yXZTcdSeyY43zt wbgj1j2RbeIaVQV4V2Z4y0OiqGR3rSXaNCXJgLdE2CIo5d5IgJznSRzeLRsMjEWhHGu/ yFAtj+yKLRv9u2T6sM5JxjDuFP22Obz5/iUY9f2wVtShr7RFTAl0bYj0vP75opjGuZo7 HrX2bbcZlyeZYZjmeysgox2UzcYnQ8xlJrei5QrIx8gdQdrEQrkvfdu2QdhAAdxd4hgl fwKg== X-Gm-Message-State: AOJu0YzYrW26zXPqKO3biT1muK9EsNwPeqB30NlY8qfJRbe4mNBoekEg NOwdfCvvPqoJCJaZmP7S9USWdDexFY01fb0bmu+Mhuphd3//kw1I3MkKMMBSmeXV+wguZWniZ3Y mUYrsCKk= X-Gm-Gg: ASbGnctjb03JJZ3oAvVAsa6WYfsUtbhkzjf+mlVm0lR66q1kCbKFDuTywzz+mtjicJd QPdmioQdj9jrMnNJG3PL0yAfAZLQ7mdPIfDnZOzN8P70PLRaU3nRJcQpWJt7U7vzTawNT5rZsGS 4l8mSVCal8fq4/qfTMMZM4wo9h4OktUrVARi38Mgl5sX4jRPjDOP08eSikkDsYJTrbSihlA7ySM FJsAJ+Dez79zADqHIWiXEJV+nupWUGwCZFfOhY3vWuG2qE4ViyMAtwgpiR/HJnzyjoc22e4cDzz kW7sul2WwwnOI5JEnOb3fRYX2By6w9c+plG3kZYC349/CS9pXoqJS+tz0kJdWcVy9RBo9gmWjfq GmLIfyjDoT193A62N2PZQcbNWvA== X-Google-Smtp-Source: AGHT+IFavYLkjFmtmd47RFYLz95wqtF/AITqoCSmalH++VzPT9h05R1tRUpwCLbHP1Ad/lvtP/Hd+g== X-Received: by 2002:a05:6a00:23d1:b0:771:e1bf:bddc with SMTP id d2e1a72fcca58-771e1bfccbfmr13032300b3a.13.1756256804289; Tue, 26 Aug 2025 18:06:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 19/61] target/arm: Reorder ENCODE_AA64_CP_REG arguments Date: Wed, 27 Aug 2025 11:04:10 +1000 Message-ID: <20250827010453.4059782-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250827010453.4059782-1-richard.henderson@linaro.org> References: <20250827010453.4059782-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1756257282769124100 Content-Type: text/plain; charset="utf-8" The order of the parameters in the Arm ARM is op0, op1, crn, crm, op2 Reorder the arguments of ENCODE_AA64_CP_REG to match. Signed-off-by: Richard Henderson Reviewed-by: Manos Pitsidianakis --- target/arm/cpregs.h | 2 +- target/arm/helper.c | 4 ++-- target/arm/hvf/hvf.c | 6 +++--- target/arm/tcg/translate-a64.c | 4 ++-- 4 files changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 95b0b9c78e..7bdf6cf847 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -187,7 +187,7 @@ enum { ((is64) << CP_REG_AA32_64BIT_SHIFT) | \ ((cp) << 16) | ((crn) << 11) | ((crm) << 7) | ((opc1) << 3) | (opc2)) =20 -#define ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) \ +#define ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) \ (CP_REG_AA64_MASK | CP_REG_ARM64_SYSREG | \ ((op0) << CP_REG_ARM64_SYSREG_OP0_SHIFT) | \ ((op1) << CP_REG_ARM64_SYSREG_OP1_SHIFT) | \ diff --git a/target/arm/helper.c b/target/arm/helper.c index 93cae888e2..b48b669a6a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4527,7 +4527,7 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) }; =20 #define K(op0, op1, crn, crm, op2) \ - ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2) + ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2) =20 static const struct E2HAlias aliases[] =3D { { K(3, 0, 1, 0, 0), K(3, 4, 1, 0, 0), K(3, 5, 1, 0, 0), @@ -7299,7 +7299,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, */ assert(cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH); cp =3D 0; - key =3D ENCODE_AA64_CP_REG(r->crn, crm, r->opc0, opc1, opc2); + key =3D ENCODE_AA64_CP_REG(r->opc0, opc1, r->crn, crm, opc2); break; default: g_assert_not_reached(); diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index af03fc7fc1..bda57614ed 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1124,10 +1124,10 @@ static bool is_id_sysreg(uint32_t reg) =20 static uint32_t hvf_reg2cp_reg(uint32_t reg) { - return ENCODE_AA64_CP_REG((reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, - (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, - (reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, + return ENCODE_AA64_CP_REG((reg >> SYSREG_OP0_SHIFT) & SYSREG_OP0_MASK, (reg >> SYSREG_OP1_SHIFT) & SYSREG_OP1_MASK, + (reg >> SYSREG_CRN_SHIFT) & SYSREG_CRN_MASK, + (reg >> SYSREG_CRM_SHIFT) & SYSREG_CRM_MASK, (reg >> SYSREG_OP2_SHIFT) & SYSREG_OP2_MASK); } =20 diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index 743c5a10e1..58303c224f 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -2466,7 +2466,7 @@ static void handle_sys(DisasContext *s, bool isread, unsigned int op0, unsigned int op1, unsigned int op= 2, unsigned int crn, unsigned int crm, unsigned int rt) { - uint32_t key =3D ENCODE_AA64_CP_REG(crn, crm, op0, op1, op2); + uint32_t key =3D ENCODE_AA64_CP_REG(op0, op1, crn, crm, op2); const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(s->cp_regs, key); bool need_exit_tb =3D false; bool nv_trap_to_el2 =3D false; @@ -2602,7 +2602,7 @@ static void handle_sys(DisasContext *s, bool isread, * We don't use the EL1 register's access function, and * fine-grained-traps on EL1 also do not apply here. */ - key =3D ENCODE_AA64_CP_REG(crn, crm, op0, 0, op2); + key =3D ENCODE_AA64_CP_REG(op0, 0, crn, crm, op2); ri =3D get_arm_cp_reginfo(s->cp_regs, key); assert(ri); assert(cp_access_ok(s->current_el, ri, isread)); --=20 2.43.0