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(unknown [9.10.239.198]) by smtpav03.wdc07v.mail.ibm.com (Postfix) with ESMTP; Tue, 26 Aug 2025 20:21:26 +0000 (GMT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ibm.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pp1; bh=gH0Mrx gmDF8cGzIffDLABoM1qs9HAAUWVUyd4RuutL0=; b=EbBzznj+zo8TqOeWNOKmXs Y+LeGtqcbO76H+6Xvscm4VAgLiRFDZKdo9APshPqpV56miqFUvnwZ0+LBIlj3U6u Wl9vZP+Zc7qmkLZ+/Rva+1jTMM289EoSEscK4U85d24252UOtageIv1FHGli1iwM SSHWIaipsMyfqUdvkX0epWodR9uH8rNrotDJtOgOBYPDFmeHpUPMbXT0yOKTQ66z MS2kNUlIG5AdKIuLGkl9kCB5ALALGAbGi3MqZqmIe+lDtfh1OmAz96kwN+4yjcdf sARmwPo8/m01xoiNS8VVWbfyt6PST2MU3IJ+c2EkPh5p4UXmUWbzK0T11NVn2bUQ == From: Glenn Miles To: qemu-devel@nongnu.org Cc: Glenn Miles , qemu-ppc@nongnu.org, clg@redhat.com, npiggin@gmail.com, harshpb@linux.ibm.com, thuth@redhat.com, rathc@linux.ibm.com, richard.henderson@linaro.org Subject: [PATCH v2 3/4] hw/ppc: Add a test machine for the IBM PPE42 CPU Date: Tue, 26 Aug 2025 15:17:50 -0500 Message-ID: <20250826201920.335308-4-milesg@linux.ibm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250826201920.335308-1-milesg@linux.ibm.com> References: <20250826201920.335308-1-milesg@linux.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-GUID: K7whvDs0Ce6XP9L_LEByeSDfd2RNlKxY X-Proofpoint-ORIG-GUID: v1hBtrWuZhoIyP_dKNXnY678C42MZQ06 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDA3MSBTYWx0ZWRfX/0PlbXEmZ+pV w0JOILK1E5XPvutYNKY75r+j4Z6CQd2b3NwEJ0DE4vzQwIrpUcrq3wK/jk/qqKErLUWITxgoHbW XehRCLvzTNHJgSevIMS7UGTF2yjC8lSZ3S/WdOU2NpyV8BBCbL9oesNzlF3+KaBDmjQU/Sr94bD 2gBKw4iN390cTL959nN+u1ziwCxcxlovB2fSeO3+bf7jB9yZHs8f4Ao9dhoTsRbam/FsJQltm1M qsfBb3nkER/fFBNpaVIMfVYnYOydA1LYMK8fcCbFLuSSWY2smtBm5kZW2v2vM7y8p565+pLXxi2 FlQ0PwgKls9R9hpE8IHQig/nZNUAEWsdMti2pA0BKtUW61wwnRtqcbGCnHcLSPz2BHR7MFL9QnM uJKGWwPw X-Authority-Analysis: v=2.4 cv=RtDFLDmK c=1 sm=1 tr=0 ts=68ae174a cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=IkcTkHD0fZMA:10 a=2OwXVqhp2XgA:10 a=VnNF1IyMAAAA:8 a=69wJf7TsAAAA:8 a=up-X0YpDAAAA:8 a=cbWz_aXUB6W1s0bw1rsA:9 a=3ZKOabzyN94A:10 a=QEXdDO2ut3YA:10 a=Fg1AiH1G6rFz08G2ETeA:22 a=86FmjZgct7XXK6GGpxvI:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 suspectscore=0 malwarescore=0 spamscore=0 priorityscore=1501 bulkscore=0 clxscore=1015 phishscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230071 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=milesg@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1756239785960124100 Adds a test machine for the IBM PPE42 processor, including a DEC, FIT, WDT and 1MB of ram. The purpose of this machine is only to provide a generic platform for testing instructions of the recently added PPE42 processor model which is used extensively in the IBM Power9, Power10 and future Power server processors. Signed-off-by: Glenn Miles --- Changes from previous version - Added ppe42_machine.c to MAINTAINERS file with self as maintainer MAINTAINERS | 6 ++++ hw/ppc/Kconfig | 9 ++++++ hw/ppc/meson.build | 2 ++ hw/ppc/ppc_booke.c | 7 ++++- hw/ppc/ppe42_machine.c | 69 ++++++++++++++++++++++++++++++++++++++++++ include/hw/ppc/ppc.h | 1 + 6 files changed, 93 insertions(+), 1 deletion(-) create mode 100644 hw/ppc/ppe42_machine.c diff --git a/MAINTAINERS b/MAINTAINERS index a07086ed76..52fa303e0a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1531,6 +1531,12 @@ F: include/hw/pci-host/grackle.h F: pc-bios/qemu_vga.ndrv F: tests/functional/test_ppc_mac.py =20 +PPE42 +M: Glenn Miles +L: qemu-ppc@nongnu.org +S: Odd Fixes +F: hw/ppc/ppe42_machine.c + PReP M: Herv=C3=A9 Poussineau L: qemu-ppc@nongnu.org diff --git a/hw/ppc/Kconfig b/hw/ppc/Kconfig index ced6bbc740..3fdea5919c 100644 --- a/hw/ppc/Kconfig +++ b/hw/ppc/Kconfig @@ -44,6 +44,15 @@ config POWERNV select SSI_M25P80 select PNV_SPI =20 +config PPC405 + bool + default y + depends on PPC + select M48T59 + select PFLASH_CFI02 + select PPC4XX + select SERIAL + config PPC440 bool default y diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build index 9893f8adeb..170b90ae7d 100644 --- a/hw/ppc/meson.build +++ b/hw/ppc/meson.build @@ -57,6 +57,8 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files( 'pnv_n1_chiplet.c', )) # PowerPC 4xx boards +ppc_ss.add(when: 'CONFIG_PPC405', if_true: files( + 'ppe42_machine.c')) ppc_ss.add(when: 'CONFIG_PPC440', if_true: files( 'ppc440_bamboo.c', 'ppc440_uc.c')) diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 3872ae2822..13403a56b1 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -352,7 +352,12 @@ void ppc_booke_timers_init(PowerPCCPU *cpu, uint32_t f= req, uint32_t flags) booke_timer =3D g_new0(booke_timer_t, 1); =20 cpu->env.tb_env =3D tb_env; - tb_env->flags =3D flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERED; + if (flags & PPC_TIMER_PPE) { + /* PPE's use a modified version of the booke behavior */ + tb_env->flags =3D flags | PPC_DECR_UNDERFLOW_TRIGGERED; + } else { + tb_env->flags =3D flags | PPC_TIMER_BOOKE | PPC_DECR_ZERO_TRIGGERE= D; + } =20 tb_env->tb_freq =3D freq; tb_env->decr_freq =3D freq; diff --git a/hw/ppc/ppe42_machine.c b/hw/ppc/ppe42_machine.c new file mode 100644 index 0000000000..0bc295da28 --- /dev/null +++ b/hw/ppc/ppe42_machine.c @@ -0,0 +1,69 @@ + +/* + * Test Machine for the IBM PPE42 processor + * + * Copyright (c) 2025, IBM Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qemu/error-report.h" +#include "system/address-spaces.h" +#include "hw/boards.h" +#include "hw/ppc/ppc.h" +#include "system/system.h" +#include "system/reset.h" +#include "system/kvm.h" + +static void main_cpu_reset(void *opaque) +{ + PowerPCCPU *cpu =3D opaque; + + cpu_reset(CPU(cpu)); +} + +static void ppe42_machine_init(MachineState *machine) +{ + PowerPCCPU *cpu; + CPUPPCState *env; + + if (kvm_enabled()) { + error_report("machine %s does not support the KVM accelerator", + MACHINE_GET_CLASS(machine)->name); + exit(EXIT_FAILURE); + } + + /* init CPU */ + cpu =3D POWERPC_CPU(cpu_create(machine->cpu_type)); + env =3D &cpu->env; + if (PPC_INPUT(env) !=3D PPC_FLAGS_INPUT_PPE42) { + error_report("Incompatible CPU, only PPE42 bus supported"); + exit(1); + } + + qemu_register_reset(main_cpu_reset, cpu); + + /* This sets the decrementer timebase */ + ppc_booke_timers_init(cpu, 37500000, PPC_TIMER_PPE); + + /* RAM */ + if (machine->ram_size > 2 * GiB) { + error_report("RAM size more than 2 GiB is not supported"); + exit(1); + } + memory_region_add_subregion(get_system_memory(), 0xfff80000, machine->= ram); +} + + +static void ppe42_machine_class_init(MachineClass *mc) +{ + mc->desc =3D "PPE42 Test Machine"; + mc->init =3D ppe42_machine_init; + mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("PPE42XM"); + mc->default_ram_id =3D "ram"; + mc->default_ram_size =3D 1 * MiB; +} + +DEFINE_MACHINE("ppe42_machine", ppe42_machine_class_init) diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index 8a14d623f8..cb51d704c6 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -52,6 +52,7 @@ struct ppc_tb_t { #define PPC_DECR_UNDERFLOW_LEVEL (1 << 4) /* Decr interrupt active when * the most significant bit = is 1. */ +#define PPC_TIMER_PPE (1 << 5) /* Enable PPE support */ =20 uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offse= t); void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq); --=20 2.43.0