From nobody Wed Dec 17 18:05:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=reject dis=none) header.from=oss.qualcomm.com ARC-Seal: i=1; a=rsa-sha256; t=1756234017; cv=none; d=zohomail.com; s=zohoarc; b=AlhHgrtGgypmSDQg/18xdt6myxJ22qv3skvmT2ooDbDbYaDj8oQGoe9mD88H/rCqnc55Xk7UWIaiw8Yswjjke/QHU7QcMtiayd6RRbxiL0DnLUlcoOQtRUqPTE8WHpIW0pmVMQgYR5u4Wzbr6aos2eKJ9mMIMFsN5Y4dsfIOXis= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1756234017; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=N/cJ1VigX5TamwRxQg27K5ECt0YK3rjIAflQIFqgDpE=; b=EcZ/e8y/olcn29b1vaWK04Mj1XSwB9pWhHns6Lw2pxgjZg+IlBe0bxdYfgWHu/GN1ONqD7EQF0xq0aca3lal0WuQYjYTEpM7GlmAzBS34G5X3wR+K+zJacKe+cFtTkBRDTFEQCJSfMzqrLUCk3gmo9PNU48E57wQkvWRRsHN1QA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=reject dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1756234017390402.59758225874157; Tue, 26 Aug 2025 11:46:57 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uqyfe-0004vX-9I; Tue, 26 Aug 2025 14:45:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uqyfb-0004un-Fa for qemu-devel@nongnu.org; Tue, 26 Aug 2025 14:45:23 -0400 Received: from mx0a-0031df01.pphosted.com ([205.220.168.131]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uqyfU-0008Sv-0b for qemu-devel@nongnu.org; Tue, 26 Aug 2025 14:45:23 -0400 Received: from pps.filterd (m0279863.ppops.net [127.0.0.1]) by mx0a-0031df01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 57QCRS1q004082 for ; Tue, 26 Aug 2025 18:45:12 GMT Received: from mail-pl1-f197.google.com (mail-pl1-f197.google.com [209.85.214.197]) by mx0a-0031df01.pphosted.com (PPS) with ESMTPS id 48q5xpt6qq-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT) for ; Tue, 26 Aug 2025 18:45:12 +0000 (GMT) Received: by mail-pl1-f197.google.com with SMTP id d9443c01a7336-246f49067bdso23372545ad.0 for ; Tue, 26 Aug 2025 11:45:12 -0700 (PDT) Received: from admin15.qualcomm.com (i-global254.qualcomm.com. [199.106.103.254]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3276aeef8b8sm220661a91.21.2025.08.26.11.45.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 26 Aug 2025 11:45:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=qualcomm.com; h= cc:content-transfer-encoding:date:from:in-reply-to:message-id :mime-version:references:subject:to; s=qcppdkim1; bh=N/cJ1VigX5T amwRxQg27K5ECt0YK3rjIAflQIFqgDpE=; b=ga0rQ9zhXMkM6gR5QZZ7qtIGbJF 4oKO+nFIJtmYSSni+7GoGxxvR4ygnWhZFpdMaHmaR2XcSEqEEuMgFdydq0bDbNEH 6DHNOAh0xfuW7Jsu0WsIMxuq3c79keqyNdzHJB6T0KjNRG9JsjziaW4/TuLQB7yB ke2lLEMlX9G0IvyOdI4hrq7zGT3vqfjJJgg5bdJnYRQ+raLKDHG45rrAe3bZWHTh nb/UAmjxrfC2s98hv9JpIJs0rLMwFOc0OyRpnP7jgsWt8Sf+guj1NjrODwxoQidR sJSXizqGvQVNf8o0JiQ8XgbLF6eqYTj5uV+hBtNSbr3IS2/R+E/gpuDh7LA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1756233911; x=1756838711; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=N/cJ1VigX5TamwRxQg27K5ECt0YK3rjIAflQIFqgDpE=; b=c/JtWCE6b9by7XMopE6SpDxHZpkanlt4MpGxYJTt4296h6O7aHmNJ2vvk4i4lJx1SM JUWF1k/945C0F5Gqzsj/47CVgvsmgjfuCSMuPNg1eqAqRS4gS92sbg+lve0JGl4K2xfx dTFtNmqyPuydXD+ieEL9TAkfqa76Hp1F3jaFtLvuZfH60pbxKk79x5Hc0TBFEN2RBVq/ bm3TjOGavrnUMIEsQTxh6rF7ObzGkmS0CqQUHnmwSGNHiTxuysl1W19+vC4GLiRmObzC ClcXTJWGk51hZoCUjoxg/EF4/AHSehvMHcs3KtIPzC17nx4DP8atANo0v0PYdQoAw+Oi DEYg== X-Gm-Message-State: AOJu0YzivwWzWZLEqOKYCyupunaDfKSaWOzxQSVF9FA2Jtv1HVos8Y6x qJSpjAzvUINAa4N6cm2rw7Dx9wohMjGNkJe8uRLtkVovfPscP7nzib0DNJ7AWzDiTg2QfJf2C4w J3efPoZjt9sv29zs2RTCKieYuhfpTCjirw/PefXNeQXv7x3fsSuu5RlRKCGpVgxTAbFV9 X-Gm-Gg: ASbGncuy7PZcrMyOZV7EMtZPgsaMGN9s/Fcl/LAgcbH64BO/DHDnKcZzaNIVKTsDIcc frSY3RRlYD0FwRmvGuYx9O4gqw39VI9eASlBMjqGqg7ldizrNPLl9gF3TmA9bKXol5xXdbP56n0 zgi2FUdppFHlkGqsz18JjvrHYzzYxE1CGPLmgxvixmuWi5fSFiMAZvqRg/kL9LUnNhbZKjGmKhD uwG5ysm4AFbzPJJ3Lhefj47j7UjgXoY7mXS0U+ppcijtp97TJ8amQsmxhnArRenmXQXZ0jkwoJ1 YMOY1CWKQjSoFgs1QmKGiAqudVjP40aGhh/YDAFlxWQhNb1YXOfLReLmFePblkMNsw8fdfcLSMx PdDorjG//Q/Joysc= X-Received: by 2002:a17:902:e786:b0:246:80b1:8c87 with SMTP id d9443c01a7336-24680b190famr149128375ad.43.1756233911044; Tue, 26 Aug 2025 11:45:11 -0700 (PDT) X-Google-Smtp-Source: AGHT+IH9HnvJ9dEZOIKH20ityDwao35hmppm9k0kcAS/YV/wZgjhfUi73rgdrU6+DJL1x89N1dULnA== X-Received: by 2002:a17:902:e786:b0:246:80b1:8c87 with SMTP id d9443c01a7336-24680b190famr149127965ad.43.1756233910507; Tue, 26 Aug 2025 11:45:10 -0700 (PDT) From: Vacha Bhavsar To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Paolo Bonzini , Peter Maydell , Thomas Huth , Vacha Bhavsar Subject: [PATCH v6 2/3] target/arm: Added support for SME register exposure to GDB Date: Tue, 26 Aug 2025 18:45:03 +0000 Message-Id: <20250826184504.510279-3-vacha.bhavsar@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250826184504.510279-1-vacha.bhavsar@oss.qualcomm.com> References: <20250826184504.510279-1-vacha.bhavsar@oss.qualcomm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=KOlaDEFo c=1 sm=1 tr=0 ts=68ae00b8 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=JYp8KDb2vCoCEuGobkYCKw==:17 a=2OwXVqhp2XgA:10 a=EUspDBNiAAAA:8 a=JRRW1ReKSft4RaJC_60A:9 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: T_HCbiUH8wKIjC16wDFY0z24qc_V_ri2 X-Proofpoint-ORIG-GUID: T_HCbiUH8wKIjC16wDFY0z24qc_V_ri2 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwODIzMDAzMyBTYWx0ZWRfXz54XwALcxT4h Iz4WzepBYkMXaWoyWBTVUzJR6U+Mpb6dUJIkbK813r5hQgSqfeFKNTIq/jaeFPWNzYU7mWqBIYG /HKMvgatKjDwuOIPAeoUB5FAq483osAWwSQIQmuqOxTuB8APDBvmvBC/yCH52fpRomf5BUZzsTv DIIsA0dE/bjixnREMO1l5bYw+Sf01SweFc/eDE5s/3Zzh00+h638NOGsJ0RA8EoJW+FYTy2G/5I gzj3KfQFCYQqSFR6dg0Qlaqz7RZ7/LxICslFqqsYVO3gzSTJS2fQLQaLyVbxBDXS+YF/uJrpthy e9DiYVCyNiPFumif1z3NwixsQ5ZZU6/codCJ+KkfBZxdGUWHq7jgtCFj12Ctmx0klZlpAhnKlX2 E+Z3FnpQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.1.9,FMLib:17.12.80.40 definitions=2025-08-26_02,2025-08-26_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 clxscore=1015 bulkscore=0 adultscore=0 phishscore=0 impostorscore=0 spamscore=0 suspectscore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2507300000 definitions=main-2508230033 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.220.168.131; envelope-from=vacha.bhavsar@oss.qualcomm.com; helo=mx0a-0031df01.pphosted.com X-Spam_score_int: -26 X-Spam_score: -2.7 X-Spam_bar: -- X-Spam_report: (-2.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @qualcomm.com) X-ZM-MESSAGEID: 1756234020208124100 Content-Type: text/plain; charset="utf-8" The QEMU GDB stub does not expose the ZA storage SME register to GDB via the remote serial protocol, which can be a useful functionality to debug SME code. To provide this functionality in Aarch64 target, this patch registers= the SME register set with the GDB stub. To do so, this patch implements the aarch64_gdb_get_sme_reg() and aarch64_gdb_set_sme_reg() functions to specify how to get and set the SME registers, and the arm_gen_dynamic_smereg_feature() function to generate the target description in XML format to indicate the target architecture supports SME. Finally, this patch includes a dyn_smereg_feature structure to hold this GDB XML description of the SME registers for each CPU. Signed-off-by: Vacha Bhavsar --- Changes since v5: - added code to handle the case when we have SME without SVE - added comments to indicate th cases in aarch64_gdb_get/set_sme_reg - added/removed braces where necessary - corrected capitalization in comments --- target/arm/cpu.h | 1 + target/arm/gdbstub.c | 9 ++- target/arm/gdbstub64.c | 121 +++++++++++++++++++++++++++++++++++++++++ target/arm/internals.h | 3 + 4 files changed, 133 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index dc9b6dce4c..8bd66d7049 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -933,6 +933,7 @@ struct ArchCPU { =20 DynamicGDBFeatureInfo dyn_sysreg_feature; DynamicGDBFeatureInfo dyn_svereg_feature; + DynamicGDBFeatureInfo dyn_smereg_feature; DynamicGDBFeatureInfo dyn_m_systemreg_feature; DynamicGDBFeatureInfo dyn_m_secextreg_feature; =20 diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ce4497ad7c..110258ec18 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -527,7 +527,7 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu) * registers so we don't need to include both. */ #ifdef TARGET_AARCH64 - if (isar_feature_aa64_sve(&cpu->isar)) { + if (isar_feature_aa64_sve(&cpu->isar) || isar_feature_aa64_sme(&cp= u->isar)) { GDBFeature *feature =3D arm_gen_dynamic_svereg_feature(cs, cs-= >gdb_num_regs); gdb_register_coprocessor(cs, aarch64_gdb_get_sve_reg, aarch64_gdb_set_sve_reg, feature, 0); @@ -537,6 +537,13 @@ void arm_cpu_register_gdb_regs_for_features(ARMCPU *cp= u) gdb_find_static_feature("aarch64-fpu.= xml"), 0); } + + if (isar_feature_aa64_sme(&cpu->isar)) { + GDBFeature *sme_feature =3D arm_gen_dynamic_smereg_feature(cs, + cs->gdb_num_regs); + gdb_register_coprocessor(cs, aarch64_gdb_get_sme_reg, + aarch64_gdb_set_sme_reg, sme_feature, 0); + } /* * Note that we report pauth information via the feature name * org.gnu.gdb.aarch64.pauth_v2, not org.gnu.gdb.aarch64.pauth. diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index 08e2858539..d3fd94b93d 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -249,6 +249,90 @@ int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf= , int reg) return 0; } =20 +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + { + int vq =3D 0; + if (FIELD_EX64(env->svcr, SVCR, SM)) { + vq =3D sve_vqm1_for_el_sm(env, arm_current_el(env), + FIELD_EX64(env->svcr, SVCR, SM)) + 1; + } + /* svg =3D vector granules (2 * vector quardwords) in streaming mo= de */ + return gdb_get_reg64(buf, vq * 2); + } + case 1: /* svcr register */ + return gdb_get_reg64(buf, env->svcr); + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + len +=3D gdb_get_reg128(buf, + env->za_state.za[i].d[q * 2 + 1], + env->za_state.za[i].d[q * 2]); + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + qemu_log_mask(LOG_UNIMP, "%s: out of range register %d", __func__,= reg); + break; + } + + return 0; +} + +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + + switch (reg) { + case 0: /* svg register */ + /* cannot set svg via gdbstub */ + return 8; + case 1: /* svcr register */ + aarch64_set_svcr(env, ldq_le_p(buf), + R_SVCR_SM_MASK | R_SVCR_ZA_MASK); + return 8; + case 2: /* za register */ + { + int len =3D 0; + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + for (int i =3D 0; i < svl; i++) { + for (int q =3D 0; q < vq; q++) { + if (target_big_endian()) { + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + } else{ + env->za_state.za[i].d[q * 2] =3D ldq_p(buf); + buf +=3D 8; + env->za_state.za[i].d[q * 2 + 1] =3D ldq_p(buf); + } + buf +=3D 8; + len +=3D 16; + } + } + return len; + } + default: + /* gdbstub asked for something out of range */ + break; + } + + return 0; +} + int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg) { ARMCPU *cpu =3D ARM_CPU(cs); @@ -413,6 +497,43 @@ GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *c= s, int base_reg) return &cpu->dyn_svereg_feature.desc; } =20 +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cs, int base_reg) +{ + ARMCPU *cpu =3D ARM_CPU(cs); + int vq =3D cpu->sme_max_vq; + int svl =3D vq * 16; + GDBFeatureBuilder builder; + int reg =3D 0; + + gdb_feature_builder_init(&builder, &cpu->dyn_smereg_feature.desc, + "org.gnu.gdb.aarch64.sme", "sme-registers.xml", base_reg); + + + /* Create the sme_bv vector type. */ + gdb_feature_builder_append_tag(&builder, + "", + svl); + + /* Create the sme_bvv vector type. */ + gdb_feature_builder_append_tag( + &builder, "", + svl); + + /* Define the svg, svcr, and za registers. */ + + /* fpscr & status registers */ + gdb_feature_builder_append_reg(&builder, "svg", 64, reg++, + "int", NULL); + gdb_feature_builder_append_reg(&builder, "svcr", 64, reg++, + "int", NULL); + gdb_feature_builder_append_reg(&builder, "za", svl * svl * 8, reg++, + "sme_bvv", NULL); + + gdb_feature_builder_end(&builder); + + return &cpu->dyn_smereg_feature.desc; +} + #ifdef CONFIG_USER_ONLY int aarch64_gdb_get_tag_ctl_reg(CPUState *cs, GByteArray *buf, int reg) { diff --git a/target/arm/internals.h b/target/arm/internals.h index 1b3d0244fd..41e05066b9 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1802,8 +1802,11 @@ static inline uint64_t pmu_counter_mask(CPUARMState = *env) } =20 GDBFeature *arm_gen_dynamic_svereg_feature(CPUState *cpu, int base_reg); +GDBFeature *arm_gen_dynamic_smereg_feature(CPUState *cpu, int base_reg); int aarch64_gdb_get_sve_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_sve_reg(CPUState *cs, uint8_t *buf, int reg); +int aarch64_gdb_get_sme_reg(CPUState *cs, GByteArray *buf, int reg); +int aarch64_gdb_set_sme_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_fpu_reg(CPUState *cs, GByteArray *buf, int reg); int aarch64_gdb_set_fpu_reg(CPUState *cs, uint8_t *buf, int reg); int aarch64_gdb_get_pauth_reg(CPUState *cs, GByteArray *buf, int reg); --=20 2.34.1