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Iglesias" To: qemu-devel@nongnu.org, "Edgar E. Iglesias" Cc: richard.henderson@linaro.org, philmd@linaro.org, edgar.iglesias@amd.com Subject: [PATCH v2 3/3] target/microblaze: Handle signed division overflows Date: Mon, 25 Aug 2025 13:20:51 +0200 Message-ID: <20250825112051.4155931-4-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250825112051.4155931-1-edgar.iglesias@gmail.com> References: <20250825112051.4155931-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::12c; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x12c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1756120908191116600 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Handle signed division overflows as specified in UG984: https://docs.amd.com/r/en-US/ug984-vivado-microblaze-ref/idiv Signed-off-by: Edgar E. Iglesias Reviewed-by: Richard Henderson --- target/microblaze/cpu.h | 1 + target/microblaze/op_helper.c | 15 +++++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 3ce28b302f..c9bf9361db 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -87,6 +87,7 @@ typedef struct CPUArchState CPUMBState; #define ESR_ESS_FSL_OFFSET 5 =20 #define ESR_ESS_MASK (0x7f << 5) +#define ESR_ESS_DEC_OF (1 << 11) /* DEC: 0=3DDBZ, 1=3DOF */ =20 #define ESR_EC_FSL 0 #define ESR_EC_UNALIGNED_DATA 1 diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index fbc9c8ca4f..c704233c8c 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -89,6 +89,21 @@ uint32_t helper_divs(CPUMBState *env, uint32_t ra, uint3= 2_t rb) raise_divzero(env, ESR_EC_DIVZERO, GETPC()); return 0; } + + /* + * Check for division overflows. + * + * Spec: https://docs.amd.com/r/en-US/ug984-vivado-microblaze-ref/idiv + * UG984, Chapter 5 MicroBlaze Instruction Set Architecture, idiv. + * + * If the U bit is clear, the value of rA is -1, and the value of rB is + * -2147483648 (divide overflow), the DZO bit in MSR will be set and + * the value in rD will be -2147483648, unless an exception is generat= ed. + */ + if ((int32_t)ra =3D=3D -1 && (int32_t)rb =3D=3D INT32_MIN) { + raise_divzero(env, ESR_EC_DIVZERO | ESR_ESS_DEC_OF, GETPC()); + return INT32_MIN; + } return (int32_t)rb / (int32_t)ra; } =20 --=20 2.43.0