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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v4 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Date: Fri, 22 Aug 2025 17:16:04 +0200 Message-ID: <20250822151614.187856-40-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250822151614.187856-1-luc.michel@amd.com> References: <20250822151614.187856-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: None (SATLEXMB05.amd.com: luc.michel@amd.com does not designate permitted sender hosts) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ1PEPF0000231D:EE_|LV8PR12MB9155:EE_ X-MS-Office365-Filtering-Correlation-Id: 433564f7-418d-4e5b-745a-08dde18f0ba4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|82310400026|36860700013|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DjOt4fhh+dhuW8WhQefT/7Fy1S8Ac+DfPk/8pYuA3gjNNAPyjPK+qujgrZ4a?= =?us-ascii?Q?AFPZLHuQSFz/mMRfGBZu4UZj+NhghAUvP5x2S5iD/jFSdVBSGsEVkExk/2VC?= =?us-ascii?Q?wewPFkxHHq95Y2RVPzBGKv0/utBccUPkQsOi/6p7XfGbmNIdxRBwXxfn43We?= =?us-ascii?Q?z7dQCMUSjLdxnEdIXryKyYnzwx+7KnbkvxYRjhWDG0kkOYjcbYNFkNWgxxnx?= =?us-ascii?Q?+2lE/a8a2aBxgaNlUCtKw3Fc4hmrY1+nN/k81sZdxyREEwLqK4kHqNras2wc?= =?us-ascii?Q?69+P6h5cK0XDf9bpXfVKTWpgbV1y/uZq778jwgs8J0go/2W0f3vT3FJCwuYy?= =?us-ascii?Q?e1JXw/c4LJSzTh0W+EOQfd0aUJ6mBpPyws7PH19no+G/+YZT3fNG7VGgyjux?= =?us-ascii?Q?BsE0RXbBaa6Apagqu2tuGoG1Eq0Cq1OZiLzVOq36+Fh50+vuK8epYkJfzjin?= =?us-ascii?Q?w41wnZkxhrJOXiRCGeEO+McXDu6BDWix4MXnq9mqm5US4c2qmPgfkiY3xDeL?= =?us-ascii?Q?5tWs5Wl/PQ3Ao7WImNsJv1JNQ9sZ59NnqsQc/PmFs0OJXBb1VGLs4t3WdwTo?= =?us-ascii?Q?rdJeOcTjshAC/CVZPsiT2dUjzXZSrqAP/TEFWLXGDkY4fJfoKMRyjpV9jPhn?= =?us-ascii?Q?PBIkwljV8DxdkGGZTwYeJFMT0UsW8KBxJe7wRpJ38Mvgnwdv/klPUSRebA2F?= =?us-ascii?Q?UVmyjPcKFQEOxyXQodGOxnnoycmx7X0rkg5NT3LjtqwOobmPRl3dRRhOR5XW?= =?us-ascii?Q?h7n+4MrmG+fdFeM7tFKj+G9iUBMeP0uEeqO+IEpj8CLD256Vcz5/FCIUN+S3?= =?us-ascii?Q?WB3/w6mk3xsSmmlj81EZZ7TkIXj8LSLoQDtq26JkN2Zzw3o7XN5Eqtr1zV0M?= =?us-ascii?Q?mHF3sp1rAAK4PZzCrdLAN7xIWUtN9QmJbwkRGLk4pFpCXGo+iaOQ3Fy4RyXy?= =?us-ascii?Q?4s5wAJ6alU3d81tmPrwhDwWKvXfkpz+a8txwTo2llaMgjIp9KS4NSnOc/e/o?= =?us-ascii?Q?boQ0crJUJlpAZvsAop1stwU0MsN/gnkGclCrULRRp3BCFx6K6AFC+6VFgUD5?= =?us-ascii?Q?nKxmPV2MTRT2W9LGBlGS6LTSBwFSxa6QcdksxBLrplmwFMWubECfeHO7XNzP?= =?us-ascii?Q?I4OS3bN6/HDeP67ANBsSGSYSPTtX0qwMUSOXAeSXWfJiyy/6uPgu6PXGkm5m?= =?us-ascii?Q?TPFoEalIkfGyVGElPHm+NXSCBXsxyM7YRuF/rsKVqXPcK/utNBK5QDswO/o/?= =?us-ascii?Q?eZoiRKc/gAsG8Wn/kUKu4ZLxy5U7PYvTLgkvmEZzlBy5WA7SofRmIMfD2lzW?= =?us-ascii?Q?kiJP/g96mfLaigw/99YHxLRCqvLqv5XfaKds8hqLLyxahHON+m0nL4CBsBaY?= =?us-ascii?Q?2NphplE2SvE4aKWAzvGS3Xypo4lM3A/q/XNUZexUueVOSmPpy6vH6xE1+Mmj?= =?us-ascii?Q?hUUo1WDP+giDDWq/hgmnXRAZAz8spnAZaFqIJmr35u5m7tEksUjbVGCnj0p8?= =?us-ascii?Q?sXQKL8a5G2y1r2ydQoNDjytX9vhimJjL01kp?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(82310400026)(36860700013)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2025 15:17:44.7016 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 433564f7-418d-4e5b-745a-08dde18f0ba4 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF0000231D.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9155 Received-SPF: permerror client-ip=2a01:111:f403:2414::604; envelope-from=Luc.Michel@amd.com; helo=NAM11-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755876045656116600 Content-Type: text/plain; charset="utf-8" Add support for the ARM Cortex-A78AE CPU. Signed-off-by: Luc Michel --- target/arm/tcg/cpu64.c | 79 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 35cddbafa4c..b56677c1a5d 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -404,10 +404,84 @@ static void aarch64_a76_initfn(Object *obj) =20 /* From D5.1 AArch64 PMU register summary */ cpu->isar.reset_pmcr_el0 =3D 0x410b3000; } =20 +static void aarch64_a78ae_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + + cpu->dtb_compatible =3D "arm,cortex-a78ae"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + SET_IDREG(isar, CLIDR, 0x82000023); + cpu->ctr =3D 0x9444c004; + cpu->dcz_blocksize =3D 4; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); + SET_IDREG(isar, ID_AA64ISAR0, 0x0010100010211120ull); + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000001200031ull); + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000100001011ull); + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); + SET_IDREG(isar, ID_AFR0, 0x00000000); + SET_IDREG(isar, ID_DFR0, 0x04010088); + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); + cpu->midr =3D 0x410fd421; /* r0p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + /* 512KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB,= 7); + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x41223000; +} + static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; =20 @@ -1313,10 +1387,15 @@ void aarch64_max_tcg_initfn(Object *obj) static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, + /* + * The Cortex-A78AE differs slightly from the plain Cortex-A78. We don= 't + * currently model the latter. + */ + { .name =3D "cortex-a78ae", .initfn =3D aarch64_a78ae_initfn }, { .name =3D "cortex-a710", .initfn =3D aarch64_a710_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, --=20 2.50.1