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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v4 31/47] hw/misc/xlnx-versal-crl: split into base/concrete classes Date: Fri, 22 Aug 2025 17:15:56 +0200 Message-ID: <20250822151614.187856-32-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250822151614.187856-1-luc.michel@amd.com> References: <20250822151614.187856-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS2PEPF0000343D:EE_|PH7PR12MB7306:EE_ X-MS-Office365-Filtering-Correlation-Id: 07e30710-56aa-4416-e27b-08dde18f0141 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?Ave+hagd7CmbncxumSjV6wzT1wbE3tGXDp0IAyzTXgh3YrG3BXn1keJ6b7JK?= =?us-ascii?Q?pIHs2luQmTmqQKrca/cXKrUxeyyW+LoEzWqATePBFVfWNG06OhGZ/r1VPmSH?= =?us-ascii?Q?0YrKvd5GdUCVbK+y7O3fp4JCWQtIJ7OrMvHnd9ni8kVkGRS5LNrsL0InduDB?= =?us-ascii?Q?mZle0E+tEyvC/rXaQF5Uwffjr8y94YdrK34L9beDqTMcG1YsodXT/SUSPHXe?= =?us-ascii?Q?1NLxpxVesNa25ipZAjPCIKd73fHawfmVEJteKUf08UAW1lQsCzCI37uk1dbl?= =?us-ascii?Q?CT0EnivPECDBqorG3PNtr5EzXSD++XOqji78l32KdlAxO4DbczxOLKoEr+Nu?= =?us-ascii?Q?qjL/LZEo0HPCf2TBz36cDSUp0WWaQNfVuontaW0xVclj3MGnTlBJqf4tshCn?= =?us-ascii?Q?aqWpze49to943vT1hwlRnIDgkGZ6mgJ2bE0JlwycQEvSPwqDPgMTcd8k8dDB?= =?us-ascii?Q?94fBUwPEUTZpL9LTp/sDGgiPn+EXqLoG/iSJVP+9VMwIwuIL82W8lFL+GnCf?= =?us-ascii?Q?bOaA33W/52Lu3lrTj4MJU/PPk72sTwBCBe4SaVCn0NIWTsUP/b7urmvNcj+z?= =?us-ascii?Q?MKdqxEKTPsVmX0AoDdMMypYPLF0sYpx/i9pBEkzFEXYJPSPSkDDLPOue6XTj?= =?us-ascii?Q?BALlUw1d0OYPclSUS0XBhvxGzJzZAiKrEGbMbW4i5WSBMgEAJztu1I2u5ufP?= =?us-ascii?Q?b6hIyRK8iVRZLkhkl+p+HwA3GHAOm9Xnz5jq03ndJOyERsHS+khJahshs4Ee?= =?us-ascii?Q?3CqC0iJwQrbQ3mX4GDxHdOJQVPONrBUxydQHEfOFNg93Xz5CClhB8RDQB2oA?= =?us-ascii?Q?WJfCAQHWDJpQrh8Z0tEnbuGCHBidmgoULNHK0mTp1adzWvrH/OU4uyUdP1fE?= =?us-ascii?Q?TO3O+9lxkdsJyB8FAUxjZzia9hQtZyNqxNa5fR+UaCpYpA/k9tytnBcDwPlL?= =?us-ascii?Q?tC2v0u1iQyMFh60buRPeU8sRiy69rl4r0LbcvfJY9pd3ODfvQGlSqFFd2/ma?= =?us-ascii?Q?Yvca9FekyXg4xkSpL0E6+ELctI9WHrz+Ne3E5A+7IcSZzm0dxN1LfUpjdMyf?= =?us-ascii?Q?9wIHal7cOW5bKbAN6KQ0VWNDRM+bEgzEBuUxSjGEzrxE0pOh5Q6GahPv45oF?= =?us-ascii?Q?+31Uh676gpIxuVLF7jouhH5bidipSLyXA9j+LO5IlB/EKSniyOVG3cUIlbWU?= =?us-ascii?Q?v6EUaJggIbdyyUt0og/GnpJIyhYLySe9mYPfDCTv4LaQXHoZejrXaBkhwaug?= =?us-ascii?Q?Rucy9sAGSvxmJsdTww7K0Efa3dS4y7VS5d9k0y7PzUAycKYuXEaJBcu5Tg2M?= =?us-ascii?Q?So0oW4EoBsoNCGtbwUA947Cili5/PkyFUFwRXF478+J7qJ+2mICMRpzSVox3?= =?us-ascii?Q?tRYyijPfmLmV3yK+QT1w3Ad5qDReyS94IBu+cHMAvisRvpcUHSZrOAP2LJmV?= =?us-ascii?Q?nFZ7CdAVS8feXXZjPgV5cyHFdt3kxzFrPkhI5fHp5XuuzNq5Mx/+1nzI0cgv?= =?us-ascii?Q?EcmMF0dakNC1rZjKjx9wC8EPF3+wSmQf9GBz?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Aug 2025 15:17:27.3349 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 07e30710-56aa-4416-e27b-08dde18f0141 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS2PEPF0000343D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH7PR12MB7306 Received-SPF: permerror client-ip=2a01:111:f403:2416::61e; envelope-from=Luc.Michel@amd.com; helo=NAM11-CO1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755876460429116601 Content-Type: text/plain; charset="utf-8" Split the TYPE_XLNX_VERSAL_CRL type into base and concrete classes. This is in preparation for the versal2 version of the CRL. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/misc/xlnx-versal-crl.h | 31 ++++++++++++++++++-- hw/misc/xlnx-versal-crl.c | 48 +++++++++++++++++++------------ 2 files changed, 58 insertions(+), 21 deletions(-) diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versa= l-crl.h index dba6d3585d1..2b39d203a67 100644 --- a/include/hw/misc/xlnx-versal-crl.h +++ b/include/hw/misc/xlnx-versal-crl.h @@ -1,21 +1,27 @@ /* * QEMU model of the Clock-Reset-LPD (CRL). * * Copyright (c) 2022 Xilinx Inc. + * Copyright (c) 2025 Advanced Micro Devices, Inc. * SPDX-License-Identifier: GPL-2.0-or-later * * Written by Edgar E. Iglesias */ #ifndef HW_MISC_XLNX_VERSAL_CRL_H #define HW_MISC_XLNX_VERSAL_CRL_H =20 #include "hw/sysbus.h" #include "hw/register.h" #include "target/arm/cpu-qom.h" +#include "hw/arm/xlnx-versal-version.h" =20 +#define TYPE_XLNX_VERSAL_CRL_BASE "xlnx-versal-crl-base" #define TYPE_XLNX_VERSAL_CRL "xlnx-versal-crl" + +OBJECT_DECLARE_TYPE(XlnxVersalCRLBase, XlnxVersalCRLBaseClass, + XLNX_VERSAL_CRL_BASE) OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) =20 REG32(ERR_CTRL, 0x0) FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) REG32(IR_STATUS, 0x4) @@ -214,22 +220,43 @@ REG32(PSM_RST_MODE, 0x370) =20 #define CRL_R_MAX (R_PSM_RST_MODE + 1) =20 #define RPU_MAX_CPU 2 =20 -struct XlnxVersalCRL { +struct XlnxVersalCRLBase { SysBusDevice parent_obj; + + RegisterInfoArray *reg_array; + uint32_t *regs; +}; + +struct XlnxVersalCRLBaseClass { + SysBusDeviceClass parent_class; +}; + +struct XlnxVersalCRL { + XlnxVersalCRLBase parent_obj; qemu_irq irq; =20 struct { ARMCPU *cpu_r5[RPU_MAX_CPU]; DeviceState *adma[8]; DeviceState *uart[2]; DeviceState *gem[2]; DeviceState *usb; } cfg; =20 - RegisterInfoArray *reg_array; uint32_t regs[CRL_R_MAX]; RegisterInfo regs_info[CRL_R_MAX]; }; + +static inline const char *xlnx_versal_crl_class_name(VersalVersion ver) +{ + switch (ver) { + case VERSAL_VER_VERSAL: + return TYPE_XLNX_VERSAL_CRL; + default: + g_assert_not_reached(); + } +} + #endif diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c index f288545967a..be89e0da40d 100644 --- a/hw/misc/xlnx-versal-crl.c +++ b/hw/misc/xlnx-versal-crl.c @@ -296,21 +296,21 @@ static const RegisterAccessInfo crl_regs_info[] =3D { .reset =3D 0x1, .rsvd =3D 0xf8, } }; =20 -static void crl_reset_enter(Object *obj, ResetType type) +static void versal_crl_reset_enter(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); unsigned int i; =20 for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { register_reset(&s->regs_info[i]); } } =20 -static void crl_reset_hold(Object *obj, ResetType type) +static void versal_crl_reset_hold(Object *obj, ResetType type) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); =20 crl_update_irq(s); } @@ -323,24 +323,26 @@ static const MemoryRegionOps crl_ops =3D { .min_access_size =3D 4, .max_access_size =3D 4, }, }; =20 -static void crl_init(Object *obj) +static void versal_crl_init(Object *obj) { XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + XlnxVersalCRLBase *xvcb =3D XLNX_VERSAL_CRL_BASE(obj); SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); int i; =20 - s->reg_array =3D + xvcb->reg_array =3D register_init_block32(DEVICE(obj), crl_regs_info, ARRAY_SIZE(crl_regs_info), s->regs_info, s->regs, &crl_ops, XLNX_VERSAL_CRL_ERR_DEBUG, CRL_R_MAX * 4); - sysbus_init_mmio(sbd, &s->reg_array->mem); + xvcb->regs =3D s->regs; + sysbus_init_mmio(sbd, &xvcb->reg_array->mem); sysbus_init_irq(sbd, &s->irq); =20 for (i =3D 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, (Object **)&s->cfg.cpu_r5[i], @@ -375,45 +377,53 @@ static void crl_init(Object *obj) OBJ_PROP_LINK_STRONG); } =20 static void crl_finalize(Object *obj) { - XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + XlnxVersalCRLBase *s =3D XLNX_VERSAL_CRL_BASE(obj); register_finalize_block(s->reg_array); } =20 -static const VMStateDescription vmstate_crl =3D { +static const VMStateDescription vmstate_versal_crl =3D { .name =3D TYPE_XLNX_VERSAL_CRL, .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (const VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), VMSTATE_END_OF_LIST(), } }; =20 -static void crl_class_init(ObjectClass *klass, const void *data) +static void versal_crl_class_init(ObjectClass *klass, const void *data) { - ResettableClass *rc =3D RESETTABLE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 - dc->vmsd =3D &vmstate_crl; - - rc->phases.enter =3D crl_reset_enter; - rc->phases.hold =3D crl_reset_hold; + dc->vmsd =3D &vmstate_versal_crl; + rc->phases.enter =3D versal_crl_reset_enter; + rc->phases.hold =3D versal_crl_reset_hold; } =20 -static const TypeInfo crl_info =3D { - .name =3D TYPE_XLNX_VERSAL_CRL, +static const TypeInfo crl_base_info =3D { + .name =3D TYPE_XLNX_VERSAL_CRL_BASE, .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(XlnxVersalCRL), - .class_init =3D crl_class_init, - .instance_init =3D crl_init, + .instance_size =3D sizeof(XlnxVersalCRLBase), + .class_size =3D sizeof(XlnxVersalCRLBaseClass), .instance_finalize =3D crl_finalize, + .abstract =3D true, +}; + +static const TypeInfo versal_crl_info =3D { + .name =3D TYPE_XLNX_VERSAL_CRL, + .parent =3D TYPE_XLNX_VERSAL_CRL_BASE, + .instance_size =3D sizeof(XlnxVersalCRL), + .instance_init =3D versal_crl_init, + .class_init =3D versal_crl_class_init, }; =20 static void crl_register_types(void) { - type_register_static(&crl_info); + type_register_static(&crl_base_info); + type_register_static(&versal_crl_info); } =20 type_init(crl_register_types) --=20 2.50.1