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Fri, 22 Aug 2025 05:27:20 -0700 (PDT) X-Google-Smtp-Source: AGHT+IF4QyhNH/l/h9I8lpEV4/58c9InFecoTq547IY6++qyea3OGvYZ1od1o/0nqOqfoZc6nRZSjg== X-Received: by 2002:a05:6000:22c6:b0:3b9:51db:ba4d with SMTP id ffacd0b85a97d-3c5d4ce14edmr2598032f8f.24.1755865640054; Fri, 22 Aug 2025 05:27:20 -0700 (PDT) From: Paolo Bonzini To: qemu-devel@nongnu.org Cc: tanishdesai37@gmail.com, stefanha@redhat.com, berrange@redhat.com, mads@ynddal.dk Subject: [PATCH 09/14] rust: pl011: add tracepoints Date: Fri, 22 Aug 2025 14:26:50 +0200 Message-ID: <20250822122655.1353197-10-pbonzini@redhat.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250822122655.1353197-1-pbonzini@redhat.com> References: <20250822122655.1353197-1-pbonzini@redhat.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @redhat.com) X-ZM-MESSAGEID: 1755870250646124100 Content-Type: text/plain; charset="utf-8" Finally bring parity between C and Rust versions of the PL011 device model. Changing some types of the arguments makes for nicer Rust code; C does not care. :) Signed-off-by: Paolo Bonzini --- hw/char/trace-events | 14 ++++---- rust/Cargo.lock | 1 + rust/hw/char/pl011/Cargo.toml | 1 + rust/hw/char/pl011/meson.build | 1 + rust/hw/char/pl011/src/device.rs | 57 ++++++++++++++++++++++---------- 5 files changed, 50 insertions(+), 24 deletions(-) diff --git a/hw/char/trace-events b/hw/char/trace-events index 05a33036c12..9e74be2c14f 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -58,15 +58,15 @@ imx_serial_write(const char *chrname, uint64_t addr, ui= nt64_t value) "%s:[0x%03" imx_serial_put_data(const char *chrname, uint32_t value) "%s: 0x%" PRIx32 =20 # pl011.c -pl011_irq_state(int level) "irq state %d" -pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03= x value 0x%08x reg %s" -pl011_read_fifo(unsigned rx_fifo_used, size_t rx_fifo_depth) "RX FIFO read= , used %u/%zu" -pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%0= 3x value 0x%08x reg %s" -pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, size_t rx_fifo_dept= h, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%zu, can_receiv= e %u chars" -pl011_fifo_rx_put(uint32_t c, unsigned read_count, size_t rx_fifo_depth) "= RX FIFO push char [0x%02x] %d/%zu depth used" +pl011_irq_state(bool level) "irq state %d" +pl011_read(uint64_t addr, uint32_t value, const char *regname) "addr 0x%03= " PRIx64 " value 0x%08x reg %s" +pl011_read_fifo(unsigned rx_fifo_used, unsigned rx_fifo_depth) "RX FIFO re= ad, used %u/%u" +pl011_write(uint64_t addr, uint32_t value, const char *regname) "addr 0x%0= 3" PRIx64 " value 0x%08x reg %s" +pl011_can_receive(uint32_t lcr, unsigned rx_fifo_used, unsigned rx_fifo_de= pth, unsigned rx_fifo_available) "LCR 0x%02x, RX FIFO used %u/%u, can_recei= ve %u chars" +pl011_fifo_rx_put(uint32_t c, unsigned read_count, unsigned rx_fifo_depth)= "RX FIFO push char [0x%02x] %d/%u depth used" pl011_fifo_rx_full(void) "RX FIFO now full, RXFF set" pl011_baudrate_change(unsigned int baudrate, uint64_t clock, uint32_t ibrd= , uint32_t fbrd) "new baudrate %u (clk: %" PRIu64 "hz, ibrd: %" PRIu32 ", f= brd: %" PRIu32 ")" -pl011_receive(int size) "recv %d chars" +pl011_receive(size_t size) "recv %zd chars" =20 # cmsdk-apb-uart.c cmsdk_apb_uart_read(uint64_t offset, uint64_t data, unsigned size) "CMSDK = APB UART read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" diff --git a/rust/Cargo.lock b/rust/Cargo.lock index aa13ab2a99a..6ed838f863f 100644 --- a/rust/Cargo.lock +++ b/rust/Cargo.lock @@ -91,6 +91,7 @@ dependencies =3D [ "bits", "qemu_api", "qemu_api_macros", + "trace", ] =20 [[package]] diff --git a/rust/hw/char/pl011/Cargo.toml b/rust/hw/char/pl011/Cargo.toml index 88ef110507d..d71b881f4e1 100644 --- a/rust/hw/char/pl011/Cargo.toml +++ b/rust/hw/char/pl011/Cargo.toml @@ -18,6 +18,7 @@ bilge-impl =3D { version =3D "0.2.0" } bits =3D { path =3D "../../../bits" } qemu_api =3D { path =3D "../../../qemu-api" } qemu_api_macros =3D { path =3D "../../../qemu-api-macros" } +trace =3D { path =3D "../../../trace" } =20 [lints] workspace =3D true diff --git a/rust/hw/char/pl011/meson.build b/rust/hw/char/pl011/meson.build index 16acf12f7cc..5083701d6a7 100644 --- a/rust/hw/char/pl011/meson.build +++ b/rust/hw/char/pl011/meson.build @@ -9,6 +9,7 @@ _libpl011_rs =3D static_library( bits_rs, qemu_api_rs, qemu_api_macros, + trace_rs ], ) =20 diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/devi= ce.rs index 8411db8d00c..bd30b117e92 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -4,6 +4,8 @@ =20 use std::{ffi::CStr, mem::size_of}; =20 +::trace::include_trace!("trace-hw_char"); + use qemu_api::{ chardev::{CharBackend, Chardev, Event}, impl_vmstate_forward, impl_vmstate_struct, @@ -210,13 +212,7 @@ pub(self) fn read(&mut self, offset: RegisterOffset) -= > (bool, u32) { (update, result) } =20 - pub(self) fn write( - &mut self, - offset: RegisterOffset, - value: u32, - char_backend: &CharBackend, - ) -> bool { - // eprintln!("write offset {offset} value {value}"); + pub(self) fn write(&mut self, offset: RegisterOffset, value: u32, devi= ce: &PL011State) -> bool { use RegisterOffset::*; match offset { DR =3D> return self.write_data_register(value), @@ -231,9 +227,11 @@ pub(self) fn write( } IBRD =3D> { self.ibrd =3D value; + device.trace_baudrate_change(self.ibrd, self.fbrd); } FBRD =3D> { self.fbrd =3D value; + device.trace_baudrate_change(self.ibrd, self.fbrd); } LCR_H =3D> { let new_val: registers::LineControl =3D value.into(); @@ -244,7 +242,7 @@ pub(self) fn write( } let update =3D (self.line_control.send_break() !=3D new_va= l.send_break()) && { let break_enable =3D new_val.send_break(); - let _ =3D char_backend.send_break(break_enable); + let _ =3D device.char_backend.send_break(break_enable); self.loopback_break(break_enable) }; self.line_control =3D new_val; @@ -281,12 +279,13 @@ pub(self) fn write( } =20 fn read_data_register(&mut self, update: &mut bool) -> u32 { + let depth =3D self.fifo_depth(); self.flags.set_receive_fifo_full(false); let c =3D self.read_fifo[self.read_pos]; =20 if self.read_count > 0 { self.read_count -=3D 1; - self.read_pos =3D (self.read_pos + 1) & (self.fifo_depth() - 1= ); + self.read_pos =3D (self.read_pos + 1) & (depth - 1); } if self.read_count =3D=3D 0 { self.flags.set_receive_fifo_empty(true); @@ -294,6 +293,7 @@ fn read_data_register(&mut self, update: &mut bool) -> = u32 { if self.read_count + 1 =3D=3D self.read_trigger { self.int_level &=3D !Interrupt::RX; } + trace::trace_pl011_read_fifo(self.read_count, depth); self.receive_status_error_clear.set_from_data(c); *update =3D true; u32::from(c) @@ -449,7 +449,9 @@ pub fn fifo_rx_put(&mut self, value: registers::Data) -= > bool { self.read_fifo[slot] =3D value; self.read_count +=3D 1; self.flags.set_receive_fifo_empty(false); + trace::trace_pl011_fifo_rx_put(value.into(), self.read_count, dept= h); if self.read_count =3D=3D depth { + trace::trace_pl011_fifo_rx_full(); self.flags.set_receive_fifo_full(true); } =20 @@ -518,8 +520,21 @@ unsafe fn init(mut this: ParentInit) { uninit_field_mut!(*this, clock).write(clock); } =20 - const fn clock_update(&self, _event: ClockEvent) { - /* pl011_trace_baudrate_change(s); */ + pub fn trace_baudrate_change(&self, ibrd: u32, fbrd: u32) { + let divider =3D 4.0 / f64::from(ibrd * (FBRD_MASK + 1) + fbrd); + let hz =3D self.clock.get_hz(); + let rate =3D if ibrd =3D=3D 0 { + 0 + } else { + ((hz as f64) * divider) as u32 + }; + trace::trace_pl011_baudrate_change(rate, hz, ibrd, fbrd); + } + + fn clock_update(&self, _event: ClockEvent) { + let regs =3D self.regs.borrow(); + let (ibrd, fbrd) =3D (regs.ibrd, regs.fbrd); + self.trace_baudrate_change(ibrd, fbrd) } =20 pub fn clock_needed(&self) -> bool { @@ -545,6 +560,7 @@ fn read(&self, offset: hwaddr, _size: u32) -> u64 { } Ok(field) =3D> { let (update_irq, result) =3D self.regs.borrow_mut().read(f= ield); + trace::trace_pl011_read(offset, result, c""); if update_irq { self.update(); self.char_backend.accept_input(); @@ -559,6 +575,7 @@ fn write(&self, offset: hwaddr, value: u64, _size: u32)= { if let Ok(field) =3D RegisterOffset::try_from(offset) { // qemu_chr_fe_write_all() calls into the can_receive // callback, so handle writes before entering PL011Registers. + trace::trace_pl011_write(offset, value as u32, c""); if field =3D=3D RegisterOffset::DR { // ??? Check if transmitter is enabled. let ch: [u8; 1] =3D [value as u8]; @@ -567,10 +584,7 @@ fn write(&self, offset: hwaddr, value: u64, _size: u32= ) { let _ =3D self.char_backend.write_all(&ch); } =20 - update_irq =3D self - .regs - .borrow_mut() - .write(field, value as u32, &self.char_backend); + update_irq =3D self.regs.borrow_mut().write(field, value as u3= 2, &self); } else { log_mask_ln!( Log::GuestError, @@ -584,11 +598,19 @@ fn write(&self, offset: hwaddr, value: u64, _size: u3= 2) { =20 fn can_receive(&self) -> u32 { let regs =3D self.regs.borrow(); - // trace_pl011_can_receive(s->lcr, s->read_count, r); - regs.fifo_depth() - regs.read_count + let fifo_available =3D regs.fifo_depth() - regs.read_count; + trace::trace_pl011_can_receive( + regs.line_control.into(), + regs.read_count, + regs.fifo_depth(), + fifo_available, + ); + fifo_available } =20 fn receive(&self, buf: &[u8]) { + trace::trace_pl011_receive(buf.len()); + let mut regs =3D self.regs.borrow_mut(); if regs.loopback_enabled() { // In loopback mode, the RX input signal is internally disconn= ected @@ -637,6 +659,7 @@ fn reset_hold(&self, _type: ResetType) { fn update(&self) { let regs =3D self.regs.borrow(); let flags =3D regs.int_level & regs.int_enabled; + trace::trace_pl011_irq_state(flags !=3D 0); for (irq, i) in self.interrupts.iter().zip(IRQMASK) { irq.set(flags.any_set(i)); } --=20 2.50.1