From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755871046; cv=none; d=zohomail.com; s=zohoarc; b=buatlkP5rlHU0Hzb4YyefQXkFD41bZXMrU7VTKQAqY/Y3RdJXvKgVhS3ZvB8b2VGQiSFIi9AVj2hHsxabXZX0bnYwkKY3ZiRoMH2E5r+wOzXND7+l4W4RcI5KTtiDxdMtwnIVqBMuuuly3Rfx3urNJw5EnR7p6iaTO4eCZcu2AU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755871046; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=zCby+eLrg4GAHoTlGaZ+HvxqNUEpTOhGwkTAgVF2XVQ=; b=kSTpTEdPTI81TtNPD03Iv1v/1owuXpglGULP8qDraTAdypRe5YjR3Xq7nqiQ4YOVlMR2zKzy/VwnGm0FLJ6Fa/rfBhXVlEtdsDobrN5s6O3VXcF9YZx1ngGppgOzcQEIX9U+r07WYJXQgzfzBECDeo4HGvS/0h92xxVDgO0gZi8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755871046815889.0400372528709; Fri, 22 Aug 2025 06:57:26 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upSDQ-0005tF-VQ; Fri, 22 Aug 2025 09:54:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upO1M-0005aD-4t for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:16 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1upO1F-00077Z-Ja for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:15 -0400 Received: by mail-pl1-x631.google.com with SMTP id d9443c01a7336-245f19aab74so14594105ad.0 for ; Fri, 22 Aug 2025 02:25:09 -0700 (PDT) Received: from warg.hq.igel.co.jp (napt.igel.co.jp. [219.106.231.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4c6fb7sm78560215ad.89.2025.08.22.02.25.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 02:25:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igel-co-jp.20230601.gappssmtp.com; s=20230601; t=1755854707; x=1756459507; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=zCby+eLrg4GAHoTlGaZ+HvxqNUEpTOhGwkTAgVF2XVQ=; b=smxz4qOjekaPlYatmjCZX2+1yw+qAm94ZfmUiUPcX/WHVhSgyqKf+by/sMgJkBSeCv U+qp4xqfXgCTmXQix+L592Zlb2LwcJDwiUOEdJQ3gcT8FG/sO2ha/7wWxrzEkrQr5f23 UP+riUrwkxrJLTE1ubbrHwhEZX2LssEd22KLjP24bJmpVjmYvFm1lLCuvKbJamoOirF/ xLoAbWg4HTQJ8fIShFRkQ7tZhn7OCQeeJPc5LofnQFD9g+uEejzPZaW/kk30zO5E504/ 5dWyQ8RXMo0wVN7IJ0sNrddkST75BpW529zgk41lAfBths9vOMPpWQZbyRmIe3BpKrUE 7fmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755854707; x=1756459507; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=zCby+eLrg4GAHoTlGaZ+HvxqNUEpTOhGwkTAgVF2XVQ=; b=C7tdF8p7CpTddQnHXF8rYMSFmuQlxE71ShJx+8kLsbIHV+8n7uxLiogpimQQXDYjfv N/g/o3/ifq22tU4jr1LymVv0g/VPLpopkYdRX6/sF9BLWoZe5s1XblK33xeytczOrlBt k6JWhfag+Rev/Z4GFsf3396qWTRllJ+IuXNu0TIyiTuHrOYs+XqG6G/v9Xe0GHupi7nS UzTxePirVjD7MAm0f2lGRtChiE8wh2zkWE/tUyNwyaLGXrOThVNH5DUicGxGHJyGvyhC Z5SyWB87uV9jG1T72Cbf7z8XY77FPwt44qa4eNeThyPnGm33tiFJJuy/6b24rxw8RusB T3hQ== X-Gm-Message-State: AOJu0YyW2iHmXI/U0nFpZnZx/tmJ9jKgkENSC6Z9uX5yZUcLJfCwIGYx 6Vp4EkeLMWJHnlE/3vdfWmf6K/OOL9/N10I7mnrV2gD22VsWzN9nthLJMRI91fg7ZXm1XpfKWXQ 12l+9AEE= X-Gm-Gg: ASbGncsJtoM9Cz4di8+g6beqfR/i26CoHgAz60NSva8Fg4yLAWbUAtPkHJ0QLH66MDi z+YSkF1RAe5ioIxPsR6tXHRxM2hy5UNisAmJMIyzhMkH3QJ+t9brA/AVJ1Zot9jfppUnTnfjNDR iYSaUv8qirYz6eABosZqD33zSuR6ea+4IVUDGJ3WWaFToXawvKqfMIaLYBaenFEFIzD6s80XbXU v/4IRiGZDOupUOBb3sEG3PBx4Qv/cczwpTdcpYjfCIZb9LnARqjCys97JFlHUB3gByO48sFvHiV YCb9V1b74KdHM3baVswvjOtyohoZRfPzVB/S0QhynSs2zVlVwEZJNyQ/6Ib/WF3Pl4/UarACmeQ c23qUzl2YG7TE22E+sskVAQpnPvE+t7ngK0ujQ1TZGA== X-Google-Smtp-Source: AGHT+IF0Xwuu5LZYmRduWk25dRQ4N23vj9IjGYBGoJ9IRke8ciqE9vsRzsdrjU7wgvFYWKAZPSqDoA== X-Received: by 2002:a17:903:1ac4:b0:240:66ff:b253 with SMTP id d9443c01a7336-2462ef93318mr30091655ad.46.1755854707455; Fri, 22 Aug 2025 02:25:07 -0700 (PDT) From: CJ Chen To: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org Cc: Paolo Bonzini , Keith Busch , Klaus Jensen , Jesper Devantier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tyrone Ting , Hao Wu , Max Filippov , Peter Xu , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Tomoyuki Hirose , Peter Maydell , CJ Chen Subject: [RFC PATCH v2 1/9] doc/devel/memory.rst: additional explanation for unaligned access Date: Fri, 22 Aug 2025 18:24:02 +0900 Message-Id: <20250822092410.25833-2-cjchen@igel.co.jp> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822092410.25833-1-cjchen@igel.co.jp> References: <20250822092410.25833-1-cjchen@igel.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=cjchen@igel.co.jp; helo=mail-pl1-x631.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 22 Aug 2025 09:53:58 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @igel-co-jp.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1755871050023124100 Add documentation to clarify that if `.valid.unaligned =3D true` but `.impl.unaligned =3D false`, QEMU=E2=80=99s memory core will automatically = split unaligned guest accesses into multiple aligned accesses. This helps devices avoid implementing their own unaligned logic, but can be problematic for devices with side-effect-heavy registers. Also note that setting `.valid.unaligned =3D false` together with `.impl.unaligned =3D true` is invalid, as it contradicts itself and will trigger an assertion. Signed-off-by: CJ Chen Acked-by: Tomoyuki Hirose Suggested-by: Peter Maydell --- docs/devel/memory.rst | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/docs/devel/memory.rst b/docs/devel/memory.rst index 57fb2aec76..71d7de7ae5 100644 --- a/docs/devel/memory.rst +++ b/docs/devel/memory.rst @@ -365,6 +365,24 @@ callbacks are called: - .impl.unaligned specifies that the *implementation* supports unaligned accesses; if false, unaligned accesses will be emulated by two aligned accesses. +- Additionally, if .valid.unaligned =3D true but .impl.unaligned =3D false= , the + memory core will emulate each unaligned guest access by splitting it into + multiple aligned sub-accesses. This ensures that devices which only hand= le + aligned requests do not need to implement unaligned logic themselves. For + example, see xhci_cap_ops in hw/usb/hcd-xhci.c: it sets .valid.unaligned + =3D true so guests can do unaligned reads on the xHCI Capability Registe= rs, + while keeping .impl.unaligned =3D false to rely on the core splitting lo= gic. + However, if a device=E2=80=99s registers have side effects on read or wr= ite, this + extra splitting can introduce undesired behavior. Specifically, for devi= ces + whose registers trigger state changes on each read/write, splitting an a= ccess + can lead to reading or writing bytes beyond the originally requested sub= range + thereby triggering repeated or otherwise unintended register side effect= s. + In such cases, one should set .valid.unaligned =3D false to reject unali= gned + accesses entirely. +- Conversely, if .valid.unaligned =3D false but .impl.unaligned =3D true, + that setting is considered invalid; it claims unaligned access is allowed + by the implementation yet disallowed for the device. QEMU enforces this = with + an assertion to prevent contradictory usage. =20 API Reference ------------- --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755871104; cv=none; d=zohomail.com; s=zohoarc; b=UtkECT4k6rOW16fvc8TPLrTHdfFT9zY72Fd2qwDd+ljgTJHN50onFsQ5ATaDTvE6/ahya7fns3dXjY2UvzXCCf+f3JvZZIKVs3ycirN7irP2lQCC69Pwg/p9jU6qjRP25+8QYroTFqpQFZhgCJEvIU70uJ/qL3qjXZta7wu/02w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755871104; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=mlo0VNE2LkX+k6ixV83bmWbI8LIl4VVBBmVNmXeQQcY=; b=jABhYJDyDezfaFlFJ98bOZZCsk8oYwcvK6Ai1J1OaRQwKnG63dpE+MM5BUcr+hGMc3wpVaFj0ebqjSzWM7ErJDziUUb7UhTRaVsFbi77vBPHK8wL7RxNt1X0q0ew40gTTtYBInXY04FE9idl1YZu50G/O1dxsA1NYaDIsAr6bmw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755871104255861.7257474094797; Fri, 22 Aug 2025 06:58:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upSDW-0005vP-J9; Fri, 22 Aug 2025 09:54:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upO1Q-0005cm-1M for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:20 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1upO1M-000792-Cj for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:19 -0400 Received: by mail-pg1-x535.google.com with SMTP id 41be03b00d2f7-b49c622e598so137810a12.1 for ; Fri, 22 Aug 2025 02:25:15 -0700 (PDT) Received: from warg.hq.igel.co.jp (napt.igel.co.jp. [219.106.231.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4c6fb7sm78560215ad.89.2025.08.22.02.25.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 02:25:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igel-co-jp.20230601.gappssmtp.com; s=20230601; t=1755854714; x=1756459514; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=mlo0VNE2LkX+k6ixV83bmWbI8LIl4VVBBmVNmXeQQcY=; b=gHlpWm/esdPlDf6OBTQA7j9IL58URUKNJ0ypl7KeyPyy08LqL136YGcVIR5dnkvhRM D31OB5pb2A36D7g9zEb8ePHOJPr7cdsNh17PgXh4SQaLp6GvjkAuKeD1qVoL2XvDPueB LmmTrstfjrYf8b+fKHtwP01Ch/obmqPSUI5hebbJ86QYdt0qHVYzHlQsa3u+1z5AiF/k nyyE5JhkLvgRS/cOnxTLmoMavA4IARyEM0sbEzJdzHfZqnQwAOXJtF2AvR8QnPmHnpY+ 80ufSJoKrpnPDXps6WynkWrmvAtTbD+qjVzBLInJun54WGVFd8lC2xmW+hhRGTPUaCmq fY2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755854714; x=1756459514; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=mlo0VNE2LkX+k6ixV83bmWbI8LIl4VVBBmVNmXeQQcY=; b=v4TtVMhs1NzXghMduwyd2VdC7j31A0Oi5mAKxA9zvh/Yq9u8tsu5QLDqKuUXkXq7a/ birS3llMyzz/cTLFPiSIQh06x5QZppScz3Icy2P2ODEhGAI31vjRfzlUUY0+b1nH2788 HaDnlCu5UybNFxlJj/DiEaeONrpQOyUuF2ELkmK/erBxZuDEC8V79KPZbvaWcXXux1Kh VZRMFHz8C58lKMXB+F2/i/eV0kn3/7a6L+ucsZn0L5Sjus50WspNMPpIRXcMymqOYja3 ofk1ajT3YOBmGD6QZuSbrRoQZG/LIf5hzMNabhIMFPeF7OHLnc1OjRiKezSph5OMD292 zr2Q== X-Gm-Message-State: AOJu0YxzE7kRNh+QgXb5W4Wc+rqPlE4UmXN1rJRm8PI8bGXv59Yw7WX9 EVdm8tspIbXPTsgbnhZO1Epm6/5dWFO1IQKEUliFiHQ1lWSO8/bEEnmO5PRO4AIwUCGTCkA4bpI SOX3IkIk= X-Gm-Gg: ASbGncvlesa3rpUoGqKN1YPQ8ul8yyhFscQ2vmUVY3UBlvsUB2kANyH4PuowY0p3JnS Edq2pcXZGFveKrMccyZr/jdIFhRWn8u9rhtH5bsLvRyaNxHgAYCFgoAxVJv1ednOdBHLV6lwAZd RYH3VssI1HhnKcvquK1vAlkdZkb26lbDr0MvoWR805vPBWDXEoQ+X8DKg+0SEOU/noA6iIWlHms m9r/3fUXtJ6LAR4qcRBgw8Z3YThKE5VqUqv2Eq1wuCrWj1TjLLW7DBHasZfrBB8K63n76Xt1Icg aRFOl/2zju5xIx+JsjgpjaPrTWsEnssgVZJ5K8hAtSdhdcjox7tLLwJg5rp2/Va0HYoQgQQ+5pQ hVeuhrCVglAa/FQbFcKBLlKpuOQu1IgpZJyb2nk2+EwoSWXicV8dP+l0EXciVbQQ= X-Google-Smtp-Source: AGHT+IEqxrEnh0zkYioghUeAJylIvzfIK34NEJeRhP+7uR5uCgzNq3nYAwgrwA28HLoaAtq27/RD1g== X-Received: by 2002:a17:903:2302:b0:240:3b9e:dd4c with SMTP id d9443c01a7336-2462ef446b7mr34309165ad.36.1755854714249; Fri, 22 Aug 2025 02:25:14 -0700 (PDT) From: CJ Chen To: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org Cc: Paolo Bonzini , Keith Busch , Klaus Jensen , Jesper Devantier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tyrone Ting , Hao Wu , Max Filippov , Peter Xu , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Tomoyuki Hirose , Peter Maydell , CJ Chen Subject: [RFC PATCH v2 2/9] hw/riscv: iommu-trap: remove .impl.unaligned = true Date: Fri, 22 Aug 2025 18:24:03 +0900 Message-Id: <20250822092410.25833-3-cjchen@igel.co.jp> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822092410.25833-1-cjchen@igel.co.jp> References: <20250822092410.25833-1-cjchen@igel.co.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=cjchen@igel.co.jp; helo=mail-pg1-x535.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 22 Aug 2025 09:53:58 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @igel-co-jp.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1755871104912116600 Content-Type: text/plain; charset="utf-8" Since riscv-iommu does not support unaligned accesses, drop `.impl.unaligned =3D true` to avoid the contradictory pairing with `.valid.unaligned =3D false`. This makes QEMU reject unaligned accesses for this device and prevents the assertion in memory.c that previously caused `make check` to fail. Signed-off-by: CJ Chen Tested-by: CJ Chen Acked-by: Tomoyuki Hirose Reported-by: Tomoyuki Hirose Reviewed-by: Daniel Henrique Barboza --- hw/riscv/riscv-iommu.c | 1 - 1 file changed, 1 deletion(-) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index a877e5da84..277746598a 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -2288,7 +2288,6 @@ static const MemoryRegionOps riscv_iommu_trap_ops =3D= { .impl =3D { .min_access_size =3D 4, .max_access_size =3D 8, - .unaligned =3D true, }, .valid =3D { .min_access_size =3D 4, --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755870994; cv=none; d=zohomail.com; s=zohoarc; b=e9+cQpfWJ6ZkkwhK/AAA0I/KQqajwYNxm68yRIY2kICVEAKWENdTkMJC6CobxjH3/KlkfulfSuVew/yZNBn/sAIuHrHSyDbVRQHH1Fm+bj1kwDgzd7BGh85eO/4dhuqyC87eSiPGs0cO/qpKffbFzZH5UmZlpJoPdhzFo+hTN48= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755870994; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=CPBXmwU1P2JOttDvf/F4AUriHtbYHkfUE8krSjFXNTI=; b=Bjl8EAlcA47Zqd2v1RyCXIgTryYL/GwZukEeSZTkcSyHnYo2uWgWf4MnMNg1K74bXWtZWcRgl/LL+q12mZ8tf12bKjIp0ezvjuxWheVW5qBeKKBOgHhFUFsZP3N5Z8bB4TySxI3otnlfVwPaXuhCEWwyEYDrA5O99vaeyCfaNb4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175587099497572.45021682246238; Fri, 22 Aug 2025 06:56:34 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upSDZ-0005z3-BZ; Fri, 22 Aug 2025 09:54:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upO1W-0005hk-Ll for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:26 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1upO1T-0007Af-1B for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:26 -0400 Received: by mail-pl1-x62a.google.com with SMTP id d9443c01a7336-24458194d83so16197505ad.2 for ; Fri, 22 Aug 2025 02:25:22 -0700 (PDT) Received: from warg.hq.igel.co.jp (napt.igel.co.jp. [219.106.231.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4c6fb7sm78560215ad.89.2025.08.22.02.25.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 02:25:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igel-co-jp.20230601.gappssmtp.com; s=20230601; t=1755854721; x=1756459521; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=CPBXmwU1P2JOttDvf/F4AUriHtbYHkfUE8krSjFXNTI=; b=0hyhumnHT+wzjxI3l5lQ9w0ReGx82Z/8UJBX6STsFLkQFkhwawLw0/dGvjvrhxs7v5 9MW2s+0D0fWAQKH5SZQENaXmS71uF+FfJDu+pQqoNNemiw4c13CWb/Ec99L6iX49yQLw 9EGCOpA5xDTW+lRicn0IxN6hDpbR6VbcK3WsB8ieV2DcL743e7eu8AzqtcNnvFIBvrNj YVm7wP/GJKDHCDSPA6s0KjFaO6V60xBClkkTk6Zb4AoEPKYnk/A3NLq9A6gczX+hd+H/ d0RHzTUDG2/m3GKGFl5I3bx3b0BvrwIfbIXRQX3w/9mOZHQVIM0x01CERVWSP1MRSdMr 3biA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755854721; x=1756459521; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=CPBXmwU1P2JOttDvf/F4AUriHtbYHkfUE8krSjFXNTI=; b=cpj73OZlm4bDuDQrB+Z8YK7CEZj4nn2YKt7O9eIMoeKzq/u6KWQnWpeByiwmYPQrRJ nQhkt9+nLzLVzERgfce910Fz+fd3W1A1d8akAZ4xBFyIoUkB1qhw9GsPQIWASzFHxiDJ YkB6WCvrCAHcnTU0e4GO+eKGrVUcVvpXXaqbXDXndVb5k+lx9FMZb+2/N7tDTgEGSG34 QOb26uF4wmf7Is7C6RwO0ymfvd2S207DPueo02C3y5/iaOUpVxJbOsANfI1FeObjICvD arai83vmHRkSgOdDsZBWf6xu5/EdPOHDM8cLY0iey73r5/7Syt4Zv2NnSPR/9yw6DThK y7qQ== X-Gm-Message-State: AOJu0YwTIdA9FwM9asMffYZRBAMJcLt5baZcLZWbGjydv3kFeFwNU7L+ zxsGTflTXX+O0g5V+5ObryyiJdOyGve61R+87gbdsuRYBK9G12zVJBcwfC+jYVRNLYPLIzLTQaW qkUu8zt4= X-Gm-Gg: ASbGncvTdMMOfuJXMG/ikp+C94Kd4r/DfS1JvB89pauLOQyPZKTJs3rD5BLmjwGlSAa T8Ud+Z3V5g2Hb2MxuCXn5PMW3roWaIVf7a8rKlkI3Ep8ZtU4RdrPVODUQ9dyBcsGwHctELUhZ56 aG0o5oV1pmPd9Sn45Yt8mF1ynfR/yAO/fidcHRcJicl4eT69zCNhZPpzFQNCYba32NEpcq/06sq /NkwGqZQWvPNJE4cRSMHNehUcaqxN0cCyxFLEB5hxtLyHPaXZMZwAlKQInETEWTaOLwP0vu+97Q 31LoqL4CnJeuFKJ2pq89JhM7mdDcqh1ihnVDTgudur0cui9IWqp0IO9Sgr9gy5EDeqKwsFUoaQA lrk1YYcjTdywyJ5tobmvwqaK1gczd4+8Y88qgwAqjkxJeB1/S6gNv X-Google-Smtp-Source: AGHT+IFjvo9bWFDlURrx68v+zTGIpikr6/j0R2yKpRo9yWHk3zInG5YNv7tU7I9P2qs4WDy/XMZHDA== X-Received: by 2002:a17:902:da85:b0:234:c8f6:1afb with SMTP id d9443c01a7336-2462eb37ab9mr32227985ad.0.1755854720839; Fri, 22 Aug 2025 02:25:20 -0700 (PDT) From: CJ Chen To: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org Cc: Paolo Bonzini , Keith Busch , Klaus Jensen , Jesper Devantier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tyrone Ting , Hao Wu , Max Filippov , Peter Xu , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Tomoyuki Hirose , Peter Maydell , CJ Chen Subject: [RFC PATCH v2 3/9] hw: npcm7xx_fiu and mx_pic change .impl.unaligned = true Date: Fri, 22 Aug 2025 18:24:04 +0900 Message-Id: <20250822092410.25833-4-cjchen@igel.co.jp> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822092410.25833-1-cjchen@igel.co.jp> References: <20250822092410.25833-1-cjchen@igel.co.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=cjchen@igel.co.jp; helo=mail-pl1-x62a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 22 Aug 2025 09:53:58 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @igel-co-jp.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1755870997462124100 Content-Type: text/plain; charset="utf-8" By setting .impl.unaligned =3D true, we allow QEMU to pass along unaligned requests directly as-is, rather than splitting them into multiple aligned sub-requests that might cause repeated device callbacks or unintended side effects. Signed-off-by: CJ Chen Tested-by: CJ Chen Acked-by: Tomoyuki Hirose Reported-by: Tomoyuki Hirose --- hw/ssi/npcm7xx_fiu.c | 3 +++ hw/xtensa/mx_pic.c | 3 +++ 2 files changed, 6 insertions(+) diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index 056ce13394..10ee4deb31 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -255,6 +255,9 @@ static const MemoryRegionOps npcm7xx_fiu_flash_ops =3D { .max_access_size =3D 8, .unaligned =3D true, }, + .impl =3D { + .unaligned =3D true, + }, }; =20 /* Control register read handler. */ diff --git a/hw/xtensa/mx_pic.c b/hw/xtensa/mx_pic.c index 8211c993eb..6bf524a918 100644 --- a/hw/xtensa/mx_pic.c +++ b/hw/xtensa/mx_pic.c @@ -270,6 +270,9 @@ static const MemoryRegionOps xtensa_mx_pic_ops =3D { .valid =3D { .unaligned =3D true, }, + .impl =3D { + .unaligned =3D true, + }, }; =20 MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx, --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755871121; cv=none; d=zohomail.com; s=zohoarc; b=bFXkMqwbCbMP/0qdkyrx6ICOsorwQHxAXRep19beSkdlNmGtgxVpOtIJSWh0LOcxEo61dOB/FErSdCkZzeiRy3m7dDjPcz5PW6+OhsiUy54BGVHDb2pEf5y5koFbzGMGur48964932HzksVWxCdGxC8dV8bBHLBuk6sLdg/FTvg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755871121; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2LelFaXu4nBaY9dT35+wlto5FIYzudNjlsl9EfmiZ5M=; b=l/Zp9Hl39OFrPIlLv9IjRy0u2HK1OSz96HfncGZI/z0UOXvwB0yqRswKFMJc4T8vUyuG3Y2CpbgNYiwpzXDResHNDBo336UFzQlzM2acnYqUX3hc5fbVvJZYvLwhiKAcxb18hsCwWB+GnUrMgWUa0wKmUNI4bSgKuStpzvBj7/4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755871121416691.9025817484359; Fri, 22 Aug 2025 06:58:41 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upSDX-0005vq-3a; Fri, 22 Aug 2025 09:54:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upO1f-0005pj-G0 for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:36 -0400 Received: from mail-pl1-x62c.google.com ([2607:f8b0:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1upO1a-0007Bo-UH for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:34 -0400 Received: by mail-pl1-x62c.google.com with SMTP id d9443c01a7336-24458272c00so20901255ad.3 for ; Fri, 22 Aug 2025 02:25:29 -0700 (PDT) Received: from warg.hq.igel.co.jp (napt.igel.co.jp. [219.106.231.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4c6fb7sm78560215ad.89.2025.08.22.02.25.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 02:25:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igel-co-jp.20230601.gappssmtp.com; s=20230601; t=1755854727; x=1756459527; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=2LelFaXu4nBaY9dT35+wlto5FIYzudNjlsl9EfmiZ5M=; b=2R5rzeR8InbtkyQo0P+AOoUt6iDP30ONkSIVG/0yTNb+ahyVL0I0n24yUL8floJWOU WTmXAuUX7mtKzkIDdmZm9zJ10BxRXHsvJvGyf2Lni0cZGrwKP2sWZciBCGXBPhs3iDr5 rTtW3UXJ8w/eaAnit5w99PBOG9wHZTgWHwijCwuHJo7+NbLs1YQ/Rz62tfkNJ8IwT812 XQ79chaVxbocuAHWZa2pY5QOvXI7iHVjCKhi/7/CimleexWo9qRWCXwT8T+Mf7lxyvML kDi0ieP6vfq71M7V6Yt9wMb9lTcgXIp3o/6iiA4uheBEKLt5bObQd3J83LvFsF/nsUj8 pXpw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755854727; x=1756459527; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2LelFaXu4nBaY9dT35+wlto5FIYzudNjlsl9EfmiZ5M=; b=WFFzsZL4lX21ocrpYtZRXBfGk7wkJA4URwUlLwIrns04dQrGH5ZnttGCMfBKBeKGUQ L+CXHSthov1LDgX7W+fTZ3n66WtfScVmQjvYON3qdnajLCCwTKG8HhrIvuN8WRVo2x2L juiCEhqdKmCR46JAN7f7bpEkrY2YT0LMCu5VXLtex9+T4sacbp7g2If0xBcyAo39Xs4s UW0r9Losyd7qbzvoOJkVq2jBWVEQQNjizgF91o2ypQvFFDJq6mtfEXUvcJ+J33hvkX3L 3L8+cFsSJkIt4H9zprscooQJqG3jsCz9uEGGgO6Vex2l4nTxxhfNT0UVY5PMlhZZYktN N/ug== X-Gm-Message-State: AOJu0YyQQRPFHdm6kX2kkF6K80vrAOy+YJh/ry3Ju4LnT99XI9jwKAKz d6aG7MLbuur1sOA9A+W9iDwC6UV7SXejraUj1Bi7WlBBoMW190Oev5NTWHU+LhRFSdCxGeGnr2o rtEqzsDQ= X-Gm-Gg: ASbGncvgwPTQcRIOva4EaTULeaeD7qx+tbxNKVcpIrv5FrayqzXMJW8VOLNzdoNciAF RBu8o80WHhEp7lyeN/+oPh/C9MD6E04RPz92q9pMI/pZ28xjkjEyeXtDUYoUJDFA7qnPIVbDO18 +1p+ofiCphh/KpVCAd80XVutBlpaPIAPi7HBZ9Bxln3YvcrBQ9191MjZrvjPKVcZ4qpYjuwM5Rx bxFEpA1RoP0lj5CpbZWIZ5syM4NhirIIrehicPqTAzZ+BDhlh3hB0WfQz+5i7xi96fvkLkmte/y DI3JzKHwANWCSoMs/ZNBhxUAhB8Hqr691OyN1T3xb9e2FH0WwlNEqFcFv4za+gm/9hPvbsZGoWs egBogQymOjVQf9FFaxUWIONwNivuR0YS0rd5z2agOxZ5x4/35o+4j X-Google-Smtp-Source: AGHT+IHwO6/ISB0j/F3Fu/FL8iXEouvPElKuNTjaAa80YP6la6HrQCx45MOnxFn2E7Ame5lgK/uVxw== X-Received: by 2002:a17:903:94f:b0:246:4417:db76 with SMTP id d9443c01a7336-2464417dd58mr21785165ad.5.1755854727321; Fri, 22 Aug 2025 02:25:27 -0700 (PDT) From: CJ Chen To: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org Cc: Paolo Bonzini , Keith Busch , Klaus Jensen , Jesper Devantier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tyrone Ting , Hao Wu , Max Filippov , Peter Xu , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Tomoyuki Hirose , Peter Maydell , CJ Chen Subject: [RFC PATCH v2 4/9] hw/nvme/ctrl: specify the 'valid' field in MemoryRegionOps Date: Fri, 22 Aug 2025 18:24:05 +0900 Message-Id: <20250822092410.25833-5-cjchen@igel.co.jp> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822092410.25833-1-cjchen@igel.co.jp> References: <20250822092410.25833-1-cjchen@igel.co.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=cjchen@igel.co.jp; helo=mail-pl1-x62c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 22 Aug 2025 09:53:58 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @igel-co-jp.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1755871122867124100 Content-Type: text/plain; charset="utf-8" From: Tomoyuki Hirose 'valid' field in MemoryRegionOps struct indicates how the MemoryRegion can be accessed by the guest. In the previous code, the 'valid' field was not specified explicitly. As a result, the CMB area could only be accessed in units of 4 bytes. This commit specifies the 'valid' field in MemoryRegionOps of CMB and the CMB area can be accessed in units of 8 bytes. Signed-off-by: CJ Chen Based-on-a-patch-by: Tomoyuki Hirose Tested-by: CJ Chen Reported-by: Tomoyuki Hirose --- hw/nvme/ctrl.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index fd935507bc..9dca718ca1 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8272,6 +8272,11 @@ static const MemoryRegionOps nvme_cmb_ops =3D { .min_access_size =3D 1, .max_access_size =3D 8, }, + .valid =3D { + .unaligned =3D true, + .min_access_size =3D 1, + .max_access_size =3D 8, + }, }; =20 static bool nvme_check_params(NvmeCtrl *n, Error **errp) --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755871097; cv=none; d=zohomail.com; s=zohoarc; b=TnhQWnSx0PY9npBrOgzNN6aaiyYWjHLsCa6TGcOVtDKroJPF7qovpeIf6Z6zkx+feK9rIUeWnM4/q7RVCYHFYRgb5wfhrCw+4B++5uWbJQgwDbgccqcFv8JOcZG/CRhlzRm7AL51mCKdVSK4EpDt86Oo9QcGYKB7rAtL/1aIy/w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755871097; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=R20a+AC/qNPmE0yIiAxw+Sd4sMt8EwUMqbCQvSGoLUU=; b=MHr42RHKxgh/ai2ElQ1a2jGz570WomxSwdPayTV7G7l6ieNRa6Fr7Y0+KDyzXfC3dq6ZU0HbF7ub8bu3ZfF1P+gld5FmdbXqHwkebwHSVoCAu338ki7545HqKYvsJFCDw2lP1XmImspTPxX79lCv7nAwHJMM4PLWpimJyZhBXHo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755871096912618.7447103685552; Fri, 22 Aug 2025 06:58:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upSDa-00062J-Ca; Fri, 22 Aug 2025 09:54:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upO1l-0005uG-OC for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:42 -0400 Received: from mail-pl1-x632.google.com ([2607:f8b0:4864:20::632]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1upO1g-0007DG-N6 for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:41 -0400 Received: by mail-pl1-x632.google.com with SMTP id d9443c01a7336-24457f581aeso14254775ad.0 for ; Fri, 22 Aug 2025 02:25:36 -0700 (PDT) Received: from warg.hq.igel.co.jp (napt.igel.co.jp. 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But this implementation could not emulate specific registers of some devices that allow unaligned access such as xHCI Host Controller Capability Registers. This commit emulates an unaligned access with multiple aligned accesses. Additionally, the overwriting of the max access size is removed to retrieve the actual max access size. Based-on-a-patch-by: Tomoyuki Hirose Signed-off-by: CJ Chen Tested-by: CJ Chen Reported-by: Tomoyuki Hirose --- system/memory.c | 147 ++++++++++++++++++++++++++++++++++++++--------- system/physmem.c | 8 --- 2 files changed, 119 insertions(+), 36 deletions(-) diff --git a/system/memory.c b/system/memory.c index 63b983efcd..d6071b4414 100644 --- a/system/memory.c +++ b/system/memory.c @@ -509,27 +509,118 @@ static MemTxResult memory_region_write_with_attrs_ac= cessor(MemoryRegion *mr, return mr->ops->write_with_attrs(mr->opaque, addr, tmp, size, attrs); } =20 +typedef MemTxResult (*MemoryRegionAccessFn)(MemoryRegion *mr, + hwaddr addr, + uint64_t *value, + unsigned size, + signed shift, + uint64_t mask, + MemTxAttrs attrs); + +static MemTxResult access_emulation(hwaddr addr, + uint64_t *value, + unsigned int size, + unsigned int access_size_min, + unsigned int access_size_max, + MemoryRegion *mr, + MemTxAttrs attrs, + MemoryRegionAccessFn access_fn_read, + MemoryRegionAccessFn access_fn_write, + bool is_write) +{ + hwaddr a; + uint8_t *d; + uint64_t v; + MemTxResult r =3D MEMTX_OK; + bool is_big_endian =3D devend_big_endian(mr->ops->endianness); + void (*store)(void *, int, uint64_t) =3D is_big_endian ? stn_be_p : st= n_le_p; + uint64_t (*load)(const void *, int) =3D is_big_endian ? ldn_be_p : ldn= _le_p; + size_t access_size =3D MAX(MIN(size, access_size_max), access_size_min= ); + uint64_t access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); + hwaddr round_down =3D mr->ops->impl.unaligned && addr + size <=3D mr->= size ? + 0 : addr % access_size; + hwaddr start =3D addr - round_down; + hwaddr tail =3D addr + size <=3D mr->size ? addr + size : mr->size; + uint8_t data[16] =3D {0}; + g_assert(size <=3D 8); + + for (a =3D start, d =3D data, v =3D 0; a < tail; + a +=3D access_size, d +=3D access_size, v =3D 0) { + r |=3D access_fn_read(mr, a, &v, access_size, 0, access_mask, + attrs); + store(d, access_size, v); + } + if (is_write) { + stn_he_p(&data[round_down], size, load(value, size)); + for (a =3D start, d =3D data; a < tail; + a +=3D access_size, d +=3D access_size) { + v =3D load(d, access_size); + r |=3D access_fn_write(mr, a, &v, access_size, 0, access_mask, + attrs); + } + } else { + store(value, size, ldn_he_p(&data[round_down], size)); + } + + return r; +} + +static bool is_access_fastpath(hwaddr addr, + unsigned int size, + unsigned int access_size_min, + unsigned int access_size_max, + MemoryRegion *mr) +{ + size_t access_size =3D MAX(MIN(size, access_size_max), access_size_min= ); + hwaddr round_down =3D mr->ops->impl.unaligned && addr + size <=3D mr->= size ? + 0 : addr % access_size; + + return round_down =3D=3D 0 && access_size <=3D size; +} + +static MemTxResult access_fastpath(hwaddr addr, + uint64_t *value, + unsigned int size, + unsigned int access_size_min, + unsigned int access_size_max, + MemoryRegion *mr, + MemTxAttrs attrs, + MemoryRegionAccessFn fastpath) +{ + MemTxResult r =3D MEMTX_OK; + size_t access_size =3D MAX(MIN(size, access_size_max), access_size_min= ); + uint64_t access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); + + if (devend_big_endian(mr->ops->endianness)) { + for (size_t i =3D 0; i < size; i +=3D access_size) { + r |=3D fastpath(mr, addr + i, value, access_size, + (size - access_size - i) * 8, access_mask, attrs= ); + } + } else { + for (size_t i =3D 0; i < size; i +=3D access_size) { + r |=3D fastpath(mr, addr + i, value, access_size, + i * 8, access_mask, attrs); + } + } + + return r; +} + static MemTxResult access_with_adjusted_size(hwaddr addr, uint64_t *value, unsigned size, unsigned access_size_min, unsigned access_size_max, - MemTxResult (*access_fn) - (MemoryRegion *mr, - hwaddr addr, - uint64_t *value, - unsigned size, - signed shift, - uint64_t mask, - MemTxAttrs attrs), + MemoryRegionAccessFn access_fn_read, + MemoryRegionAccessFn access_fn_write, + bool is_write, MemoryRegion *mr, MemTxAttrs attrs) { - uint64_t access_mask; - unsigned access_size; - unsigned i; MemTxResult r =3D MEMTX_OK; bool reentrancy_guard_applied =3D false; + MemoryRegionAccessFn access_fn_fastpath =3D + is_write ? access_fn_write : access_fn_read; =20 if (!access_size_min) { access_size_min =3D 1; @@ -551,20 +642,16 @@ static MemTxResult access_with_adjusted_size(hwaddr a= ddr, reentrancy_guard_applied =3D true; } =20 - /* FIXME: support unaligned access? */ - access_size =3D MAX(MIN(size, access_size_max), access_size_min); - access_mask =3D MAKE_64BIT_MASK(0, access_size * 8); - if (devend_big_endian(mr->ops->endianness)) { - for (i =3D 0; i < size; i +=3D access_size) { - r |=3D access_fn(mr, addr + i, value, access_size, - (size - access_size - i) * 8, access_mask, attrs); - } + if (is_access_fastpath(addr, size, access_size_min, access_size_max, m= r)) { + r |=3D access_fastpath(addr, value, size, + access_size_min, access_size_max, mr, attrs, + access_fn_fastpath); } else { - for (i =3D 0; i < size; i +=3D access_size) { - r |=3D access_fn(mr, addr + i, value, access_size, i * 8, - access_mask, attrs); - } + r |=3D access_emulation(addr, value, size, + access_size_min, access_size_max, mr, attrs, + access_fn_read, access_fn_write, is_write); } + if (mr->dev && reentrancy_guard_applied) { mr->dev->mem_reentrancy_guard.engaged_in_io =3D false; } @@ -1450,13 +1537,15 @@ static MemTxResult memory_region_dispatch_read1(Mem= oryRegion *mr, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, memory_region_read_accessor, - mr, attrs); + memory_region_write_accessor, + false, mr, attrs); } else { return access_with_adjusted_size(addr, pval, size, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, memory_region_read_with_attrs_acc= essor, - mr, attrs); + memory_region_write_with_attrs_ac= cessor, + false, mr, attrs); } } =20 @@ -1544,15 +1633,17 @@ MemTxResult memory_region_dispatch_write(MemoryRegi= on *mr, return access_with_adjusted_size(addr, &data, size, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, - memory_region_write_accessor, mr, - attrs); + memory_region_read_accessor, + memory_region_write_accessor, + true, mr, attrs); } else { return access_with_adjusted_size(addr, &data, size, mr->ops->impl.min_access_size, mr->ops->impl.max_access_size, + memory_region_read_with_attrs_access= or, memory_region_write_with_attrs_acces= sor, - mr, attrs); + true, mr, attrs); } } =20 diff --git a/system/physmem.c b/system/physmem.c index a8a9ca309e..9c5f3fbef1 100644 --- a/system/physmem.c +++ b/system/physmem.c @@ -2864,14 +2864,6 @@ int memory_access_size(MemoryRegion *mr, unsigned l,= hwaddr addr) access_size_max =3D 4; } =20 - /* Bound the maximum access by the alignment of the address. */ - if (!mr->ops->impl.unaligned) { - unsigned align_size_max =3D addr & -addr; - if (align_size_max !=3D 0 && align_size_max < access_size_max) { - access_size_max =3D align_size_max; - } - } - /* Don't attempt accesses larger than the maximum. */ if (l > access_size_max) { l =3D access_size_max; --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755871058; cv=none; d=zohomail.com; s=zohoarc; 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In addition, the limit of access size is also unspecified. Actually, some real devices allow unaligned access and 8-byte access to these registers. This commit makes it possible to unaligned access and 8-byte access to Host Controller Capability Registers. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/143 Based-on-a-patch-by: Tomoyuki Hirose Signed-off-by: CJ Chen Tested-by: CJ Chen Reported-by: Tomoyuki Hirose --- hw/usb/hcd-xhci.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 292c378bfc..81e91e6ffb 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3190,9 +3190,11 @@ static const MemoryRegionOps xhci_cap_ops =3D { .read =3D xhci_cap_read, .write =3D xhci_cap_write, .valid.min_access_size =3D 1, - .valid.max_access_size =3D 4, + .valid.max_access_size =3D 8, + .valid.unaligned =3D true, .impl.min_access_size =3D 4, .impl.max_access_size =3D 4, + .impl.unaligned =3D false, .endianness =3D DEVICE_LITTLE_ENDIAN, }; =20 --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755870924; cv=none; d=zohomail.com; s=zohoarc; b=KDiZpHw+dtr8HznjZPoU39s44jqnDwLC/e8Ye3mn6szQKEVN3UqzHo43NmFH4SKkonmHkWgrrfi7Mfg+X72vqSNd3MsOpNPhhQmiJPAOgrjrhIef9+St96grjHtGxzZx3LwJx9RZP7tNbVLPVOulps9d7VxKsWPtb1eCfePziK4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755870924; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=vh5PW27wq4M7UAgJQHpY8LHqZa1HVp12yT5xQoyQ7OE=; b=RfXnBdDSwm6anqAWLWgdlr4T/VMRl5hpDHU2wblLs5LawXK0YsvG7ha2uw2xwMa+PL2ZP0wFeDXCIsTV28sAhOhIZ3gsvkrz0QZWSUm7p5RJXdLUBYuz1ChDZtO4+I0mYisNoQQiokn/8u3uRRJB2HrNhc4UFJmYvNdVAavpEnQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755870924674429.07937563810947; Fri, 22 Aug 2025 06:55:24 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upSDP-0005sv-Um; Fri, 22 Aug 2025 09:53:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upO1z-00063w-Oz for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:55 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1upO1u-0007HH-4F for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:55 -0400 Received: by mail-pg1-x52a.google.com with SMTP id 41be03b00d2f7-b47175d02dcso1480337a12.3 for ; Fri, 22 Aug 2025 02:25:48 -0700 (PDT) Received: from warg.hq.igel.co.jp (napt.igel.co.jp. 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The .valid structure indicates that unaligned access should be rejected at the access validation phase, yet .impl suggests the underlying device implementation can handle unaligned operations. As a result, the upper-layer code will never even reach the .impl logic, leading to confusion. Signed-off-by: CJ Chen Tested-by: CJ Chen Suggested-by: Peter Xu Acked-by: Tomoyuki Hirose Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- system/memory.c | 1 + 1 file changed, 1 insertion(+) diff --git a/system/memory.c b/system/memory.c index d6071b4414..b536a62ce9 100644 --- a/system/memory.c +++ b/system/memory.c @@ -1654,6 +1654,7 @@ void memory_region_init_io(MemoryRegion *mr, const char *name, uint64_t size) { + g_assert(!ops || !(ops->impl.unaligned && !ops->valid.unaligned)); memory_region_init(mr, owner, name, size); mr->ops =3D ops ? ops : &unassigned_mem_ops; mr->opaque =3D opaque; --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1755870937; cv=none; d=zohomail.com; s=zohoarc; b=ia0S6Obcgq+/MaDJFVDYSkeP+YG8O0Z8rFEaZVebMV47Vxx0iUoFegPBOJpzjb64ZSLa8ErJPNY9miuqjEb1Ocpe3bhoM1cuMhZ4IOaoe9koyWNOhIxcx4oaEtXm2gJ1qRoCgtjN2XBnv+W6UQVx3302DeTltDthlpPcP8APzqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755870937; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=4n1o/3nULdO/4vcLp6ocaeLLrGhDDgu+DIftv97o3kU=; b=oKTgKkpwgyulDNDjQ6nLaj3iNdbbfyJ49k4h2EMfoxOAp/0YhyYUZmk1DSK7rci+yGJxBCX397zVqZPAOldU3xkqW/41+eFLY6wpwzcjKe8uxDrfYcR67AmvLaPmxBtDw/NYBlXN48ctXsoF5Bmj42VDAdCEJT73bGWz61sZiFw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755870937863549.6732012733208; Fri, 22 Aug 2025 06:55:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upSDc-00065o-KL; Fri, 22 Aug 2025 09:54:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upO23-00066J-S4 for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:59 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1upO1z-0007JN-MJ for qemu-devel@nongnu.org; Fri, 22 Aug 2025 05:25:59 -0400 Received: by mail-pl1-x634.google.com with SMTP id d9443c01a7336-24646202152so3533735ad.0 for ; Fri, 22 Aug 2025 02:25:55 -0700 (PDT) Received: from warg.hq.igel.co.jp (napt.igel.co.jp. [219.106.231.132]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-245ed4c6fb7sm78560215ad.89.2025.08.22.02.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Aug 2025 02:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=igel-co-jp.20230601.gappssmtp.com; s=20230601; t=1755854753; x=1756459553; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=4n1o/3nULdO/4vcLp6ocaeLLrGhDDgu+DIftv97o3kU=; b=upys3JB4yKZU3ArIe++mskr14PrqnT5rPWeR6EO7s0Yqg/IlgGAjC7LaU8tAe5h+X/ 9p8bTY5elv5QATxT1TEYGRO370kAJCog70hSNKG+HLOu8+3hPFhqpIskttRA7QH8eBMh dW+WhDxFDAIDgsQKqF+XhTzCkPvUAfeS14dvfxIy+nGSs4pqO9975J08lNov7JeB9Zt+ eXGTuwh76JzjrDmt4nEIMc+324+L2IhhluBC7JI/cBZTdzL9qGf0InhM6RXdo1PjTtgw z9KdYK2g/8KujQjEdiluiui7EAiAAdO5wmo9lBik28wCjvj50/lczhKJ28bk3emkar8F 7DrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755854753; x=1756459553; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=4n1o/3nULdO/4vcLp6ocaeLLrGhDDgu+DIftv97o3kU=; b=SbYZL3F0hqR1azOhSVmvmoIQSkDuGR8sXtkk/j1rqvg2ppA8OHul+L68x/p6qGRy3R uXPQOfbfumcs+tNGvaMXD0/b9sv74K9w5rZpODpU6O+MqkHs3fii5igDnBKx9NWrR27y ZGHgPB0esdh2sWgyIw9XVjf1DTqKgU2D+qGqgZ4ugsaPbp/JKtPVBLKZxRTDK4N84/L6 xWta6wxl8kmDbnG7auhtjxPeGbwUi0Ae0uTSET9t+fYCe4z7yWAyjmVYYMKNSAHh/qvJ bQmaklSDDa2NJNx7VewlDH2UtdE7h5JOgZLW3wCEjjRfBw94tLa7tAPAvHRnCAJtUpUk vZOQ== X-Gm-Message-State: AOJu0YxybqLH+PDnt8HbAJ33JrgkMa9iDuUCFfGk18RHa35i0jbyLRJA 2+IM8J+ysZUKCRxI/USXNnNV0KRG0N2CX68qhYRblwXkwk7VlHuMHtF5y/zMxPRvb/Ii8xZOgUv Poke7yLY= X-Gm-Gg: ASbGnct72km+zsBuLk9ubFxpiZA/R0XkL9wO7WHGJiXk9WvAiXRAzQj1JhF/7PyDJ7n 8PqDdrmzj3ARomn5tdx2+j5v5Wu2JeZEdR0bJE5nuFlFTFETsWoCS8mCd2+0L11rg6QZ9cZtH4K COutpLvObVGvBiJL3mebbQ2gAaXXL4cXQfBOmwPXqC6MKpM+A5uiKPYgwwuXfxrs4WqUf1oGkSN SfSh9hs/vNe83boeycmIK4wtNWpdGAawJTy4MS8eIvxdmj33/ZMcySHhYWwk/v2d0PDPmJf2l2c ZizHDBx8C2tJcGuD6furhDJb6Eogq5asV+aSFRrykTGz3qWqFrW1NzSwpKKg3bvQ7EP/KGuimyU UZNjmuaAVG6/+8jR6lPX6hkA0Ly1vAl4FKFyM+OOfRH20EKHfsdmw X-Google-Smtp-Source: AGHT+IEnJxA4ELufqmF+83vXLTGSupOh5K2TH6ao0bmRfoYOFqouqA0TtrEayssE+w//NktDX9P0JA== X-Received: by 2002:a17:902:ebc5:b0:246:255a:1915 with SMTP id d9443c01a7336-2462eea840emr32074745ad.27.1755854753093; Fri, 22 Aug 2025 02:25:53 -0700 (PDT) From: CJ Chen To: qemu-devel@nongnu.org, qemu-block@nongnu.org, qemu-riscv@nongnu.org, qemu-arm@nongnu.org Cc: Paolo Bonzini , Keith Busch , Klaus Jensen , Jesper Devantier , Palmer Dabbelt , Alistair Francis , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , Tyrone Ting , Hao Wu , Max Filippov , Peter Xu , David Hildenbrand , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Fabiano Rosas , Laurent Vivier , Tomoyuki Hirose , Peter Maydell , CJ Chen Subject: [RFC PATCH v2 8/9] hw/misc: add test device for memory access Date: Fri, 22 Aug 2025 18:24:09 +0900 Message-Id: <20250822092410.25833-9-cjchen@igel.co.jp> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250822092410.25833-1-cjchen@igel.co.jp> References: <20250822092410.25833-1-cjchen@igel.co.jp> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=cjchen@igel.co.jp; helo=mail-pl1-x634.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Fri, 22 Aug 2025 09:53:59 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @igel-co-jp.20230601.gappssmtp.com) X-ZM-MESSAGEID: 1755870941425124100 Content-Type: text/plain; charset="utf-8" From: Tomoyuki Hirose This commit adds a test device for checking memory access. The test device generates memory regions that covers all the legal parameter patterns. With this device, we can check the handling of reading/writing the MemoryRegion is correct. Co-developed-by: CJ Chen Signed-off-by: CJ Chen Tested-by: CJ Chen Suggested-by: Peter Maydell --- v2: - Fix the typo of ops size of big-l-valid. - Replaced the huge macro blocks with dynamic loops that fill in the `MemoryRegionOps` arrays at runtime. - Remove test cases valid.unaligned =3D false,impl.unaligned =3D true. --- hw/misc/Kconfig | 4 + hw/misc/memaccess-testdev.c | 331 ++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + include/hw/misc/memaccess-testdev.h | 104 +++++++++ 4 files changed, 440 insertions(+) create mode 100644 hw/misc/memaccess-testdev.c create mode 100644 include/hw/misc/memaccess-testdev.h diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig index ec0fa5aa9f..ff7d7c65ef 100644 --- a/hw/misc/Kconfig +++ b/hw/misc/Kconfig @@ -25,6 +25,10 @@ config PCI_TESTDEV default y if TEST_DEVICES depends on PCI =20 +config MEMACCESS_TESTDEV + bool + default y if TEST_DEVICES + config EDU bool default y if TEST_DEVICES diff --git a/hw/misc/memaccess-testdev.c b/hw/misc/memaccess-testdev.c new file mode 100644 index 0000000000..1aaa52c69f --- /dev/null +++ b/hw/misc/memaccess-testdev.c @@ -0,0 +1,331 @@ +/* + * QEMU memory access test device + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Author: Tomoyuki HIROSE + * + * This device is used to test memory acccess, like: + * qemu-system-x86_64 -device memaccess-testdev,address=3D0x10000000 + */ + +#include "qemu/osdep.h" +#include "system/address-spaces.h" +#include "system/memory.h" +#include "hw/qdev-core.h" +#include "hw/qdev-properties.h" +#include "qapi/error.h" +#include "qemu/typedefs.h" +#include "qom/object.h" +#include "hw/misc/memaccess-testdev.h" + +typedef bool (*skip_func_ptr)(uint32_t valid_max, uint32_t valid_min, + bool valid_unaligned, uint32_t impl_max, + uint32_t impl_min, bool impl_unaligned); + +typedef struct MrOpsList { + const char *name; + MemoryRegionOps *ops_array; + const size_t ops_array_len; + const size_t offset_idx; + skip_func_ptr skip_fn; + bool is_little; +} MrOpsList; + +MemoryRegionOps ops_list_little_b_valid[N_OPS_LIST_LITTLE_B_VALID]; +MemoryRegionOps ops_list_little_b_invalid[N_OPS_LIST_LITTLE_B_INVALID]; +MemoryRegionOps ops_list_little_w_valid[N_OPS_LIST_LITTLE_W_VALID]; +MemoryRegionOps ops_list_little_w_invalid[N_OPS_LIST_LITTLE_W_INVALID]; +MemoryRegionOps ops_list_little_l_valid[N_OPS_LIST_LITTLE_L_VALID]; +MemoryRegionOps ops_list_little_l_invalid[N_OPS_LIST_LITTLE_L_INVALID]; +MemoryRegionOps ops_list_little_q_valid[N_OPS_LIST_LITTLE_Q_VALID]; +MemoryRegionOps ops_list_little_q_invalid[N_OPS_LIST_LITTLE_Q_INVALID]; +MemoryRegionOps ops_list_big_b_valid[N_OPS_LIST_BIG_B_VALID]; +MemoryRegionOps ops_list_big_b_invalid[N_OPS_LIST_BIG_B_INVALID]; +MemoryRegionOps ops_list_big_w_valid[N_OPS_LIST_BIG_W_VALID]; +MemoryRegionOps ops_list_big_w_invalid[N_OPS_LIST_BIG_W_INVALID]; +MemoryRegionOps ops_list_big_l_valid[N_OPS_LIST_BIG_L_VALID]; +MemoryRegionOps ops_list_big_l_invalid[N_OPS_LIST_BIG_L_INVALID]; +MemoryRegionOps ops_list_big_q_valid[N_OPS_LIST_BIG_Q_VALID]; +MemoryRegionOps ops_list_big_q_invalid[N_OPS_LIST_BIG_Q_INVALID]; + +static bool skip_core(uint32_t required_min, bool valid_test, + uint32_t valid_max, uint32_t valid_min, + bool valid_unaligned, uint32_t impl_max, + uint32_t impl_min, bool impl_unaligned) +{ + if (valid_min !=3D required_min) { + return true; + } + if (valid_test) { + if (!valid_unaligned) { + return true; + } + } else { + if (valid_unaligned || impl_unaligned) { + return true; + } + } + if (valid_max < valid_min) { + return true; + } + + if (impl_max < impl_min) { + return true; + } + + return false; +} + +#define DEFINE_SKIP_VALID_INVALID_FN(NAME, REQ_MIN) \ + static bool skip_##NAME##_valid(uint32_t vm, uint32_t vn, bool vu, \ + uint32_t im, uint32_t in, bool iu) \ + { \ + return skip_core(REQ_MIN, true, vm, vn, vu, im, in, iu); \ + } \ + \ + static bool skip_##NAME##_invalid(uint32_t vm, uint32_t vn, bool vu, \ + uint32_t im, uint32_t in, bool iu) \ + { \ + return skip_core(REQ_MIN, false, vm, vn, vu, im, in, iu); \ + } + +DEFINE_SKIP_VALID_INVALID_FN(b, 1) +DEFINE_SKIP_VALID_INVALID_FN(w, 2) +DEFINE_SKIP_VALID_INVALID_FN(l, 4) +DEFINE_SKIP_VALID_INVALID_FN(q, 8) + +static void testdev_init_memory_region(MemoryRegion *mr, + Object *owner, + const MemoryRegionOps *ops, + void *opaque, + const char *name, + uint64_t size, + MemoryRegion *container, + hwaddr container_offset) +{ + memory_region_init_io(mr, owner, ops, opaque, name, size); + memory_region_add_subregion(container, container_offset, mr); +} + +static void testdev_init_from_mr_ops_list(MemAccessTestDev *testdev, + const MrOpsList *l) +{ + for (size_t i =3D 0; i < l->ops_array_len; i++) { + g_autofree gchar *name =3D g_strdup_printf("%s-%ld", l->name, i); + testdev_init_memory_region(&testdev->memory_regions[l->offset_idx = + i], + OBJECT(testdev), &l->ops_array[i], + testdev->mr_data[l->offset_idx + i], + name, + MEMACCESS_TESTDEV_REGION_SIZE, + &testdev->container, + MEMACCESS_TESTDEV_REGION_SIZE * + (l->offset_idx + i)); + } +} + +#define LITTLE 1 +#define BIG 0 +#define _DEFINE_MR_OPS_LIST(_n, _ops, _len, _off, _skipfn, _is_little) \ +{ \ + .name =3D (_n), \ + .ops_array =3D (_ops), \ + .ops_array_len =3D (_len), \ + .offset_idx =3D (_off), \ + .skip_fn =3D (_skipfn), \ + .is_little =3D (_is_little), \ +} + +#define DEFINE_MR_OPS_LIST(e, E, w, W, v, V) \ + _DEFINE_MR_OPS_LIST( \ + #e "-" #w "-" #v, /* .name */ \ + ops_list_##e##_##w##_##v, /* .ops_array */ \ + N_OPS_LIST_##E##_##W##_##V, /* .ops_array_len */ \ + OFF_IDX_OPS_LIST_##E##_##W##_##V,/* .offset_idx */ \ + skip_##w##_##v, /* .skip_fn */ \ + E /* .is_little =3D> 1 =3D little endian, 0 =3D big endian */ \ + ) + +static MrOpsList mr_ops_list[] =3D { + DEFINE_MR_OPS_LIST(little, LITTLE, b, B, valid, VALID), + DEFINE_MR_OPS_LIST(little, LITTLE, b, B, invalid, INVALID), + DEFINE_MR_OPS_LIST(little, LITTLE, w, W, valid, VALID), + DEFINE_MR_OPS_LIST(little, LITTLE, w, W, invalid, INVALID), + DEFINE_MR_OPS_LIST(little, LITTLE, l, L, valid, VALID), + DEFINE_MR_OPS_LIST(little, LITTLE, l, L, invalid, INVALID), + DEFINE_MR_OPS_LIST(little, LITTLE, q, Q, valid, VALID), + DEFINE_MR_OPS_LIST(little, LITTLE, q, Q, invalid, INVALID), + DEFINE_MR_OPS_LIST(big, BIG, b, B, valid, VALID), + DEFINE_MR_OPS_LIST(big, BIG, b, B, invalid, INVALID), + DEFINE_MR_OPS_LIST(big, BIG, w, W, valid, VALID), + DEFINE_MR_OPS_LIST(big, BIG, w, W, invalid, INVALID), + DEFINE_MR_OPS_LIST(big, BIG, l, L, valid, VALID), + DEFINE_MR_OPS_LIST(big, BIG, l, L, invalid, INVALID), + DEFINE_MR_OPS_LIST(big, BIG, q, Q, valid, VALID), + DEFINE_MR_OPS_LIST(big, BIG, q, Q, invalid, INVALID), +}; +#undef LITTLE +#undef BIG + +static uint64_t memaccess_testdev_read_little(void *opaque, hwaddr addr, + unsigned int size) +{ + g_assert(addr + size < MEMACCESS_TESTDEV_REGION_SIZE); + void *s =3D (uint8_t *)opaque + addr; + return ldn_le_p(s, size); +} + +static void memaccess_testdev_write_little(void *opaque, hwaddr addr, + uint64_t data, unsigned int siz= e) +{ + g_assert(addr + size < MEMACCESS_TESTDEV_REGION_SIZE); + void *d =3D (uint8_t *)opaque + addr; + stn_le_p(d, size, data); +} + +static uint64_t memaccess_testdev_read_big(void *opaque, hwaddr addr, + unsigned int size) +{ + g_assert(addr + size < MEMACCESS_TESTDEV_REGION_SIZE); + void *s =3D (uint8_t *)opaque + addr; + return ldn_be_p(s, size); +} + +static void memaccess_testdev_write_big(void *opaque, hwaddr addr, + uint64_t data, unsigned int size) +{ + g_assert(addr + size < MEMACCESS_TESTDEV_REGION_SIZE); + void *d =3D (uint8_t *)opaque + addr; + stn_be_p(d, size, data); +} + +static void fill_ops_list(MemoryRegionOps *ops, + skip_func_ptr fptr, + size_t ops_len, + bool is_little) +{ + static const uint32_t sizes[] =3D { 1, 2, 4, 8 }; + static const bool bools[] =3D { false, true }; + int idx =3D 0; + + for (int vMaxIdx =3D 0; vMaxIdx < 4; vMaxIdx++) { + for (int vMinIdx =3D 0; vMinIdx < 4; vMinIdx++) { + for (int vUIdx =3D 0; vUIdx < 2; vUIdx++) { + for (int iMaxIdx =3D 0; iMaxIdx < 4; iMaxIdx++) { + for (int iMinIdx =3D 0; iMinIdx < 4; iMinIdx++) { + for (int iUIdx =3D 0; iUIdx < 2; iUIdx++) { + uint32_t valid_max =3D sizes[vMaxIdx]; + uint32_t valid_min =3D sizes[vMinIdx]; + bool valid_unaligned =3D bools[vUIdx]; + uint32_t impl_max =3D sizes[iMaxIdx]; + uint32_t impl_min =3D sizes[iMinIdx]; + bool impl_unaligned =3D bools[iUIdx]; + + if (!fptr(valid_max, valid_min, valid_unaligne= d, + impl_max, impl_min, impl_unaligned)) + { + const MemoryRegionOps new_op =3D { + .read =3D is_little ? + memaccess_testdev_read_little : + memaccess_testdev_read_big, + .write =3D is_little ? + memaccess_testdev_write_littl= e : + memaccess_testdev_write_big, + .endianness =3D is_little ? + DEVICE_LITTLE_ENDIAN : + DEVICE_BIG_ENDIAN, + .valid =3D { + .max_access_size =3D valid_max, + .min_access_size =3D valid_min, + .unaligned =3D valid_unaligne= d, + }, + .impl =3D { + .max_access_size =3D impl_max, + .min_access_size =3D impl_min, + .unaligned =3D impl_unaligne= d, + }, + }; + + ops[idx] =3D new_op; + idx++; + if (idx > ops_len) { + g_assert_not_reached(); + } + } + } + } + } + } + } + } +} + +#define N_MR_OPS_LIST (sizeof(mr_ops_list) / sizeof(MrOpsList)) + +static void init_testdev(MemAccessTestDev *testdev) +{ + memory_region_init(&testdev->container, OBJECT(testdev), "memtest-regi= ons", + MEMACCESS_TESTDEV_REGION_SIZE * N_OPS_LIST); + testdev->mr_data =3D g_malloc(MEMACCESS_TESTDEV_MR_DATA_SIZE); + + for (size_t i =3D 0; i < N_MR_OPS_LIST; i++) { + fill_ops_list( + mr_ops_list[i].ops_array, + mr_ops_list[i].skip_fn, + mr_ops_list[i].ops_array_len, + mr_ops_list[i].is_little + ); + testdev_init_from_mr_ops_list(testdev, &mr_ops_list[i]); + } + + memory_region_add_subregion(get_system_memory(), testdev->base, + &testdev->container); +} + +static void memaccess_testdev_realize(DeviceState *dev, Error **errp) +{ + MemAccessTestDev *d =3D MEM_ACCESS_TEST_DEV(dev); + + if (d->base =3D=3D UINT64_MAX) { + error_setg(errp, "base address is not assigned"); + return; + } + + init_testdev(d); +} + +static void memaccess_testdev_unrealize(DeviceState *dev) +{ + MemAccessTestDev *d =3D MEM_ACCESS_TEST_DEV(dev); + g_free(d->mr_data); +} + +static Property memaccess_testdev_props[] =3D { + DEFINE_PROP_UINT64("address", MemAccessTestDev, base, UINT64_MAX), +}; + +static void memaccess_testdev_class_init(ObjectClass *klass, const void *d= ata) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D memaccess_testdev_realize; + dc->unrealize =3D memaccess_testdev_unrealize; + device_class_set_props_n(dc, + memaccess_testdev_props, + ARRAY_SIZE(memaccess_testdev_props)); + set_bit(DEVICE_CATEGORY_MISC, dc->categories); +} + +static const TypeInfo memaccess_testdev_info =3D { + .name =3D TYPE_MEM_ACCESS_TEST_DEV, + .parent =3D TYPE_DEVICE, + .instance_size =3D sizeof(MemAccessTestDev), + .class_init =3D memaccess_testdev_class_init, +}; + +static void memaccess_testdev_register_types(void) +{ + type_register_static(&memaccess_testdev_info); +} + +type_init(memaccess_testdev_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6d47de482c..f06568aaed 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -4,6 +4,7 @@ system_ss.add(when: 'CONFIG_FW_CFG_DMA', if_true: files('vm= coreinfo.c')) system_ss.add(when: 'CONFIG_ISA_DEBUG', if_true: files('debugexit.c')) system_ss.add(when: 'CONFIG_ISA_TESTDEV', if_true: files('pc-testdev.c')) system_ss.add(when: 'CONFIG_PCI_TESTDEV', if_true: files('pci-testdev.c')) +system_ss.add(when: 'CONFIG_MEMACCESS_TESTDEV', if_true: files('memaccess-= testdev.c')) system_ss.add(when: 'CONFIG_UNIMP', if_true: files('unimp.c')) system_ss.add(when: 'CONFIG_EMPTY_SLOT', if_true: files('empty_slot.c')) system_ss.add(when: 'CONFIG_LED', if_true: files('led.c')) diff --git a/include/hw/misc/memaccess-testdev.h b/include/hw/misc/memacces= s-testdev.h new file mode 100644 index 0000000000..c1b17297a2 --- /dev/null +++ b/include/hw/misc/memaccess-testdev.h @@ -0,0 +1,104 @@ +/* + * QEMU memory access test device header + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Author: Tomoyuki HIROSE + */ + +#ifndef HW_MISC_MEMACCESS_TESTDEV_H +#define HW_MISC_MEMACCESS_TESTDEV_H + +#include "system/memory.h" +#include "hw/qdev-core.h" + +#define TYPE_MEM_ACCESS_TEST_DEV "memaccess-testdev" + +#define MEMACCESS_TESTDEV_REGION_SIZE 32 + +#define N_OPS_LIST_LITTLE_B_VALID 80 +#define N_OPS_LIST_LITTLE_B_INVALID 40 +#define N_OPS_LIST_LITTLE_W_VALID 60 +#define N_OPS_LIST_LITTLE_W_INVALID 30 +#define N_OPS_LIST_LITTLE_L_VALID 40 +#define N_OPS_LIST_LITTLE_L_INVALID 20 +#define N_OPS_LIST_LITTLE_Q_VALID 20 +#define N_OPS_LIST_LITTLE_Q_INVALID 10 +#define N_OPS_LIST_BIG_B_VALID 80 +#define N_OPS_LIST_BIG_B_INVALID 40 +#define N_OPS_LIST_BIG_W_VALID 60 +#define N_OPS_LIST_BIG_W_INVALID 30 +#define N_OPS_LIST_BIG_L_VALID 40 +#define N_OPS_LIST_BIG_L_INVALID 20 +#define N_OPS_LIST_BIG_Q_VALID 20 +#define N_OPS_LIST_BIG_Q_INVALID 10 + +#define N_OPS_LIST \ + (N_OPS_LIST_LITTLE_B_VALID + \ + N_OPS_LIST_LITTLE_B_INVALID + \ + N_OPS_LIST_LITTLE_W_VALID + \ + N_OPS_LIST_LITTLE_W_INVALID + \ + N_OPS_LIST_LITTLE_L_VALID + \ + N_OPS_LIST_LITTLE_L_INVALID + \ + N_OPS_LIST_LITTLE_Q_VALID + \ + N_OPS_LIST_LITTLE_Q_INVALID + \ + N_OPS_LIST_BIG_B_VALID + \ + N_OPS_LIST_BIG_B_INVALID + \ + N_OPS_LIST_BIG_W_VALID + \ + N_OPS_LIST_BIG_W_INVALID + \ + N_OPS_LIST_BIG_L_VALID + \ + N_OPS_LIST_BIG_L_INVALID + \ + N_OPS_LIST_BIG_Q_VALID + \ + N_OPS_LIST_BIG_Q_INVALID) + +#define OFF_IDX_OPS_LIST_LITTLE_B_VALID \ + (0) +#define OFF_IDX_OPS_LIST_LITTLE_B_INVALID \ + (OFF_IDX_OPS_LIST_LITTLE_B_VALID + N_OPS_LIST_LITTLE_B_VALID) +#define OFF_IDX_OPS_LIST_LITTLE_W_VALID \ + (OFF_IDX_OPS_LIST_LITTLE_B_INVALID + N_OPS_LIST_LITTLE_B_INVALID) +#define OFF_IDX_OPS_LIST_LITTLE_W_INVALID \ + (OFF_IDX_OPS_LIST_LITTLE_W_VALID + N_OPS_LIST_LITTLE_W_VALID) +#define OFF_IDX_OPS_LIST_LITTLE_L_VALID \ + (OFF_IDX_OPS_LIST_LITTLE_W_INVALID + N_OPS_LIST_LITTLE_W_INVALID) +#define OFF_IDX_OPS_LIST_LITTLE_L_INVALID \ + (OFF_IDX_OPS_LIST_LITTLE_L_VALID + N_OPS_LIST_LITTLE_L_VALID) +#define OFF_IDX_OPS_LIST_LITTLE_Q_VALID \ + (OFF_IDX_OPS_LIST_LITTLE_L_INVALID + N_OPS_LIST_LITTLE_L_INVALID) +#define OFF_IDX_OPS_LIST_LITTLE_Q_INVALID \ + (OFF_IDX_OPS_LIST_LITTLE_Q_VALID + N_OPS_LIST_LITTLE_Q_VALID) +#define OFF_IDX_OPS_LIST_BIG_B_VALID \ + (OFF_IDX_OPS_LIST_LITTLE_Q_INVALID + N_OPS_LIST_LITTLE_Q_INVALID) +#define OFF_IDX_OPS_LIST_BIG_B_INVALID \ + (OFF_IDX_OPS_LIST_BIG_B_VALID + N_OPS_LIST_BIG_B_VALID) +#define OFF_IDX_OPS_LIST_BIG_W_VALID \ + (OFF_IDX_OPS_LIST_BIG_B_INVALID + N_OPS_LIST_BIG_B_INVALID) +#define OFF_IDX_OPS_LIST_BIG_W_INVALID \ + (OFF_IDX_OPS_LIST_BIG_W_VALID + N_OPS_LIST_BIG_W_VALID) +#define OFF_IDX_OPS_LIST_BIG_L_VALID \ + (OFF_IDX_OPS_LIST_BIG_W_INVALID + N_OPS_LIST_BIG_W_INVALID) +#define OFF_IDX_OPS_LIST_BIG_L_INVALID \ + (OFF_IDX_OPS_LIST_BIG_L_VALID + N_OPS_LIST_BIG_L_VALID) +#define OFF_IDX_OPS_LIST_BIG_Q_VALID \ + (OFF_IDX_OPS_LIST_BIG_L_INVALID + N_OPS_LIST_BIG_L_INVALID) +#define OFF_IDX_OPS_LIST_BIG_Q_INVALID \ + (OFF_IDX_OPS_LIST_BIG_Q_VALID + N_OPS_LIST_BIG_Q_VALID) + +typedef uint8_t MrData[MEMACCESS_TESTDEV_REGION_SIZE]; +#define MEMACCESS_TESTDEV_MR_DATA_SIZE (sizeof(MrData) * N_OPS_LIST) + +typedef DeviceClass MemAccessTestDevClass; +typedef struct MemAccessTestDev { + /* Private */ + DeviceState parent_obj; + /* Public */ + MemoryRegion container; + MemoryRegion memory_regions[N_OPS_LIST]; /* test memory regions */ + uint64_t base; /* map base address */ + MrData *mr_data; /* memory region data array */ +} MemAccessTestDev; + +#define MEM_ACCESS_TEST_DEV(obj) \ + OBJECT_CHECK(MemAccessTestDev, obj, TYPE_MEM_ACCESS_TEST_DEV) + +#endif --=20 2.25.1 From nobody Sat Nov 15 03:13:55 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 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The qtest checks the correctness of handling the access to memory regions by using 'memaccess-testdev'. Signed-off-by: CJ Chen Co-developed-by: CJ Chen Reported-by: Tomoyuki Hirose --- tests/qtest/memaccess-test.c | 597 +++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 9 + 2 files changed, 606 insertions(+) create mode 100644 tests/qtest/memaccess-test.c diff --git a/tests/qtest/memaccess-test.c b/tests/qtest/memaccess-test.c new file mode 100644 index 0000000000..7e90028ea0 --- /dev/null +++ b/tests/qtest/memaccess-test.c @@ -0,0 +1,597 @@ +/* + * QEMU memory region access test + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Author: Tomoyuki HIROSE + */ + +#include "qemu/osdep.h" +#include "libqtest.h" + +#include "hw/misc/memaccess-testdev.h" + +static const char *arch =3D ""; +static const hwaddr base =3D 0x200000000; + +struct arch2cpu { + const char *arch; + const char *cpu_model; +}; + +static struct arch2cpu cpus_map[] =3D { + /* tested targets list */ + { "arm", "cortex-a15" }, + { "aarch64", "cortex-a57" }, + { "avr", "avr6-avr-cpu" }, + { "x86_64", "qemu64,apic-id=3D0" }, + { "i386", "qemu32,apic-id=3D0" }, + { "alpha", "ev67" }, + { "cris", "crisv32" }, + { "m68k", "m5206" }, + { "microblaze", "any" }, + { "microblazeel", "any" }, + { "mips", "4Kc" }, + { "mipsel", "I7200" }, + { "mips64", "20Kc" }, + { "mips64el", "I6500" }, + { "or1k", "or1200" }, + { "ppc", "604" }, + { "ppc64", "power8e_v2.1" }, + { "s390x", "qemu" }, + { "sh4", "sh7750r" }, + { "sh4eb", "sh7751r" }, + { "sparc", "LEON2" }, + { "sparc64", "Fujitsu Sparc64" }, + { "tricore", "tc1796" }, + { "xtensa", "dc233c" }, + { "xtensaeb", "fsf" }, + { "hppa", "hppa" }, + { "riscv64", "rv64" }, + { "riscv32", "rv32" }, + { "rx", "rx62n" }, + { "loongarch64", "la464" }, +}; + +static const char *get_cpu_model_by_arch(const char *arch) +{ + for (int i =3D 0; i < ARRAY_SIZE(cpus_map); i++) { + if (!strcmp(arch, cpus_map[i].arch)) { + return cpus_map[i].cpu_model; + } + } + return NULL; +} + +static QTestState *create_memaccess_qtest(void) +{ + QTestState *qts; + + qts =3D qtest_initf("-machine none -cpu \"%s\" " + "-device memaccess-testdev,address=3D0x%" PRIx64, + get_cpu_model_by_arch(arch), base); + return qts; +} + +static void little_b_valid(QTestState *qts, uint64_t offset) +{ + qtest_writeb(qts, base + offset + 0, 0x00); + qtest_writeb(qts, base + offset + 1, 0x11); + qtest_writeb(qts, base + offset + 2, 0x22); + qtest_writeb(qts, base + offset + 3, 0x33); + qtest_writeb(qts, base + offset + 4, 0x44); + qtest_writeb(qts, base + offset + 5, 0x55); + qtest_writeb(qts, base + offset + 6, 0x66); + qtest_writeb(qts, base + offset + 7, 0x77); + g_assert_cmphex(qtest_readb(qts, base + offset + 0), =3D=3D, 0x00); + g_assert_cmphex(qtest_readb(qts, base + offset + 1), =3D=3D, 0x11); + g_assert_cmphex(qtest_readb(qts, base + offset + 2), =3D=3D, 0x22); + g_assert_cmphex(qtest_readb(qts, base + offset + 3), =3D=3D, 0x33); + g_assert_cmphex(qtest_readb(qts, base + offset + 4), =3D=3D, 0x44); + g_assert_cmphex(qtest_readb(qts, base + offset + 5), =3D=3D, 0x55); + g_assert_cmphex(qtest_readb(qts, base + offset + 6), =3D=3D, 0x66); + g_assert_cmphex(qtest_readb(qts, base + offset + 7), =3D=3D, 0x77); +} + +static void little_b_invalid(QTestState *qts, uint64_t offset) +{ + qtest_writeb(qts, base + offset + 0, 0x00); + qtest_writeb(qts, base + offset + 1, 0x11); + qtest_writeb(qts, base + offset + 2, 0x22); + qtest_writeb(qts, base + offset + 3, 0x33); + qtest_writeb(qts, base + offset + 4, 0x44); + qtest_writeb(qts, base + offset + 5, 0x55); + qtest_writeb(qts, base + offset + 6, 0x66); + qtest_writeb(qts, base + offset + 7, 0x77); + g_assert_cmphex(qtest_readb(qts, base + offset + 0), =3D=3D, 0x00); + g_assert_cmphex(qtest_readb(qts, base + offset + 1), =3D=3D, 0x11); + g_assert_cmphex(qtest_readb(qts, base + offset + 2), =3D=3D, 0x22); + g_assert_cmphex(qtest_readb(qts, base + offset + 3), =3D=3D, 0x33); + g_assert_cmphex(qtest_readb(qts, base + offset + 4), =3D=3D, 0x44); + g_assert_cmphex(qtest_readb(qts, base + offset + 5), =3D=3D, 0x55); + g_assert_cmphex(qtest_readb(qts, base + offset + 6), =3D=3D, 0x66); + g_assert_cmphex(qtest_readb(qts, base + offset + 7), =3D=3D, 0x77); +} + +static void little_w_valid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 1, 0x3322); + qtest_writew(qts, base + offset + 2, 0x5544); + qtest_writew(qts, base + offset + 3, 0x7766); + qtest_writew(qts, base + offset + 4, 0x9988); + qtest_writew(qts, base + offset + 5, 0xbbaa); + qtest_writew(qts, base + offset + 6, 0xddcc); + qtest_writew(qts, base + offset + 7, 0xffee); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x113= 3); + g_assert_cmphex(qtest_readw(qts, base + offset + 1), =3D=3D, 0x335= 5); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x557= 7); + g_assert_cmphex(qtest_readw(qts, base + offset + 3), =3D=3D, 0x779= 9); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0x99b= b); + g_assert_cmphex(qtest_readw(qts, base + offset + 5), =3D=3D, 0xbbd= d); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0xddf= f); + g_assert_cmphex(qtest_readw(qts, base + offset + 7), =3D=3D, 0xffe= e); + } else { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 1, 0x3322); + qtest_writew(qts, base + offset + 2, 0x5544); + qtest_writew(qts, base + offset + 3, 0x7766); + qtest_writew(qts, base + offset + 4, 0x9988); + qtest_writew(qts, base + offset + 5, 0xbbaa); + qtest_writew(qts, base + offset + 6, 0xddcc); + qtest_writew(qts, base + offset + 7, 0xffee); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x220= 0); + g_assert_cmphex(qtest_readw(qts, base + offset + 1), =3D=3D, 0x442= 2); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x664= 4); + g_assert_cmphex(qtest_readw(qts, base + offset + 3), =3D=3D, 0x886= 6); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0xaa8= 8); + g_assert_cmphex(qtest_readw(qts, base + offset + 5), =3D=3D, 0xcca= a); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0xeec= c); + g_assert_cmphex(qtest_readw(qts, base + offset + 7), =3D=3D, 0xffe= e); + } +} + +static void little_w_invalid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 2, 0x3322); + qtest_writew(qts, base + offset + 4, 0x5544); + qtest_writew(qts, base + offset + 6, 0x7766); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x110= 0); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x332= 2); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0x554= 4); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0x776= 6); + } else { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 2, 0x3322); + qtest_writew(qts, base + offset + 4, 0x5544); + qtest_writew(qts, base + offset + 6, 0x7766); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x110= 0); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x332= 2); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0x554= 4); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0x776= 6); + } +} + +static void little_l_valid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 1, 0x77665544); + qtest_writel(qts, base + offset + 2, 0xbbaa9988); + qtest_writel(qts, base + offset + 3, 0xffeeddcc); + qtest_writel(qts, base + offset + 4, 0x01234567); + qtest_writel(qts, base + offset + 5, 0x89abcdef); + qtest_writel(qts, base + offset + 6, 0xfedcba98); + qtest_writel(qts, base + offset + 7, 0x76543210); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0x337= 7bbff); + g_assert_cmphex(qtest_readl(qts, base + offset + 1), =3D=3D, 0x77b= bff01); + g_assert_cmphex(qtest_readl(qts, base + offset + 2), =3D=3D, 0xbbf= f0189); + g_assert_cmphex(qtest_readl(qts, base + offset + 3), =3D=3D, 0xff0= 189fe); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x018= 9fe76); + g_assert_cmphex(qtest_readl(qts, base + offset + 5), =3D=3D, 0x89f= e7654); + g_assert_cmphex(qtest_readl(qts, base + offset + 6), =3D=3D, 0xfe7= 65432); + g_assert_cmphex(qtest_readl(qts, base + offset + 7), =3D=3D, 0x765= 43210); + } else { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 1, 0x77665544); + qtest_writel(qts, base + offset + 2, 0xbbaa9988); + qtest_writel(qts, base + offset + 3, 0xffeeddcc); + qtest_writel(qts, base + offset + 4, 0x01234567); + qtest_writel(qts, base + offset + 5, 0x89abcdef); + qtest_writel(qts, base + offset + 6, 0xfedcba98); + qtest_writel(qts, base + offset + 7, 0x76543210); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0xcc8= 84400); + g_assert_cmphex(qtest_readl(qts, base + offset + 1), =3D=3D, 0x67c= c8844); + g_assert_cmphex(qtest_readl(qts, base + offset + 2), =3D=3D, 0xef6= 7cc88); + g_assert_cmphex(qtest_readl(qts, base + offset + 3), =3D=3D, 0x98e= f67cc); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x109= 8ef67); + g_assert_cmphex(qtest_readl(qts, base + offset + 5), =3D=3D, 0x321= 098ef); + g_assert_cmphex(qtest_readl(qts, base + offset + 6), =3D=3D, 0x543= 21098); + g_assert_cmphex(qtest_readl(qts, base + offset + 7), =3D=3D, 0x765= 43210); + } +} + +static void little_l_invalid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 4, 0x77665544); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0x332= 21100); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x776= 65544); + } else { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 4, 0x77665544); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0x332= 21100); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x776= 65544); + } +} + +static void little_q_valid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + qtest_writeq(qts, base + offset + 1, 0xffeeddccbbaa9988); + qtest_writeq(qts, base + offset + 2, 0xfedcba9876543210); + qtest_writeq(qts, base + offset + 3, 0x0123456789abcdef); + qtest_writeq(qts, base + offset + 4, 0xdeadbeefdeadbeef); + qtest_writeq(qts, base + offset + 5, 0xcafebabecafebabe); + qtest_writeq(qts, base + offset + 6, 0xbeefcafebeefcafe); + qtest_writeq(qts, base + offset + 7, 0xfacefeedfacefeed); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0x77fffe01decabefa); + g_assert_cmphex(qtest_readq(qts, base + offset + 1), =3D=3D, + 0xfffe01decabeface); + g_assert_cmphex(qtest_readq(qts, base + offset + 2), =3D=3D, + 0xfe01decabefacefe); + g_assert_cmphex(qtest_readq(qts, base + offset + 3), =3D=3D, + 0x01decabefacefeed); + g_assert_cmphex(qtest_readq(qts, base + offset + 4), =3D=3D, + 0xdecabefacefeedfa); + g_assert_cmphex(qtest_readq(qts, base + offset + 5), =3D=3D, + 0xcabefacefeedface); + g_assert_cmphex(qtest_readq(qts, base + offset + 6), =3D=3D, + 0xbefacefeedfacefe); + g_assert_cmphex(qtest_readq(qts, base + offset + 7), =3D=3D, + 0xfacefeedfacefeed); + } else { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + qtest_writeq(qts, base + offset + 1, 0xffeeddccbbaa9988); + qtest_writeq(qts, base + offset + 2, 0xfedcba9876543210); + qtest_writeq(qts, base + offset + 3, 0x0123456789abcdef); + qtest_writeq(qts, base + offset + 4, 0xdeadbeefdeadbeef); + qtest_writeq(qts, base + offset + 5, 0xcafebabecafebabe); + qtest_writeq(qts, base + offset + 6, 0xbeefcafebeefcafe); + qtest_writeq(qts, base + offset + 7, 0xfacefeedfacefeed); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0xedfebeefef108800); + g_assert_cmphex(qtest_readq(qts, base + offset + 1), =3D=3D, + 0xfeedfebeefef1088); + g_assert_cmphex(qtest_readq(qts, base + offset + 2), =3D=3D, + 0xcefeedfebeefef10); + g_assert_cmphex(qtest_readq(qts, base + offset + 3), =3D=3D, + 0xfacefeedfebeefef); + g_assert_cmphex(qtest_readq(qts, base + offset + 4), =3D=3D, + 0xedfacefeedfebeef); + g_assert_cmphex(qtest_readq(qts, base + offset + 5), =3D=3D, + 0xfeedfacefeedfebe); + g_assert_cmphex(qtest_readq(qts, base + offset + 6), =3D=3D, + 0xcefeedfacefeedfe); + g_assert_cmphex(qtest_readq(qts, base + offset + 7), =3D=3D, + 0xfacefeedfacefeed); + } +} + +static void little_q_invalid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0x7766554433221100); + } else { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0x7766554433221100); + } +} + +static void big_b_valid(QTestState *qts, uint64_t offset) +{ + qtest_writeb(qts, base + offset + 0, 0x00); + qtest_writeb(qts, base + offset + 1, 0x11); + qtest_writeb(qts, base + offset + 2, 0x22); + qtest_writeb(qts, base + offset + 3, 0x33); + qtest_writeb(qts, base + offset + 4, 0x44); + qtest_writeb(qts, base + offset + 5, 0x55); + qtest_writeb(qts, base + offset + 6, 0x66); + qtest_writeb(qts, base + offset + 7, 0x77); + g_assert_cmphex(qtest_readb(qts, base + offset + 0), =3D=3D, 0x00); + g_assert_cmphex(qtest_readb(qts, base + offset + 1), =3D=3D, 0x11); + g_assert_cmphex(qtest_readb(qts, base + offset + 2), =3D=3D, 0x22); + g_assert_cmphex(qtest_readb(qts, base + offset + 3), =3D=3D, 0x33); + g_assert_cmphex(qtest_readb(qts, base + offset + 4), =3D=3D, 0x44); + g_assert_cmphex(qtest_readb(qts, base + offset + 5), =3D=3D, 0x55); + g_assert_cmphex(qtest_readb(qts, base + offset + 6), =3D=3D, 0x66); + g_assert_cmphex(qtest_readb(qts, base + offset + 7), =3D=3D, 0x77); +} + +static void big_b_invalid(QTestState *qts, uint64_t offset) +{ + qtest_writeb(qts, base + offset + 0, 0x00); + qtest_writeb(qts, base + offset + 1, 0x11); + qtest_writeb(qts, base + offset + 2, 0x22); + qtest_writeb(qts, base + offset + 3, 0x33); + qtest_writeb(qts, base + offset + 4, 0x44); + qtest_writeb(qts, base + offset + 5, 0x55); + qtest_writeb(qts, base + offset + 6, 0x66); + qtest_writeb(qts, base + offset + 7, 0x77); + g_assert_cmphex(qtest_readb(qts, base + offset + 0), =3D=3D, 0x00); + g_assert_cmphex(qtest_readb(qts, base + offset + 1), =3D=3D, 0x11); + g_assert_cmphex(qtest_readb(qts, base + offset + 2), =3D=3D, 0x22); + g_assert_cmphex(qtest_readb(qts, base + offset + 3), =3D=3D, 0x33); + g_assert_cmphex(qtest_readb(qts, base + offset + 4), =3D=3D, 0x44); + g_assert_cmphex(qtest_readb(qts, base + offset + 5), =3D=3D, 0x55); + g_assert_cmphex(qtest_readb(qts, base + offset + 6), =3D=3D, 0x66); + g_assert_cmphex(qtest_readb(qts, base + offset + 7), =3D=3D, 0x77); +} + +static void big_w_valid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 1, 0x3322); + qtest_writew(qts, base + offset + 2, 0x5544); + qtest_writew(qts, base + offset + 3, 0x7766); + qtest_writew(qts, base + offset + 4, 0x9988); + qtest_writew(qts, base + offset + 5, 0xbbaa); + qtest_writew(qts, base + offset + 6, 0xddcc); + qtest_writew(qts, base + offset + 7, 0xffee); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x113= 3); + g_assert_cmphex(qtest_readw(qts, base + offset + 1), =3D=3D, 0x335= 5); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x557= 7); + g_assert_cmphex(qtest_readw(qts, base + offset + 3), =3D=3D, 0x779= 9); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0x99b= b); + g_assert_cmphex(qtest_readw(qts, base + offset + 5), =3D=3D, 0xbbd= d); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0xddf= f); + g_assert_cmphex(qtest_readw(qts, base + offset + 7), =3D=3D, 0xffe= e); + } else { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 1, 0x3322); + qtest_writew(qts, base + offset + 2, 0x5544); + qtest_writew(qts, base + offset + 3, 0x7766); + qtest_writew(qts, base + offset + 4, 0x9988); + qtest_writew(qts, base + offset + 5, 0xbbaa); + qtest_writew(qts, base + offset + 6, 0xddcc); + qtest_writew(qts, base + offset + 7, 0xffee); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x220= 0); + g_assert_cmphex(qtest_readw(qts, base + offset + 1), =3D=3D, 0x442= 2); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x664= 4); + g_assert_cmphex(qtest_readw(qts, base + offset + 3), =3D=3D, 0x886= 6); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0xaa8= 8); + g_assert_cmphex(qtest_readw(qts, base + offset + 5), =3D=3D, 0xcca= a); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0xeec= c); + g_assert_cmphex(qtest_readw(qts, base + offset + 7), =3D=3D, 0xffe= e); + } +} + +static void big_w_invalid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 2, 0x3322); + qtest_writew(qts, base + offset + 4, 0x5544); + qtest_writew(qts, base + offset + 6, 0x7766); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x110= 0); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x332= 2); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0x554= 4); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0x776= 6); + } else { + qtest_writew(qts, base + offset + 0, 0x1100); + qtest_writew(qts, base + offset + 2, 0x3322); + qtest_writew(qts, base + offset + 4, 0x5544); + qtest_writew(qts, base + offset + 6, 0x7766); + g_assert_cmphex(qtest_readw(qts, base + offset + 0), =3D=3D, 0x110= 0); + g_assert_cmphex(qtest_readw(qts, base + offset + 2), =3D=3D, 0x332= 2); + g_assert_cmphex(qtest_readw(qts, base + offset + 4), =3D=3D, 0x554= 4); + g_assert_cmphex(qtest_readw(qts, base + offset + 6), =3D=3D, 0x776= 6); + } +} + +static void big_l_valid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 1, 0x77665544); + qtest_writel(qts, base + offset + 2, 0xbbaa9988); + qtest_writel(qts, base + offset + 3, 0xffeeddcc); + qtest_writel(qts, base + offset + 4, 0x01234567); + qtest_writel(qts, base + offset + 5, 0x89abcdef); + qtest_writel(qts, base + offset + 6, 0xfedcba98); + qtest_writel(qts, base + offset + 7, 0x76543210); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0x337= 7bbff); + g_assert_cmphex(qtest_readl(qts, base + offset + 1), =3D=3D, 0x77b= bff01); + g_assert_cmphex(qtest_readl(qts, base + offset + 2), =3D=3D, 0xbbf= f0189); + g_assert_cmphex(qtest_readl(qts, base + offset + 3), =3D=3D, 0xff0= 189fe); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x018= 9fe76); + g_assert_cmphex(qtest_readl(qts, base + offset + 5), =3D=3D, 0x89f= e7654); + g_assert_cmphex(qtest_readl(qts, base + offset + 6), =3D=3D, 0xfe7= 65432); + g_assert_cmphex(qtest_readl(qts, base + offset + 7), =3D=3D, 0x765= 43210); + } else { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 1, 0x77665544); + qtest_writel(qts, base + offset + 2, 0xbbaa9988); + qtest_writel(qts, base + offset + 3, 0xffeeddcc); + qtest_writel(qts, base + offset + 4, 0x01234567); + qtest_writel(qts, base + offset + 5, 0x89abcdef); + qtest_writel(qts, base + offset + 6, 0xfedcba98); + qtest_writel(qts, base + offset + 7, 0x76543210); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0xcc8= 84400); + g_assert_cmphex(qtest_readl(qts, base + offset + 1), =3D=3D, 0x67c= c8844); + g_assert_cmphex(qtest_readl(qts, base + offset + 2), =3D=3D, 0xef6= 7cc88); + g_assert_cmphex(qtest_readl(qts, base + offset + 3), =3D=3D, 0x98e= f67cc); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x109= 8ef67); + g_assert_cmphex(qtest_readl(qts, base + offset + 5), =3D=3D, 0x321= 098ef); + g_assert_cmphex(qtest_readl(qts, base + offset + 6), =3D=3D, 0x543= 21098); + g_assert_cmphex(qtest_readl(qts, base + offset + 7), =3D=3D, 0x765= 43210); + } +} + +static void big_l_invalid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 4, 0x77665544); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0x332= 21100); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x776= 65544); + } else { + qtest_writel(qts, base + offset + 0, 0x33221100); + qtest_writel(qts, base + offset + 4, 0x77665544); + g_assert_cmphex(qtest_readl(qts, base + offset + 0), =3D=3D, 0x332= 21100); + g_assert_cmphex(qtest_readl(qts, base + offset + 4), =3D=3D, 0x776= 65544); + } +} + +static void big_q_valid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + qtest_writeq(qts, base + offset + 1, 0xffeeddccbbaa9988); + qtest_writeq(qts, base + offset + 2, 0xfedcba9876543210); + qtest_writeq(qts, base + offset + 3, 0x0123456789abcdef); + qtest_writeq(qts, base + offset + 4, 0xdeadbeefdeadbeef); + qtest_writeq(qts, base + offset + 5, 0xcafebabecafebabe); + qtest_writeq(qts, base + offset + 6, 0xbeefcafebeefcafe); + qtest_writeq(qts, base + offset + 7, 0xfacefeedfacefeed); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0x77fffe01decabefa); + g_assert_cmphex(qtest_readq(qts, base + offset + 1), =3D=3D, + 0xfffe01decabeface); + g_assert_cmphex(qtest_readq(qts, base + offset + 2), =3D=3D, + 0xfe01decabefacefe); + g_assert_cmphex(qtest_readq(qts, base + offset + 3), =3D=3D, + 0x01decabefacefeed); + g_assert_cmphex(qtest_readq(qts, base + offset + 4), =3D=3D, + 0xdecabefacefeedfa); + g_assert_cmphex(qtest_readq(qts, base + offset + 5), =3D=3D, + 0xcabefacefeedface); + g_assert_cmphex(qtest_readq(qts, base + offset + 6), =3D=3D, + 0xbefacefeedfacefe); + g_assert_cmphex(qtest_readq(qts, base + offset + 7), =3D=3D, + 0xfacefeedfacefeed); + } else { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + qtest_writeq(qts, base + offset + 1, 0xffeeddccbbaa9988); + qtest_writeq(qts, base + offset + 2, 0xfedcba9876543210); + qtest_writeq(qts, base + offset + 3, 0x0123456789abcdef); + qtest_writeq(qts, base + offset + 4, 0xdeadbeefdeadbeef); + qtest_writeq(qts, base + offset + 5, 0xcafebabecafebabe); + qtest_writeq(qts, base + offset + 6, 0xbeefcafebeefcafe); + qtest_writeq(qts, base + offset + 7, 0xfacefeedfacefeed); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0xedfebeefef108800); + g_assert_cmphex(qtest_readq(qts, base + offset + 1), =3D=3D, + 0xfeedfebeefef1088); + g_assert_cmphex(qtest_readq(qts, base + offset + 2), =3D=3D, + 0xcefeedfebeefef10); + g_assert_cmphex(qtest_readq(qts, base + offset + 3), =3D=3D, + 0xfacefeedfebeefef); + g_assert_cmphex(qtest_readq(qts, base + offset + 4), =3D=3D, + 0xedfacefeedfebeef); + g_assert_cmphex(qtest_readq(qts, base + offset + 5), =3D=3D, + 0xfeedfacefeedfebe); + g_assert_cmphex(qtest_readq(qts, base + offset + 6), =3D=3D, + 0xcefeedfacefeedfe); + g_assert_cmphex(qtest_readq(qts, base + offset + 7), =3D=3D, + 0xfacefeedfacefeed); + } +} + +static void big_q_invalid(QTestState *qts, hwaddr offset) +{ + if (qtest_big_endian(qts)) { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0x7766554433221100); + } else { + qtest_writeq(qts, base + offset + 0, 0x7766554433221100); + g_assert_cmphex(qtest_readq(qts, base + offset + 0), =3D=3D, + 0x7766554433221100); + } +} + +#define DEFINE_test_memaccess(e, e_u, w, w_u, v, v_u) \ + static void \ + test_memaccess_##e##_##w##_##v(void) \ + { \ + QTestState *qts; \ + qts =3D create_memaccess_qtest(); \ + if (!qts) { \ + return; \ + } \ + \ + for (size_t i =3D OFF_IDX_OPS_LIST_##e_u##_##w_u##_##v_u; \ + i < OFF_IDX_OPS_LIST_##e_u##_##w_u##_##v_u + \ + N_OPS_LIST_##e_u##_##w_u##_##v_u; \ + i++) { \ + e##_##w##_##v(qts, MEMACCESS_TESTDEV_REGION_SIZE * i); \ + } \ + \ + qtest_quit(qts); \ + } + +DEFINE_test_memaccess(little, LITTLE, b, B, valid, VALID) +DEFINE_test_memaccess(little, LITTLE, w, W, valid, VALID) +DEFINE_test_memaccess(little, LITTLE, l, L, valid, VALID) +DEFINE_test_memaccess(little, LITTLE, q, Q, valid, VALID) +DEFINE_test_memaccess(little, LITTLE, b, B, invalid, INVALID) +DEFINE_test_memaccess(little, LITTLE, w, W, invalid, INVALID) +DEFINE_test_memaccess(little, LITTLE, l, L, invalid, INVALID) +DEFINE_test_memaccess(little, LITTLE, q, Q, invalid, INVALID) +DEFINE_test_memaccess(big, BIG, b, B, valid, VALID) +DEFINE_test_memaccess(big, BIG, w, W, valid, VALID) +DEFINE_test_memaccess(big, BIG, l, L, valid, VALID) +DEFINE_test_memaccess(big, BIG, q, Q, valid, VALID) +DEFINE_test_memaccess(big, BIG, b, B, invalid, INVALID) +DEFINE_test_memaccess(big, BIG, w, W, invalid, INVALID) +DEFINE_test_memaccess(big, BIG, l, L, invalid, INVALID) +DEFINE_test_memaccess(big, BIG, q, Q, invalid, INVALID) + +#undef DEFINE_test_memaccess + +static struct { + const char *name; + void (*test)(void); +} tests[] =3D { + {"little_b_valid", test_memaccess_little_b_valid}, + {"little_w_valid", test_memaccess_little_w_valid}, + {"little_l_valid", test_memaccess_little_l_valid}, + {"little_q_valid", test_memaccess_little_q_valid}, + {"little_b_invalid", test_memaccess_little_b_invalid}, + {"little_w_invalid", test_memaccess_little_w_invalid}, + {"little_l_invalid", test_memaccess_little_l_invalid}, + {"little_q_invalid", test_memaccess_little_q_invalid}, + {"big_b_valid", test_memaccess_big_b_valid}, + {"big_w_valid", test_memaccess_big_w_valid}, + {"big_l_valid", test_memaccess_big_l_valid}, + {"big_q_valid", test_memaccess_big_q_valid}, + {"big_b_invalid", test_memaccess_big_b_invalid}, + {"big_w_invalid", test_memaccess_big_w_invalid}, + {"big_l_invalid", test_memaccess_big_l_invalid}, + {"big_q_invalid", test_memaccess_big_q_invalid}, +}; + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + arch =3D qtest_get_arch(); + + for (int i =3D 0; i < ARRAY_SIZE(tests); i++) { + g_autofree gchar *path =3D g_strdup_printf("memaccess/%s", tests[i= ].name); + qtest_add_func(path, tests[i].test); + } + + return g_test_run(); +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 669d07c06b..5d721b2c60 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -95,6 +95,7 @@ qtests_i386 =3D \ (config_all_devices.has_key('CONFIG_SDHCI_PCI') ? ['fuzz-sdcard-test'] := []) + \ (config_all_devices.has_key('CONFIG_ESP_PCI') ? ['am53c974-test'] : []) = + \ (config_all_devices.has_key('CONFIG_VTD') ? ['intel-iommu-test'] : []) += \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ (host_os !=3D 'windows' and = \ config_all_devices.has_key('CONFIG_ACPI_ERST') ? ['erst-test'] : []) + = \ (config_all_devices.has_key('CONFIG_PCIE_PORT') and = \ @@ -138,6 +139,7 @@ qtests_x86_64 =3D qtests_i386 =20 qtests_alpha =3D ['boot-serial-test'] + \ qtests_filter + \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) =20 qtests_avr =3D [ 'boot-serial-test' ] @@ -162,6 +164,7 @@ qtests_microblazeel =3D qtests_microblaze =20 qtests_mips =3D \ qtests_filter + \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] = : []) + \ (config_all_devices.has_key('CONFIG_VGA') ? ['display-vga-test'] : []) =20 @@ -172,6 +175,7 @@ qtests_mips64el =3D qtests_mips qtests_ppc =3D \ qtests_filter + \ (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] = : []) + \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ (config_all_accel.has_key('CONFIG_TCG') ? ['prom-env-test'] : []) + = \ (config_all_accel.has_key('CONFIG_TCG') ? ['boot-serial-test'] : []) + = \ ['boot-order-test'] @@ -198,6 +202,7 @@ qtests_sparc =3D ['prom-env-test', 'm48t59-test', 'boot= -serial-test'] + \ =20 qtests_sparc64 =3D \ (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] = : []) + \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ qtests_filter + \ ['prom-env-test', 'boot-serial-test'] =20 @@ -248,6 +253,7 @@ qtests_arm =3D \ (config_all_devices.has_key('CONFIG_FSI_APB2OPB_ASPEED') ? ['aspeed_fsi-= test'] : []) + \ (config_all_devices.has_key('CONFIG_STM32L4X5_SOC') and config_all_devices.has_key('CONFIG_DM163')? ['dm163-test'] : []) + \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ ['arm-cpu-features', 'boot-serial-test'] =20 @@ -263,6 +269,7 @@ qtests_aarch64 =3D \ config_all_devices.has_key('CONFIG_TPM_TIS_I2C') ? ['tpm-tis-i2c-test']= : []) + \ (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed64 : [])= + \ (config_all_devices.has_key('CONFIG_NPCM8XX') ? qtests_npcm8xx : []) + \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ qtests_cxl + = \ ['arm-cpu-features', 'numa-test', @@ -279,9 +286,11 @@ qtests_s390x =3D \ 'migration-test'] =20 qtests_riscv32 =3D \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ (config_all_devices.has_key('CONFIG_SIFIVE_E_AON') ? ['sifive-e-aon-watc= hdog-test'] : []) =20 qtests_riscv64 =3D ['riscv-csr-test'] + \ + (config_all_devices.has_key('CONFIG_MEMACCESS_TESTDEV') ? ['memaccess-te= st'] : []) + \ (unpack_edk2_blobs ? ['bios-tables-test'] : []) =20 qos_test_ss =3D ss.source_set() --=20 2.25.1