From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845062; cv=none; d=zohomail.com; s=zohoarc; b=UVgPDv9PqQwoEtwiI4N2ol14ibcX4dKrWVcLbpbvABh1LVpg2jheK6xAR5nm8MWzsMG5HN+8pK5EVlij0cIUypvQdXco3EQehr7Hb6SN+mI2JPQHjQlfQvlpJv3p2ztk5SXLRQyHi4z6CGkXn+BEXps4bHVzYNUgWYOm6xAZv3c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845062; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=H5RBf6uKx6SK1+4nyy1fvgmXpfy9p0pMwO9mbFph6dk=; b=cZkjr3JqtsBMqc19ZLRm6hfRfUQRdaRpfVHF3GKffk/8MasEVdc0KVxsdsPRlaixourngtp2B04LMoQinN1sKxvqxrC4+2/v3i07BIUiJtif/B9aXccJMhjHzL/08zwCYSklb19IJJ8dD6lB2faXopkrrdE0wj7ae2VFc+aLQqs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845062803606.940482450641; Thu, 21 Aug 2025 23:44:22 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLT2-0007sL-9t; Fri, 22 Aug 2025 02:41:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLSv-0007ne-Bf for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:34 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLSs-0000j3-Ly for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:32 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:27 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:23 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844891; x=1787380891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qz6dBz67PvF3w5m2Or4UnsyKWWxfPTSdtaFRhbfkH2s=; b=jK+N9mCEo3Ay994AUEtAiAZE/33rC8KoZ9lg7hjt6vzsBtZPVP+qJxx2 HKQFs4J1TCHfeTv0cAPCgspzgr0tjjJG0Y6T8FtCYFJmx6ZkxggdPGmgY F5lynnA56Dv/uvuis5vTOqPMx8z1Pbhp6yKas5JKhruJ+JGJz8qL5Tmk8 bqB7UoCiUhHd9DR6PCXdpAts3Rd77eDBf24MVkeh+5YEDjraEdDeR3iMG j8lPkhgvD46wCZlIL7HXC1vYh/OfSO8RIo9GtQ0RDyZ8uv2aRV5WHAGx1 gRbQphAlhsM/ge+giExOxzd2Cd2qMCqzmTerruKHrikt/v4fJb8WmySRt Q==; X-CSE-ConnectionGUID: euDIH7aUSlODQCFVi5QdNQ== X-CSE-MsgGUID: +2tQDY4bTjOFzBXdTCMD4A== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851753" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851753" X-CSE-ConnectionGUID: 0R7IHyArQnGeZnkddZXZEA== X-CSE-MsgGUID: rOrU1AB+RJqL6CgGho513A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244834" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 01/21] intel_iommu: Rename vtd_ce_get_rid2pasid_entry to vtd_ce_get_pasid_entry Date: Fri, 22 Aug 2025 02:40:39 -0400 Message-ID: <20250822064101.123526-2-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845064395124100 In early days vtd_ce_get_rid2pasid_entry() was used to get pasid entry of rid2pasid, then it was extended to get any pasid entry. So a new name vtd_ce_get_pasid_entry is better to match what it actually does. No functional change intended. Signed-off-by: Zhenzhong Duan Reviewed-by: Cl=C3=A9ment Mathieu--Drif Reviewed-by: Yi Liu Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen --- hw/i386/intel_iommu.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 83c5e44413..04809bd776 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -944,7 +944,7 @@ static int vtd_get_pe_from_pasid_table(IntelIOMMUState = *s, return 0; } =20 -static int vtd_ce_get_rid2pasid_entry(IntelIOMMUState *s, +static int vtd_ce_get_pasid_entry(IntelIOMMUState *s, VTDContextEntry *ce, VTDPASIDEntry *pe, uint32_t pasid) @@ -1025,7 +1025,7 @@ static uint32_t vtd_get_iova_level(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return VTD_PE_GET_FL_LEVEL(&pe); } else { @@ -1048,7 +1048,7 @@ static uint32_t vtd_get_iova_agaw(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return 30 + ((pe.val[0] >> 2) & VTD_SM_PASID_ENTRY_AW) * 9; } =20 @@ -1116,7 +1116,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; } else { @@ -1522,7 +1522,7 @@ static int vtd_ce_rid2pasid_check(IntelIOMMUState *s, * has valid rid2pasid setting, which includes valid * rid2pasid field and corresponding pasid entry setting */ - return vtd_ce_get_rid2pasid_entry(s, ce, &pe, PCI_NO_PASID); + return vtd_ce_get_pasid_entry(s, ce, &pe, PCI_NO_PASID); } =20 /* Map a device to its corresponding domain (context-entry) */ @@ -1611,7 +1611,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, VTDPASIDEntry pe; =20 if (s->root_scalable) { - vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + vtd_ce_get_pasid_entry(s, ce, &pe, pasid); return VTD_SM_PASID_ENTRY_DID(pe.val[1]); } =20 @@ -1687,7 +1687,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, int ret; =20 if (s->root_scalable) { - ret =3D vtd_ce_get_rid2pasid_entry(s, ce, &pe, pasid); + ret =3D vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (ret) { /* * This error is guest triggerable. We should assumt PT --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845121; cv=none; d=zohomail.com; s=zohoarc; b=D2qLn1A9nvz6RU6QN5j55kAR9y/HzeEavBt5SDbF5TPhokA97fBS5tMwGi74UiRavsqJcoIVhqbciV9pONglCpH+we2ZDE+IjSwCYarxILzSTpuU4VPUAqyR0OytZFVeh1peBmv3MDc4zT93AMfyS64H/IXJBLDoqpn5gO+NyQs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845121; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=on7/i7UbnG2Z0tv41938f5hOgn8ZA5xEQAgBRuHqGTg=; b=BCwgCAVE02CJTSjbdOidGaIuwOOBSzWlSpf/5fjaOR4KyB92sErN3Pl526Qu4pwnRjQxJb8iflhJQWs2T0PukIvjE2lq4uO8+1AhO0VrDHy0d/PnUlLO9y9tHDnGoBH+Gy9WwPC9MYcWwTTEdmeTA2wOazOj3+iioFb+kmLLOXU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845121817577.6466003536403; Thu, 21 Aug 2025 23:45:21 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLT0-0007rn-8P; Fri, 22 Aug 2025 02:41:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLSx-0007pK-Dk for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:36 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLSv-0000jU-A8 for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:35 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:31 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:27 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844893; x=1787380893; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=u2+r5WMNAselXw4pM/VEPi5BKFkWq0X7IfAEDfJ/odY=; b=j51rwmGqFL7V4ez2oVYhDTg7sURg4MOkPeGU0KvxMKl0SRiiHAdZsv7b VkkDgWaFzOGIab9kGek3UPjpO5UPg0HDaLD4bq52hhN/A0moZgnbeK0Aw Y5QDwiwfUUJTInE9AwDQPOJRwnSyvtQJjz+HUZgvq8PDVdZB5Ww7MPXz3 wYQPHMqAjDY9F7SUfMm+FwDpf6E6MDQ995IJp4h1EQ9U/l5os3V9IznUk mhTlVmMdunHOU2mfTj6MWhqjhBoLNKUKPWFWVpeSUWFFS9TNK0PTNbo7M QhiDrTVq7TeHmr/uvYmrAufdChrybqRc4qOorzxSEs9NJkMGn3Ouwr/al A==; X-CSE-ConnectionGUID: wwJ97NsXS3ODbd/M5tOQsA== X-CSE-MsgGUID: yhJXJxpESzi6wv0Uhb5PhQ== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851775" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851775" X-CSE-ConnectionGUID: XZIHusllRMi5myx0UYeBVA== X-CSE-MsgGUID: Br9lqWkQQ/aGzBccmjV9kQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244852" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 02/21] hw/pci: Introduce pci_device_get_viommu_cap() Date: Fri, 22 Aug 2025 02:40:40 -0400 Message-ID: <20250822064101.123526-3-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845122713116600 Content-Type: text/plain; charset="utf-8" Introduce a new PCIIOMMUOps optional callback, get_viommu_cap() which allows to retrieve capabilities exposed by a vIOMMU. The first planned vIOMMU device capability is VIOMMU_CAP_HW_NESTED that advertises the support of HW nested stage translation scheme. pci_device_get_viommu_cap is a wrapper that can be called on a PCI device potentially protected by a vIOMMU. get_viommu_cap() is designed to return 64bit bitmap of purely emulated capabilities which are only determined by user's configuration, no host capabilities involved. Reasons are: 1. host may has heterogeneous IOMMUs, each with different capabilities 2. this is migration friendly, return value is consistent between source and target. 3. host IOMMU capabilities are passed to vIOMMU through set_iommu_device() interface which have to be after attach_device(), when get_viommu_cap() is called in attach_device(), there is no way for vIOMMU to get host IOMMU capabilities yet, so only emulated capabilities can be returned. See below sequence: vfio_device_attach(): iommufd_cdev_attach(): pci_device_get_viommu_cap() for HW nesting cap create a nesting parent hwpt attach device to the hwpt vfio_device_hiod_create_and_realize() creating hiod ... pci_device_set_iommu_device(hiod) Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen --- MAINTAINERS | 1 + include/hw/iommu.h | 19 +++++++++++++++++++ include/hw/pci/pci.h | 25 +++++++++++++++++++++++++ hw/pci/pci.c | 11 +++++++++++ 4 files changed, 56 insertions(+) create mode 100644 include/hw/iommu.h diff --git a/MAINTAINERS b/MAINTAINERS index a07086ed76..54fb878128 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -2305,6 +2305,7 @@ F: include/system/iommufd.h F: backends/host_iommu_device.c F: include/system/host_iommu_device.h F: include/qemu/chardev_open.h +F: include/hw/iommu.h F: util/chardev_open.c F: docs/devel/vfio-iommufd.rst =20 diff --git a/include/hw/iommu.h b/include/hw/iommu.h new file mode 100644 index 0000000000..7dd0c11b16 --- /dev/null +++ b/include/hw/iommu.h @@ -0,0 +1,19 @@ +/* + * General vIOMMU capabilities, flags, etc + * + * Copyright (C) 2025 Intel Corporation. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_IOMMU_H +#define HW_IOMMU_H + +#include "qemu/bitops.h" + +enum { + /* hardware nested stage-1 page table support */ + VIOMMU_CAP_HW_NESTED =3D BIT_ULL(0), +}; + +#endif /* HW_IOMMU_H */ diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index 6b7d3ac8a3..cde7a54a69 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -462,6 +462,21 @@ typedef struct PCIIOMMUOps { * @devfn: device and function number of the PCI device. */ void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); + /** + * @get_viommu_cap: get vIOMMU capabilities + * + * Optional callback, if not implemented, then vIOMMU doesn't + * support exposing capabilities to other subsystem, e.g., VFIO. + * vIOMMU can choose which capabilities to expose. + * + * @opaque: the data passed to pci_setup_iommu(). + * + * Returns: 64bit bitmap with each bit represents a capability emulate= d by + * VIOMMU_CAP_* in include/hw/iommu.h, these capabilities are theoreti= cal + * which are only determined by vIOMMU device properties and independe= nt + * on the actual host capabilities they may depend on. + */ + uint64_t (*get_viommu_cap)(void *opaque); /** * @get_iotlb_info: get properties required to initialize a device IOT= LB. * @@ -642,6 +657,16 @@ bool pci_device_set_iommu_device(PCIDevice *dev, HostI= OMMUDevice *hiod, Error **errp); void pci_device_unset_iommu_device(PCIDevice *dev); =20 +/** + * pci_device_get_viommu_cap: get vIOMMU capabilities. + * + * Returns a 64bit bitmap with each bit represents a vIOMMU exposed + * capability, 0 if vIOMMU doesn't support exposing capabilities. + * + * @dev: PCI device pointer. + */ +uint64_t pci_device_get_viommu_cap(PCIDevice *dev); + /** * pci_iommu_get_iotlb_info: get properties required to initialize a * device IOTLB. diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c70b5ceeba..df1fb615a8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2992,6 +2992,17 @@ void pci_device_unset_iommu_device(PCIDevice *dev) } } =20 +uint64_t pci_device_get_viommu_cap(PCIDevice *dev) +{ + PCIBus *iommu_bus; + + pci_device_get_iommu_bus_devfn(dev, &iommu_bus, NULL, NULL); + if (iommu_bus && iommu_bus->iommu_ops->get_viommu_cap) { + return iommu_bus->iommu_ops->get_viommu_cap(iommu_bus->iommu_opaqu= e); + } + return 0; +} + int pci_pri_request_page(PCIDevice *dev, uint32_t pasid, bool priv_req, bool exec_req, hwaddr addr, bool lpig, uint16_t prgi, bool is_read, bool is_write) --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845024; cv=none; d=zohomail.com; s=zohoarc; b=TmbXqHobmFf/H9gkLN0VsVyrIHZrvtZI174slUeXomM5ojLEvqA6a4CAuHqSAk+Kod6+XcQTWl+IOThCePhfCO2z5oetGBMhCLymqsKNbgnuotKV9n5bY1SizNSWx6lOXkGd8MCPFL1J9w1984WvLYlY7ipyE4H+eCtYEuuYMf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845024; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=7L+MhAG1jz+CLnPg3oWnpdqnOo85hjJX/2aBAsM4CRU=; b=daTOfUFklyPuu9NjxMi4B8SxAVs2O6j5I7hJWy1aZe1IHxmT3oENacx7PIFLg/cEjANBx5ONoXltqM43Q9hTRGAg4VT86n2UMmWBqgnDa3wzGr0Ar1CtuREMigE9Fc4MMw1Ibf9ijDqYZN8TQZCNlTCmJhszHYvapCpSoqcEpII= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845024635104.08434368782707; Thu, 21 Aug 2025 23:43:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLT3-0007sq-PP; Fri, 22 Aug 2025 02:41:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLT0-0007ru-2K for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:38 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLSy-0000jU-6a for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:37 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:35 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:31 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844896; x=1787380896; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z36AfEmSiPDXm19F6cD9vWfxnxoT0B8XdLknhQkjFYQ=; b=NG1sJUWbGcv/uSvsEIHgXI2qXH4z0uQWNNhO0kMO55euh4TLp+50/+FU 1g7i7RO9fCG9wIubseZJTUwzhifAq5+eXAuLUtH5vcsFFdvNdTDI02WGS 8dxIr1/G0//S4aD12Rf+VNRc5hY9lYTH+2eDL4cAkRyLLrWtCRuXCC2O/ k9yuI9+jHmhvhnkgqyTvTD8EXntTgqH7hoK9KrpcIm1qEQGZTAyn/aaNZ caYd0Mtx//MmgASJznr0il604Fx8fGVL3kcwoworzzlBj92AusTAq5sGM rGIMBJ3TWFoGmHNVpc9ENLgf85GA5iu2sXk3EVgtOUcb+OuMUisDkWofN w==; X-CSE-ConnectionGUID: ZTF0Nz5KTtCrU5layY3IMA== X-CSE-MsgGUID: 8wEMtnYORgOHnMe2sznZUw== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851784" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851784" X-CSE-ConnectionGUID: aR+dp3jdQRuSPiNUUIBC1A== X-CSE-MsgGUID: wKdnOcauQKKB9T/68J/lIg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244893" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 03/21] intel_iommu: Implement get_viommu_cap() callback Date: Fri, 22 Aug 2025 02:40:41 -0400 Message-ID: <20250822064101.123526-4-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845026163124100 Content-Type: text/plain; charset="utf-8" Implement get_viommu_cap() callback and expose stage-1 capability for now. VFIO uses it to create nested parent domain which is further used to create nested domain in vIOMMU. All these will be implemented in following patches. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen --- hw/i386/intel_iommu.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 04809bd776..e3b871de70 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -24,6 +24,7 @@ #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/sysbus.h" +#include "hw/iommu.h" #include "intel_iommu_internal.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" @@ -4423,6 +4424,16 @@ static void vtd_dev_unset_iommu_device(PCIBus *bus, = void *opaque, int devfn) vtd_iommu_unlock(s); } =20 +static uint64_t vtd_get_viommu_cap(void *opaque) +{ + IntelIOMMUState *s =3D opaque; + uint64_t caps; + + caps =3D s->flts ? VIOMMU_CAP_HW_NESTED : 0; + + return caps; +} + /* Unmap the whole range in the notifier's scope. */ static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n) { @@ -4853,6 +4864,7 @@ static PCIIOMMUOps vtd_iommu_ops =3D { .register_iotlb_notifier =3D vtd_register_iotlb_notifier, .unregister_iotlb_notifier =3D vtd_unregister_iotlb_notifier, .ats_request_translation =3D vtd_ats_request_translation, + .get_viommu_cap =3D vtd_get_viommu_cap, }; =20 static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755844959; cv=none; d=zohomail.com; s=zohoarc; b=a/K0teA52EoRB3CXOaidyGNL+DW+7aKu6DT9IE6iXlwwDTnpaisX8tSB/k9xcfIo9mptS6Cj3o5dbhMDAXyWdhij2vftaeZmvqUGKGQmHql4s1LuF9fvi4J8TS79Qa735nRwNlUAngNESNsZ2RsfmNbSE8jVbgD3+vyE67pZtSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755844959; h=Content-Type:Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=DOpePTCe1ugovydYswVgTr2UUs+tL23UrsZwLTbCQCo=; b=lkHgV/DSmwHfKC0kUBkiA5etlpB4edrwZFWeUZ+/ADYDPqEbjjUkXb7xi5tv3LMCuZFNxaqLZ8t8T1L03hJ9M6f5bJAq7A2Sk+aP2hQR2pJiNyfcfCMf8vK9Kr5WIBNbMhbIghwtgFjHrwpn7MAfMO4uSrwAmlsIOg9gWzvVruY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755844959099251.8672044699323; Thu, 21 Aug 2025 23:42:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLT7-0007vB-QN; Fri, 22 Aug 2025 02:41:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLT4-0007u2-KJ for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:43 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLT2-0000jU-66 for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:42 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:39 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:36 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844900; x=1787380900; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=j9BUDEdPkepsUPSsAMfsaiLzD6xBlNlki1/uTIHYAWc=; b=VolTzfVLRBskIG8obH8wvk50uXwqzIWPCdKd4ANRq6tLkXjBQV5h/XuP qZGvrxO8MW1nrpWZU6xS+K5GvTrxDIFYzPgb12gUjg0Efg3YZKfVhV7Vu 3pmvcbueNeSZK6PrnipARi5P3EyJSOUMrk7aWYpKr+YnDWQFWsmKEgkQC OuWzyDt/nwIwib3+TY593F9WFpiihN7eEx245drtMAdLaXQK7q4pk1cvo BKyyKc69u+d2lnFYpY8AxoDJzohrle3QRHwKTBqyWvmF9JEOLcCo9iCo2 oyinw7c0JDRGRomFS/G3oK4azC7goto5ETHdwPzTYHfSZmbO8reHnQxH2 w==; X-CSE-ConnectionGUID: Ehvfy0/+QWi1+y6Vcaq53Q== X-CSE-MsgGUID: AhP9MUSgRemwL6mdCN690Q== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851813" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851813" X-CSE-ConnectionGUID: ixvjr/V5RESm482mdX4WQg== X-CSE-MsgGUID: RIZVvEuKQEOg+gYy53aMEA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244907" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 04/21] vfio: Introduce helper vfio_pci_from_vfio_device() Date: Fri, 22 Aug 2025 02:40:42 -0400 Message-ID: <20250822064101.123526-5-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755844961893124100 Introduce helper vfio_pci_from_vfio_device() to transform from VFIODevice to VFIOPCIDevice, also to hide low level VFIO_DEVICE_TYPE_PCI type check. Suggested-by: C=C3=A9dric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: C=C3=A9dric Le Goater Link: https://lore.kernel.org/qemu-devel/20250801023533.1458644-1-zhenzhong= .duan@intel.com [ clg: Added documentation ] Signed-off-by: C=C3=A9dric Le Goater Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Yi Liu --- hw/vfio/pci.h | 12 ++++++++++++ hw/vfio/container.c | 4 ++-- hw/vfio/device.c | 2 +- hw/vfio/iommufd.c | 4 ++-- hw/vfio/listener.c | 4 ++-- hw/vfio/pci.c | 9 +++++++++ 6 files changed, 28 insertions(+), 7 deletions(-) diff --git a/hw/vfio/pci.h b/hw/vfio/pci.h index 810a842f4a..beb8fb9ee7 100644 --- a/hw/vfio/pci.h +++ b/hw/vfio/pci.h @@ -221,6 +221,18 @@ void vfio_pci_write_config(PCIDevice *pdev, uint64_t vfio_vga_read(void *opaque, hwaddr addr, unsigned size); void vfio_vga_write(void *opaque, hwaddr addr, uint64_t data, unsigned siz= e); =20 +/** + * vfio_pci_from_vfio_device: Transform from VFIODevice to + * VFIOPCIDevice + * + * This function checks if the given @vbasedev is a VFIO PCI device. + * If it is, it returns the containing VFIOPCIDevice. + * + * @vbasedev: The VFIODevice to transform + * + * Return: The VFIOPCIDevice on success, NULL on failure. + */ +VFIOPCIDevice *vfio_pci_from_vfio_device(VFIODevice *vbasedev); void vfio_sub_page_bar_update_mappings(VFIOPCIDevice *vdev); bool vfio_opt_rom_in_denylist(VFIOPCIDevice *vdev); bool vfio_config_quirk_setup(VFIOPCIDevice *vdev, Error **errp); diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 3e13feaa74..134ddccc52 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -1087,7 +1087,7 @@ static int vfio_legacy_pci_hot_reset(VFIODevice *vbas= edev, bool single) /* Prep dependent devices for reset and clear our marker. */ QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { if (!vbasedev_iter->dev->realized || - vbasedev_iter->type !=3D VFIO_DEVICE_TYPE_PCI) { + !vfio_pci_from_vfio_device(vbasedev_iter)) { continue; } tmp =3D container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); @@ -1172,7 +1172,7 @@ out: =20 QLIST_FOREACH(vbasedev_iter, &group->device_list, next) { if (!vbasedev_iter->dev->realized || - vbasedev_iter->type !=3D VFIO_DEVICE_TYPE_PCI) { + !vfio_pci_from_vfio_device(vbasedev_iter)) { continue; } tmp =3D container_of(vbasedev_iter, VFIOPCIDevice, vbasedev); diff --git a/hw/vfio/device.c b/hw/vfio/device.c index 52a1996dc4..08f12ac31f 100644 --- a/hw/vfio/device.c +++ b/hw/vfio/device.c @@ -129,7 +129,7 @@ static inline const char *action_to_str(int action) =20 static const char *index_to_str(VFIODevice *vbasedev, int index) { - if (vbasedev->type !=3D VFIO_DEVICE_TYPE_PCI) { + if (!vfio_pci_from_vfio_device(vbasedev)) { return NULL; } =20 diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 48c590b6a9..8c27222f75 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -737,8 +737,8 @@ iommufd_cdev_dep_get_realized_vpdev(struct vfio_pci_dep= endent_device *dep_dev, } =20 vbasedev_tmp =3D iommufd_cdev_pci_find_by_devid(dep_dev->devid); - if (!vbasedev_tmp || !vbasedev_tmp->dev->realized || - vbasedev_tmp->type !=3D VFIO_DEVICE_TYPE_PCI) { + if (!vfio_pci_from_vfio_device(vbasedev_tmp) || + !vbasedev_tmp->dev->realized) { return NULL; } =20 diff --git a/hw/vfio/listener.c b/hw/vfio/listener.c index f498e23a93..903dfd8bf2 100644 --- a/hw/vfio/listener.c +++ b/hw/vfio/listener.c @@ -450,7 +450,7 @@ static void vfio_device_error_append(VFIODevice *vbased= ev, Error **errp) * MMIO region mapping failures are not fatal but in this case PCI * peer-to-peer transactions are broken. */ - if (vbasedev && vbasedev->type =3D=3D VFIO_DEVICE_TYPE_PCI) { + if (vfio_pci_from_vfio_device(vbasedev)) { error_append_hint(errp, "%s: PCI peer-to-peer transactions " "on BARs are not supported.\n", vbasedev->name); } @@ -751,7 +751,7 @@ static bool vfio_section_is_vfio_pci(MemoryRegionSectio= n *section, owner =3D memory_region_owner(section->mr); =20 QLIST_FOREACH(vbasedev, &bcontainer->device_list, container_next) { - if (vbasedev->type !=3D VFIO_DEVICE_TYPE_PCI) { + if (!vfio_pci_from_vfio_device(vbasedev)) { continue; } pcidev =3D container_of(vbasedev, VFIOPCIDevice, vbasedev); diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 07257d0fa0..3fe5b03eb1 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -2833,6 +2833,15 @@ static int vfio_pci_load_config(VFIODevice *vbasedev= , QEMUFile *f) return ret; } =20 +/* Transform from VFIODevice to VFIOPCIDevice. Return NULL if fails. */ +VFIOPCIDevice *vfio_pci_from_vfio_device(VFIODevice *vbasedev) +{ + if (vbasedev && vbasedev->type =3D=3D VFIO_DEVICE_TYPE_PCI) { + return container_of(vbasedev, VFIOPCIDevice, vbasedev); + } + return NULL; +} + void vfio_sub_page_bar_update_mappings(VFIOPCIDevice *vdev) { PCIDevice *pdev =3D &vdev->pdev; --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755844957; cv=none; d=zohomail.com; s=zohoarc; b=LnNoATmmEMom5G4sUx50TXuFgTvZP3gJ0AbHa10Db5hYJIf7Bc6cMXm33RyYWn6C4GVFvT6YidHL/K448OVWmeVIdpk6Yvc8sAfJhHVpvf2+7GMWFVbIANie6faVWnT1jNRSvJ1s0NJRNZrNEIS/SDEoWQEppxvswzS1DqP0QpM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755844957; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=g6PfwlcsX7BOW1RSi5ZVuASgB0IaZBfdqHJbSx1X3/o=; b=c15rrhxuttqFNmRPu4z6heAWuIUrmynNo6zki9cfSnp9MN1ftUV9zmnuF0eqSNSrxsMetgjk1Hw1LZDH21doe17KG375LEMjVhspluSAiiD+OL5tK338112bXO4hjZBGLgLbTDw3sK6D0/XPK1hCKXO9lp8M8Uy9F4P/WAfEkUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175584495757835.303190455175695; Thu, 21 Aug 2025 23:42:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTC-0007wl-Vo; Fri, 22 Aug 2025 02:41:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTA-0007vi-4Y for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:48 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLT6-0000jU-Jm for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:47 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:43 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:40 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844905; x=1787380905; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mr67aEYKMDhmS6xMylNnySePBuQpUauAiP6fTNis1Dw=; b=GEVrnFEpynrNqJUXbNbsgdsLeBTZoIv/HtQg/lbLJ41DpubCASV42DhM FZdr5xfWE5s1Ys8TQp3eBjpqGgjZMAt6S8LS1918pWkqxGJoZ/7l0uITh kUFbUxnPzIeykEtHWnzlnnf3+1jITJUKXKrwF2FWl8qSgRcFj5aEnBzDx veaLA7mVO5kDJ7xdo/jjghLr1pJmVHCib2pXyWQ7Mr72kxPfdY3buPJU2 GCscgcRedwDcpnBKCZozC+pN/VdX1UaAmtNR7n+Oj7kdrRny3OpS2drtj MtIChbzQXEuVQbk+bmCe2/bx1Im87kpk8w/chULAC0Ap0R2Ysb0+yGXfH g==; X-CSE-ConnectionGUID: u7N1BJ02QGS7UxQfuCH0EQ== X-CSE-MsgGUID: QJEHYUEuQjunRlNranHGeQ== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851840" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851840" X-CSE-ConnectionGUID: AVNMUW7QT1q7yuuktzuGMA== X-CSE-MsgGUID: Z2N2N0KeTCWNCNkr6hWpug== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244922" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 05/21] vfio/iommufd: Force creating nested parent domain Date: Fri, 22 Aug 2025 02:40:43 -0400 Message-ID: <20250822064101.123526-6-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755844961843124100 Content-Type: text/plain; charset="utf-8" Call pci_device_get_viommu_cap() to get if vIOMMU supports VIOMMU_CAP_HW_NE= STED, if yes, create nested parent domain which could be reused by vIOMMU to crea= te nested domain. Introduce helper vfio_device_viommu_get_nested to facilitate this implementation. It is safe because even if VIOMMU_CAP_HW_NESTED is returned, s->flts is forbidden and VFIO device fails in set_iommu_device() call, until we support passthrough device with x-flts=3Don. Suggested-by: Nicolin Chen Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Nicolin Chen --- include/hw/vfio/vfio-device.h | 2 ++ hw/vfio/device.c | 12 ++++++++++++ hw/vfio/iommufd.c | 8 ++++++++ 3 files changed, 22 insertions(+) diff --git a/include/hw/vfio/vfio-device.h b/include/hw/vfio/vfio-device.h index 6e4d5ccdac..ecd82c16c7 100644 --- a/include/hw/vfio/vfio-device.h +++ b/include/hw/vfio/vfio-device.h @@ -257,6 +257,8 @@ void vfio_device_prepare(VFIODevice *vbasedev, VFIOCont= ainerBase *bcontainer, =20 void vfio_device_unprepare(VFIODevice *vbasedev); =20 +bool vfio_device_viommu_get_nested(VFIODevice *vbasedev); + int vfio_device_get_region_info(VFIODevice *vbasedev, int index, struct vfio_region_info **info); int vfio_device_get_region_info_type(VFIODevice *vbasedev, uint32_t type, diff --git a/hw/vfio/device.c b/hw/vfio/device.c index 08f12ac31f..3eeb71bd51 100644 --- a/hw/vfio/device.c +++ b/hw/vfio/device.c @@ -23,6 +23,7 @@ =20 #include "hw/vfio/vfio-device.h" #include "hw/vfio/pci.h" +#include "hw/iommu.h" #include "hw/hw.h" #include "trace.h" #include "qapi/error.h" @@ -504,6 +505,17 @@ void vfio_device_unprepare(VFIODevice *vbasedev) vbasedev->bcontainer =3D NULL; } =20 +bool vfio_device_viommu_get_nested(VFIODevice *vbasedev) +{ + VFIOPCIDevice *vdev =3D vfio_pci_from_vfio_device(vbasedev); + + if (vdev) { + return !!(pci_device_get_viommu_cap(&vdev->pdev) & + VIOMMU_CAP_HW_NESTED); + } + return false; +} + /* * Traditional ioctl() based io */ diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index 8c27222f75..e503c232e1 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -379,6 +379,14 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *v= basedev, flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING; } =20 + /* + * If vIOMMU supports stage-1 translation, force to create nested pare= nt + * domain which could be reused by vIOMMU to create nested domain. + */ + if (vfio_device_viommu_get_nested(vbasedev)) { + flags |=3D IOMMU_HWPT_ALLOC_NEST_PARENT; + } + if (cpr_is_incoming()) { hwpt_id =3D vbasedev->cpr.hwpt_id; goto skip_alloc; --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845281; cv=none; d=zohomail.com; s=zohoarc; b=KeZmvy6Nz4kxKtmVb0ZUAheIkN+oaDIdAlvZGlhyGS1fMRaWeGOziZEmBbvgYfA5Wv7BSQnieLaYEpfxQtMqy+S8m7u8kzy822WzxzkMFycmWdWw2reFaP8dz3pzMORSif7BhWdtPMga0D4NKL1KjwYG+dtSrkGa/CxuXptYWUo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845281; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=68RpR1gw0SwZLoNC91bvog911nRLibFxM/8EWXPEgKE=; b=SNiOgqYcJcQfIzoTbDkgcMxLjoQ0C8F9So9ZRbVj6Y2k8fJHgaBJVwMiu1zUDLI7i6BEpSyBnshnMeZpiXJ5hIfmwUZFFY2lwXZVnbcenGXYzvjqSO79xkiey+5YE+oiaGgS5jUq5sOlr67ss7zdGcQrq1bM+yMpyO65VRBGSWs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845281972246.90906341085577; Thu, 21 Aug 2025 23:48:01 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTD-0007wn-5e; Fri, 22 Aug 2025 02:41:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTC-0007we-KX for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:50 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTA-0000jU-I6 for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:50 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:47 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:44 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844908; x=1787380908; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qtFeILwVk/LV3Z164OzSZJ5mhlnK18pSRXjY88VE0O0=; b=HH+D+//uGhTM5gUAmNA+ibz1wwkEzrg2kea+k+Aj2CHR4V2t5FfJcEss cn2lP9XwMG5dAIeFdVRuUKW98JBQsUs8cz5e4OMF3ntYI6Cpm8osdbpdl lGu5ziGMY2vROSXLhwaJTVyiTg9rvvxSWGin4x/KTBcvcpEBTINbmX9Mt Dtm6KHgGSkQHsZxPuFMlzhP19P/8I0UTSIE+WeJy6m2VGktlo/3DQr5LZ lXOcVqHK96+1UV8Z39JwbAvElQmFaD8ePM1ynKTBpt1+LhQZmxL4AYoGh Cco/QnyMP8DzPg4p+sohBblnyX4NTS9qOcCkrRPnRtmoJ+aaF9638BFZ0 w==; X-CSE-ConnectionGUID: Q1RDtGCRRcy1Z1UcSINaOQ== X-CSE-MsgGUID: 5raHKSg+Q0itvemN/HyTPQ== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851860" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851860" X-CSE-ConnectionGUID: iam5zphpQpC469UUusfLrQ== X-CSE-MsgGUID: 5Puo0PfKTkWJixUIihxjUA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244928" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 06/21] hw/pci: Export pci_device_get_iommu_bus_devfn() and return bool Date: Fri, 22 Aug 2025 02:40:44 -0400 Message-ID: <20250822064101.123526-7-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845284337116600 Content-Type: text/plain; charset="utf-8" Returns true if PCI device is aliased or false otherwise. This will be used in following patch to determine if a PCI device is under a PCI bridge. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Yi Liu --- include/hw/pci/pci.h | 2 ++ hw/pci/pci.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index cde7a54a69..34b4edbf1a 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -652,6 +652,8 @@ typedef struct PCIIOMMUOps { bool is_write); } PCIIOMMUOps; =20 +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn); AddressSpace *pci_device_iommu_address_space(PCIDevice *dev); bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod, Error **errp); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index df1fb615a8..151c27088b 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2857,20 +2857,21 @@ static void pci_device_class_base_init(ObjectClass = *klass, const void *data) * For call sites which don't need aliased BDF, passing NULL to * aliased_[bus|devfn] is allowed. * + * Returns true if PCI device RID is aliased or false otherwise. + * * @piommu_bus: return root #PCIBus backed by an IOMMU for the PCI device. * * @aliased_bus: return aliased #PCIBus of the PCI device, optional. * * @aliased_devfn: return aliased devfn of the PCI device, optional. */ -static void pci_device_get_iommu_bus_devfn(PCIDevice *dev, - PCIBus **piommu_bus, - PCIBus **aliased_bus, - int *aliased_devfn) +bool pci_device_get_iommu_bus_devfn(PCIDevice *dev, PCIBus **piommu_bus, + PCIBus **aliased_bus, int *aliased_dev= fn) { PCIBus *bus =3D pci_get_bus(dev); PCIBus *iommu_bus =3D bus; int devfn =3D dev->devfn; + bool aliased =3D false; =20 while (iommu_bus && !iommu_bus->iommu_ops && iommu_bus->parent_dev) { PCIBus *parent_bus =3D pci_get_bus(iommu_bus->parent_dev); @@ -2907,6 +2908,7 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, devfn =3D parent->devfn; bus =3D parent_bus; } + aliased =3D true; } =20 iommu_bus =3D parent_bus; @@ -2928,6 +2930,8 @@ static void pci_device_get_iommu_bus_devfn(PCIDevice = *dev, if (aliased_devfn) { *aliased_devfn =3D devfn; } + + return aliased; } =20 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev) --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845072; cv=none; d=zohomail.com; s=zohoarc; b=CBm3xWLq+v6n3xRas3NA83BsBVkY+VOukU/RmzK3LgPyIRib7J35kK0MUK1Mj0+0jZRz+RGj34weLLytYI2GpcxieOYZGcbL9iuWhUaJfOED0qF7ss/PvT5yuQZ60ZUTAUmnc3/VdRCke53V5y7Kl4PTaZxgkNIwHr1VG3YtO90= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845072; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=czFny7oD8IMgJvZB3pWGms7tf4vBdTo3E+5RtuBTOsg=; b=Z9StHje5MYe6Ti2BgwqzrctRFTltuFKT9OiKCqrb9Z90fWmL5EML/Ph9/2pz24eaVUjBTPi1nY3XjMxkkbIcPYVEijNgHjOvyaFGhoYE9qbpLbznOwGXRbcxcVmYy6rhim8DLMgMMHVuZJQOBReDuWrXcgtdsfDhVM/l6ClMaRM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845072317434.35166131675066; Thu, 21 Aug 2025 23:44:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTI-0007xk-LY; Fri, 22 Aug 2025 02:41:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTH-0007xX-58 for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:55 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTF-0000lZ-5T for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:54 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:51 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:48 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844913; x=1787380913; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cbj3Q3CU6iijEloLU2KvYIjvZBZ93O7eB2oa1du7vSM=; b=JATp1ZxaCVsGGKVhimNqNqkB/+d7nDYvIXK0tFi3JBzADCFcXFLnxN+9 RCts+y3WZAWgk31KX6XwPib3b/zIxlrfe8HT586yqdVB5gXtv5ViUDbn4 O+arub9OMLCTC5H2bVaZtiKTPCvaGmkLywIXe+QbhBvNkoGFvStCkVxJC dqucolWYWv32I56ABEpBhKYMCgvpMX0MUcqMYP22ONGfCMjQO2TE9PNqg 4uE5u6GnbvXono79KemnuOry6undXWYDdeDkBq76qS4RtUwgh47PH2Mqa PAlz7jIL3RKdf8UlasCGQZnG6wgm3AIDYwyPnx2I01ZKP8IUZ/WWJkQZ0 Q==; X-CSE-ConnectionGUID: DsJ2/zaFTompAVyj8Pyq8A== X-CSE-MsgGUID: cYVgzxUkQ2aC0apDkBfrjw== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851874" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851874" X-CSE-ConnectionGUID: eM08LdQQQielWoKetnXfWg== X-CSE-MsgGUID: jlU840mnR+q+KnWABvhdGg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244938" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 07/21] intel_iommu: Introduce a new structure VTDHostIOMMUDevice Date: Fri, 22 Aug 2025 02:40:45 -0400 Message-ID: <20250822064101.123526-8-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845074396116600 Content-Type: text/plain; charset="utf-8" Introduce a new structure VTDHostIOMMUDevice which replaces HostIOMMUDevice to be stored in hash table. It includes a reference to HostIOMMUDevice and IntelIOMMUState, also includes BDF information which will be used in future patches. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Nicolin Chen Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 7 +++++++ include/hw/i386/intel_iommu.h | 2 +- hw/i386/intel_iommu.c | 15 +++++++++++++-- 3 files changed, 21 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 360e937989..c7046eb4e2 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -28,6 +28,7 @@ #ifndef HW_I386_INTEL_IOMMU_INTERNAL_H #define HW_I386_INTEL_IOMMU_INTERNAL_H #include "hw/i386/intel_iommu.h" +#include "system/host_iommu_device.h" =20 /* * Intel IOMMU register specification @@ -608,4 +609,10 @@ typedef struct VTDRootEntry VTDRootEntry; /* Bits to decide the offset for each level */ #define VTD_LEVEL_BITS 9 =20 +typedef struct VTDHostIOMMUDevice { + IntelIOMMUState *iommu_state; + PCIBus *bus; + uint8_t devfn; + HostIOMMUDevice *hiod; +} VTDHostIOMMUDevice; #endif diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index e95477e855..50f9b27a45 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -295,7 +295,7 @@ struct IntelIOMMUState { /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 - GHashTable *vtd_host_iommu_dev; /* HostIOMMUDevice */ + GHashTable *vtd_host_iommu_dev; /* VTDHostIOMMUDevice */ =20 /* interrupt remapping */ bool intr_enabled; /* Whether guest enabled IR */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index e3b871de70..512ca4fdc5 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -281,7 +281,10 @@ static gboolean vtd_hiod_equal(gconstpointer v1, gcons= tpointer v2) =20 static void vtd_hiod_destroy(gpointer v) { - object_unref(v); + VTDHostIOMMUDevice *vtd_hiod =3D v; + + object_unref(vtd_hiod->hiod); + g_free(vtd_hiod); } =20 static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, @@ -4371,6 +4374,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, HostIOMMUDevice *hiod, Error **errp) { IntelIOMMUState *s =3D opaque; + VTDHostIOMMUDevice *vtd_hiod; struct vtd_as_key key =3D { .bus =3D bus, .devfn =3D devfn, @@ -4387,7 +4391,14 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, vo= id *opaque, int devfn, return false; } =20 + vtd_hiod =3D g_malloc0(sizeof(VTDHostIOMMUDevice)); + vtd_hiod->bus =3D bus; + vtd_hiod->devfn =3D (uint8_t)devfn; + vtd_hiod->iommu_state =3D s; + vtd_hiod->hiod =3D hiod; + if (!vtd_check_hiod(s, hiod, errp)) { + g_free(vtd_hiod); vtd_iommu_unlock(s); return false; } @@ -4397,7 +4408,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, new_key->devfn =3D devfn; =20 object_ref(hiod); - g_hash_table_insert(s->vtd_host_iommu_dev, new_key, hiod); + g_hash_table_insert(s->vtd_host_iommu_dev, new_key, vtd_hiod); =20 vtd_iommu_unlock(s); =20 --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845023; cv=none; d=zohomail.com; s=zohoarc; b=TJL3QmPStCWkairKVCQzKoklvwgr3XdvUzaG2xAMxOybQvaLIefsGDat93kXt2ofIBqocvT5gEioolEOBz1cAH/Ygpj3OBoqs9FRYT7VBld+zRNPzMxnYofgR7w+HW82MFMNdM50uJB8RHdke8Lj+TwRCAqZfBpHWUKjxPTQlrY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845023; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=AEGHdNjRtvIz22i2SPYgEayNFkgN9IADziGN+yCV9vs=; b=noVNFvzgENwmJrmbhLScBEpzLMKcwI0RxXODsUc6J/NbIrJ5+cqSZupp8zvCjz0ieIV5s6GJBpM1TCTzcYFzql90tymYCjUm8rMpj8ZVEeNAsrHjF3wN/QDd772qxl5M1MF2OAJWGT/u0HGe3OQIEF6GMWmvYTqE5kWDmhAAdMI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845023295542.9878236848809; Thu, 21 Aug 2025 23:43:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTM-0007zV-1h; Fri, 22 Aug 2025 02:42:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTK-0007ya-9m for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:58 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTI-0000lZ-1N for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:41:57 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:55 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:52 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844916; x=1787380916; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=JE7nwL5OsxUQdPfDzwLdaqc7O9sf7StnsOE5x6dWgxI=; b=W+WsAgnnaucidqE5OE7Y7pH1NJMAwB6imKfxtc1oxysFIAuG8owIVBcq GBPMk/XIc3wcDU8vRoDELovvnYVZMx2TRtfFmpzDOg29Sm99FL9m6L3H0 bwU+Rzw+bZh22ZJedpr3tQ+B8gzkza/cit1F2GDYiM+qZtPX/ytgDPhEr TsDfCn9B9Ao6A+HKGwAFWCcymjH6XtHi5bsjp8IQGdQTkvQZLE/+KodK9 590oldwOQ8tatIhK8Vzo3nREgtbZfwuWbVWEqVBMnCTmnlGd9D43qvmhA e3OyNSvdu0NjZIXLclmX5YtGuY611bKiGGpspwKaaCU+h39yqKcPJUS2t Q==; X-CSE-ConnectionGUID: B8URwJuxQ4aiHYuiiRzLNw== X-CSE-MsgGUID: gHZj26QrQ6qo1uciz/+voQ== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851887" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851887" X-CSE-ConnectionGUID: X2cOLmZqSkSiRBGrMXVgjw== X-CSE-MsgGUID: YzGo5ychRv6mgY+VFByNaw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244946" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 08/21] intel_iommu: Check for compatibility with IOMMUFD backed device when x-flts=on Date: Fri, 22 Aug 2025 02:40:46 -0400 Message-ID: <20250822064101.123526-9-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845026179124100 Content-Type: text/plain; charset="utf-8" When vIOMMU is configured x-flts=3Don in scalable mode, stage-1 page table is passed to host to construct nested page table. We need to check compatibility of some critical IOMMU capabilities between vIOMMU and host IOMMU to ensure guest stage-1 page table could be used by host. For instance, vIOMMU supports stage-1 1GB huge page mapping, but host does not, then this IOMMUFD backed device should fail. Even of the checks pass, for now we willingly reject the association because all the bits are not there yet. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu --- hw/i386/intel_iommu_internal.h | 1 + hw/i386/intel_iommu.c | 30 +++++++++++++++++++++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c7046eb4e2..f7510861d1 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -192,6 +192,7 @@ #define VTD_ECAP_PT (1ULL << 6) #define VTD_ECAP_SC (1ULL << 7) #define VTD_ECAP_MHMV (15ULL << 20) +#define VTD_ECAP_NEST (1ULL << 26) #define VTD_ECAP_SRS (1ULL << 31) #define VTD_ECAP_PSS (7ULL << 35) /* limit: MemTxAttrs::pid= */ #define VTD_ECAP_PASID (1ULL << 40) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 512ca4fdc5..da355bda79 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -40,6 +40,7 @@ #include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "trace.h" +#include "system/iommufd.h" =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -4366,7 +4367,34 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, return true; } =20 - error_setg(errp, "host device is uncompatible with stage-1 translation= "); +#ifdef CONFIG_IOMMUFD + struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; + struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + + /* Remaining checks are all stage-1 translation specific */ + if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { + error_setg(errp, "Need IOMMUFD backend when x-flts=3Don"); + return false; + } + + if (caps->type !=3D IOMMU_HW_INFO_TYPE_INTEL_VTD) { + error_setg(errp, "Incompatible host platform IOMMU type %d", + caps->type); + return false; + } + + if (!(vtd->ecap_reg & VTD_ECAP_NEST)) { + error_setg(errp, "Host IOMMU doesn't support nested translation"); + return false; + } + + if (s->fs1gp && !(vtd->cap_reg & VTD_CAP_FS1GP)) { + error_setg(errp, "Stage-1 1GB huge page is unsupported by host IOM= MU"); + return false; + } +#endif + + error_setg(errp, "host IOMMU is incompatible with stage-1 translation"= ); return false; } =20 --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845209; cv=none; d=zohomail.com; s=zohoarc; b=dh94fe5/6sRHz2zZlc9ZW3GiVeYkCaa4uldDD9vfuYYG1KV2U8bXRS/aSfse4IaGFJ9VG5gD2rOeBprXHaW350ECtwPwJT6Bu/7J7h28J4aYYmeRFfZangGZnsfMSsTUit2VncU9CsSeyPWZzQaMQFdDHSZsaG3gh7uL6TqDenw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845209; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=HLydYf1P8oMJaXpuFQcDImsJm8q4sT5CEQaDJa8vW64=; b=lCObVxdMuh14TnhkHbvDR3MuF8g4gWjP5aZZ1z04SpsGHHPQsZvz55a+C6vzSUljRlXsg22fUjNMK1+Urv6BTEx9U+ILgefHeKpw8JUmj+Fjkfvkm9K66RJScKJaY8JM72Ocj5WP0sNiu1Ix3qRw2t02PTA+3khSQ5xLNNdujNs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845209122560.1450473074278; Thu, 21 Aug 2025 23:46:49 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTP-00080G-Oh; Fri, 22 Aug 2025 02:42:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTO-000804-2G for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:02 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTM-0000lZ-0Q for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:01 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:59 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:55 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844920; x=1787380920; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Wr/sgImnKqsUB/Q1Gf5g12dW3k4+5Z8EsJGY2u7UEXo=; b=OcLU5jAVyu1rfqZfE28gbpsAfYUCqC97PaAoQatbZUduNvKKK9u35rvR iK6DaslONLvvCwYw8le74o1qww9mYKOBsj2EtahUfQ+YVbJHsLBQKnfBP G44VWCF/qGQg2mRttQPg3iiYFdYKwSaFyBgB1AL2EDn+UMksefIwtZh0J 9yjRb/SnIlRnvO13M4di8ePmeB8Hyj4sMVppB4bJp4ngu8iKBaTTvLb6M UC4WmDvYnxgLC7EcQYlt4iFHhqieKW0ZyVvQirMcnuARM0vx9ofB+tYR1 ZKI4PdSuhB3z2SBhxDt/ROVIS4K7jccG7QPQOogU9GBJtCPpA+A177JRn A==; X-CSE-ConnectionGUID: YXD9ppnPSGuFrsylzJG/vA== X-CSE-MsgGUID: 93c7jG1iSjmdYC2xSZXCcg== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851901" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851901" X-CSE-ConnectionGUID: cnbKnYCnTy2jM849mOPbLw== X-CSE-MsgGUID: yNkLsunpSme8e3KrzeFUKQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244954" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 09/21] intel_iommu: Fail passthrough device under PCI bridge if x-flts=on Date: Fri, 22 Aug 2025 02:40:47 -0400 Message-ID: <20250822064101.123526-10-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845210165124100 Content-Type: text/plain; charset="utf-8" Currently we don't support nested translation for passthrough device with emulated device under same PCI bridge, because they require different addre= ss space when x-flts=3Don. In theory, we do support if devices under same PCI bridge are all passthrou= gh devices. But emulated device can be hotplugged under same bridge. To simpli= fy, just forbid passthrough device under PCI bridge no matter if there is, or w= ill be emulated devices under same bridge. This is acceptable because PCIE brid= ge is more popular than PCI bridge now. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 13 +++++++++++-- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index da355bda79..6edd91d94e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -4341,9 +4341,10 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s,= PCIBus *bus, return vtd_dev_as; } =20 -static bool vtd_check_hiod(IntelIOMMUState *s, HostIOMMUDevice *hiod, +static bool vtd_check_hiod(IntelIOMMUState *s, VTDHostIOMMUDevice *vtd_hio= d, Error **errp) { + HostIOMMUDevice *hiod =3D vtd_hiod->hiod; HostIOMMUDeviceClass *hiodc =3D HOST_IOMMU_DEVICE_GET_CLASS(hiod); int ret; =20 @@ -4370,6 +4371,8 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostIO= MMUDevice *hiod, #ifdef CONFIG_IOMMUFD struct HostIOMMUDeviceCaps *caps =3D &hiod->caps; struct iommu_hw_info_vtd *vtd =3D &caps->vendor_caps.vtd; + PCIBus *bus =3D vtd_hiod->bus; + PCIDevice *pdev =3D pci_find_device(bus, pci_bus_num(bus), vtd_hiod->d= evfn); =20 /* Remaining checks are all stage-1 translation specific */ if (!object_dynamic_cast(OBJECT(hiod), TYPE_HOST_IOMMU_DEVICE_IOMMUFD)= ) { @@ -4392,6 +4395,12 @@ static bool vtd_check_hiod(IntelIOMMUState *s, HostI= OMMUDevice *hiod, error_setg(errp, "Stage-1 1GB huge page is unsupported by host IOM= MU"); return false; } + + if (pci_device_get_iommu_bus_devfn(pdev, &bus, NULL, NULL)) { + error_setg(errp, "Host device under PCI bridge is unsupported " + "when x-flts=3Don"); + return false; + } #endif =20 error_setg(errp, "host IOMMU is incompatible with stage-1 translation"= ); @@ -4425,7 +4434,7 @@ static bool vtd_dev_set_iommu_device(PCIBus *bus, voi= d *opaque, int devfn, vtd_hiod->iommu_state =3D s; vtd_hiod->hiod =3D hiod; =20 - if (!vtd_check_hiod(s, hiod, errp)) { + if (!vtd_check_hiod(s, vtd_hiod, errp)) { g_free(vtd_hiod); vtd_iommu_unlock(s); return false; --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755844957; cv=none; d=zohomail.com; s=zohoarc; b=CDVGbrg8dXhemvlWvQiQoPoqOp+h9L+dy6C7eJLFOq7A6yd8SttMJW+VUb4loTzlRj7vSuT6ANbxkBjcfYYF2jXVqgq5cM06u8d7LKrPjOxZZMymX/fpympUsSmfj0cf+jbTP1+VrwIznqqQhG6no6agGxWBmlH/WLfKJivAoIA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755844957; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=+yvgHvHbqU0nIQK0VO6c45fmvqBnKB1iE7Gt+IhrxmE=; b=B+cQ38Goo/a6rXj++GpDXdk8sXhf9VM/CBs0FdqM6sQ+x0+kMxQGsTqhWLnDK9sf64w5pYXZHMx9X5IYu2s9vUtpduD4v4bt2+pL8eV9TKIan74XjUWqT+SDmgwEdqtai+eoQ84J2zJSbVi5ZZ9p2QbNm6fAWt/xxt9D+AuVmpg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755844957578274.1397602830567; Thu, 21 Aug 2025 23:42:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTU-00083i-DP; Fri, 22 Aug 2025 02:42:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTS-000820-3B for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:06 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTQ-0000lZ-1b for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:05 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:03 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:41:59 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844924; x=1787380924; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=n1AYY9sLKpZLVrmwGwJBs088FA6QHkXkQvSnpeX3C4U=; b=X+0aOYHeXB70tl98g2AT3AplHnWdyCqlJ+KQfz5I+/bopLlHnPP64YB1 tWWa1A7fbxIuw44yfmaEkpXlqUzCGqAKaBt02tIPvs2CLjmTzeh8e61gb mmAOfYvnmA4dGLPuNmVZBQCF+PtJmpcAeL9+EmfrA+vageqXqtbz0dJb4 VsFXyuCvXjqGIh90Fk/0sQGIBFMr7HI8BPD1ofL+tGfU0W3l9DpnGfYFC iu2IkpDk67yUCZvVkoCgOJaddBlAshx3zVNPNBOeMg231ogAjpUoTYwT2 QCytz1Vp3woRA9sqCt0K0Ym6d8NEP28jUpcjKH63zRwJyl2BHBXSSqMaQ A==; X-CSE-ConnectionGUID: QAhBRx/NSg2CUR6a4jGKPg== X-CSE-MsgGUID: GYB5IdWGRpSk4Qe3PwPJWA== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851910" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851910" X-CSE-ConnectionGUID: 7DKYZpbRRuK4w8HiP2rIcA== X-CSE-MsgGUID: 3gIMtUioSBWT8QA29iveuA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244963" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 10/21] intel_iommu: Introduce two helpers vtd_as_from/to_iommu_pasid_locked Date: Fri, 22 Aug 2025 02:40:48 -0400 Message-ID: <20250822064101.123526-11-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755844962167124100 Content-Type: text/plain; charset="utf-8" PCI device supports two request types, Requests-without-PASID and Requests-with-PASID. Requests-without-PASID doesn't include a PASID TLP prefix, IOMMU fetches rid_pasid from context entry and use it as IOMMU's pasid to index pasid table. So we need to translate between PCI's pasid and IOMMU's pasid specially for Requests-without-PASID, e.g., PCI_NO_PASID(-1) <-> rid_pasid. For Requests-with-PASID, PCI's pasid and IOMMU's pasid are same value. vtd_as_from_iommu_pasid_locked() translates from BDF+iommu_pasid to vtd_as which contains PCI's pasid vtd_as->pasid. vtd_as_to_iommu_pasid_locked() translates from BDF+vtd_as->pasid to iommu_p= asid. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 58 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 58 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6edd91d94e..1801f1cdf6 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1602,6 +1602,64 @@ static int vtd_dev_to_context_entry(IntelIOMMUState = *s, uint8_t bus_num, return 0; } =20 +static int vtd_as_to_iommu_pasid_locked(VTDAddressSpace *vtd_as, + uint32_t *pasid) +{ + VTDContextCacheEntry *cc_entry =3D &vtd_as->context_cache_entry; + IntelIOMMUState *s =3D vtd_as->iommu_state; + uint8_t bus_num =3D pci_bus_num(vtd_as->bus); + uint8_t devfn =3D vtd_as->devfn; + VTDContextEntry ce; + int ret; + + /* For Requests-with-PASID, its pasid value is used by vIOMMU directly= */ + if (vtd_as->pasid !=3D PCI_NO_PASID) { + *pasid =3D vtd_as->pasid; + return 0; + } + + if (cc_entry->context_cache_gen =3D=3D s->context_cache_gen) { + ce =3D cc_entry->context_entry; + } else { + ret =3D vtd_dev_to_context_entry(s, bus_num, devfn, &ce); + if (ret) { + return ret; + } + } + + *pasid =3D VTD_CE_GET_RID2PASID(&ce); + return 0; +} + +static gboolean vtd_find_as_by_sid_and_iommu_pasid(gpointer key, gpointer = value, + gpointer user_data) +{ + VTDAddressSpace *vtd_as =3D (VTDAddressSpace *)value; + struct vtd_as_raw_key *target =3D (struct vtd_as_raw_key *)user_data; + uint16_t sid =3D PCI_BUILD_BDF(pci_bus_num(vtd_as->bus), vtd_as->devfn= ); + uint32_t pasid; + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return false; + } + + return (pasid =3D=3D target->pasid) && (sid =3D=3D target->sid); +} + +/* Translate iommu pasid to vtd_as */ +static inline +VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, + uint16_t sid, uint32_t pas= id) +{ + struct vtd_as_raw_key key =3D { + .sid =3D sid, + .pasid =3D pasid + }; + + return g_hash_table_find(s->vtd_address_spaces, + vtd_find_as_by_sid_and_iommu_pasid, &key); +} + static int vtd_sync_shadow_page_hook(const IOMMUTLBEvent *event, void *private) { --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845296; cv=none; d=zohomail.com; s=zohoarc; b=Sq5PFIYOaOKu+5EQ/zifSp8OEnRl0NlPOce3Lx7LSg2B5pDEW0poFv5UffZ2+sA89bFCFLLULwtGl0kc5a4B0vuyaFKnpSm5ZTp/7IGS6xV5DFGPG71Pk5mCVm3A1iaD5Qe1OUUPLB0iYtwJHqM4mYlLtzoW1J7zb7HCrUm6Leg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845296; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=dfRB0fvDcUQsPhTC4WQGp0iZKz5vkOtqrA34mC9dpl8=; b=ecGyDEJuu410/s7LTG1dg8Srj6Kz7iweYMKs6MdDm80Rj3hGlppVLUeluf+fndR3eI8oaCiYWtqTDgUUiYE2ta7yhUU+/FFSvjYUN51GvToCb3jBfSy6cPMu+YuQuc1cwcpwS5ihoV7/ae2TS+wtzfFohnjiytJCjnSmHN+Dvtg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845296680761.0677173918025; Thu, 21 Aug 2025 23:48:16 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTZ-000858-5f; Fri, 22 Aug 2025 02:42:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTW-00084b-VL for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:10 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTU-0000lZ-Bp for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:10 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:07 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:03 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844928; x=1787380928; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AyYedKklAZi/NEoMIK5BUi2qLYrPdx9QROvkxOI1fJ4=; b=lZTw5OxgM+IaMqsvIj7KTP7XDzoGJkUuPmNS3KTynq6jKzSY93+SMHkh r89gVViukAGbdDEpIJhucZracQfWWs6c3EYRXRJuC4+zDFRljE6CuXqCy mVwtTOUD4wHuTMyl36RaxGBN1Iv737sVbuYd4br2L9aDVsl5lEeOIXn2j L2C3C4cBvr/tVRksnTwFsVyAPgN4RkOLkLDdNvP+b+X0AEeY6vmJIXUtq u1yyV2uBDSg2f/8t+qDf9c9CY0cckRRNzM4vcLqYyf3ZJYas3SlTCedLR xncj8cuHw6LP25/XJj+s8hBDy8UdYf0lAXLlJfnleuiC2LpF/44TAOft/ Q==; X-CSE-ConnectionGUID: mOhsaHqsRbOf64EGxfwGdA== X-CSE-MsgGUID: GQKKWVhjQN2bprUxDv8VRA== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851916" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851916" X-CSE-ConnectionGUID: 2WQQp8p6QtCPmhrEHOiWvg== X-CSE-MsgGUID: zvY01fC4SRqfAG9tEcUYpw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244975" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v5 11/21] intel_iommu: Handle PASID entry removal and update Date: Fri, 22 Aug 2025 02:40:49 -0400 Message-ID: <20250822064101.123526-12-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845298583116600 Content-Type: text/plain; charset="utf-8" This adds an new entry VTDPASIDCacheEntry in VTDAddressSpace to cache the pasid entry and track PASID usage and future PASID tagged DMA address translation support in vIOMMU. VTDAddressSpace of PCI_NO_PASID is allocated when device is plugged and never freed. For other pasid, VTDAddressSpace instance is created/destroyed per the guest pasid entry set up/destroy. When guest removes or updates a PASID entry, QEMU will capture the guest pa= sid selective pasid cache invalidation, removes VTDAddressSpace or update cached PASID entry. vIOMMU emulator could figure out the reason by fetching latest guest pasid = entry and compare it with cached PASID entry. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 27 ++++- include/hw/i386/intel_iommu.h | 6 + hw/i386/intel_iommu.c | 196 +++++++++++++++++++++++++++++++-- hw/i386/trace-events | 3 + 4 files changed, 220 insertions(+), 12 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index f7510861d1..b9b76dd996 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -316,6 +316,7 @@ typedef enum VTDFaultReason { * request while disabled */ VTD_FR_IR_SID_ERR =3D 0x26, /* Invalid Source-ID */ =20 + VTD_FR_RTADDR_INV_TTM =3D 0x31, /* Invalid TTM in RTADDR */ /* PASID directory entry access failure */ VTD_FR_PASID_DIR_ACCESS_ERR =3D 0x50, /* The Present(P) field of pasid directory entry is 0 */ @@ -493,6 +494,15 @@ typedef union VTDInvDesc VTDInvDesc; #define VTD_INV_DESC_PIOTLB_RSVD_VAL0 0xfff000000000f1c0ULL #define VTD_INV_DESC_PIOTLB_RSVD_VAL1 0xf80ULL =20 +/* PASID-cache Invalidate Descriptor (pc_inv_dsc) fields */ +#define VTD_INV_DESC_PASIDC_G(x) extract64((x)->val[0], 4, 2) +#define VTD_INV_DESC_PASIDC_G_DSI 0 +#define VTD_INV_DESC_PASIDC_G_PASID_SI 1 +#define VTD_INV_DESC_PASIDC_G_GLOBAL 3 +#define VTD_INV_DESC_PASIDC_DID(x) extract64((x)->val[0], 16, 16) +#define VTD_INV_DESC_PASIDC_PASID(x) extract64((x)->val[0], 32, 20) +#define VTD_INV_DESC_PASIDC_RSVD_VAL0 0xfff000000000f1c0ULL + /* Information about page-selective IOTLB invalidate */ struct VTDIOTLBPageInvInfo { uint16_t domain_id; @@ -553,6 +563,21 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPCInvType { + /* VTD spec defined PASID cache invalidation type */ + VTD_PASID_CACHE_DOMSI =3D VTD_INV_DESC_PASIDC_G_DSI, + VTD_PASID_CACHE_PASIDSI =3D VTD_INV_DESC_PASIDC_G_PASID_SI, + VTD_PASID_CACHE_GLOBAL_INV =3D VTD_INV_DESC_PASIDC_G_GLOBAL, +} VTDPCInvType; + +typedef struct VTDPASIDCacheInfo { + VTDPCInvType type; + uint16_t did; + uint32_t pasid; + PCIBus *bus; + uint16_t devfn; +} VTDPASIDCacheInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) @@ -574,7 +599,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_PASID_ENTRY_PT (4ULL << 6) =20 #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-widt= h */ -#define VTD_SM_PASID_ENTRY_DID(val) ((val) & VTD_DOMAIN_ID_MASK) +#define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16) =20 #define VTD_SM_PASID_ENTRY_FLPM 3ULL #define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 50f9b27a45..0e3826f6f0 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -95,6 +95,11 @@ struct VTDPASIDEntry { uint64_t val[8]; }; =20 +typedef struct VTDPASIDCacheEntry { + struct VTDPASIDEntry pasid_entry; + bool valid; +} VTDPASIDCacheEntry; + struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; @@ -107,6 +112,7 @@ struct VTDAddressSpace { MemoryRegion iommu_ir_fault; /* Interrupt region for catching fault */ IntelIOMMUState *iommu_state; VTDContextCacheEntry context_cache_entry; + VTDPASIDCacheEntry pasid_cache_entry; QLIST_ENTRY(VTDAddressSpace) next; /* Superset of notifier flags that this address space has */ IOMMUNotifierFlag notifier_flags; diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 1801f1cdf6..a2ee6d684e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1675,7 +1675,7 @@ static uint16_t vtd_get_domain_id(IntelIOMMUState *s, =20 if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); - return VTD_SM_PASID_ENTRY_DID(pe.val[1]); + return VTD_SM_PASID_ENTRY_DID(&pe); } =20 return VTD_CONTEXT_ENTRY_DID(ce->hi); @@ -3112,6 +3112,183 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState= *s, return true; } =20 +static inline int vtd_dev_get_pe_from_pasid(VTDAddressSpace *vtd_as, + uint32_t pasid, VTDPASIDEntry = *pe) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDContextEntry ce; + int ret; + + if (!s->root_scalable) { + return -VTD_FR_RTADDR_INV_TTM; + } + + ret =3D vtd_dev_to_context_entry(s, pci_bus_num(vtd_as->bus), vtd_as->= devfn, + &ce); + if (ret) { + return ret; + } + + return vtd_ce_get_pasid_entry(s, &ce, pe, pasid); +} + +static bool vtd_pasid_entry_compare(VTDPASIDEntry *p1, VTDPASIDEntry *p2) +{ + return !memcmp(p1, p2, sizeof(*p1)); +} + +/* + * This function is a loop function which return value determines if + * vtd_as including cached pasid entry is removed. + * + * For PCI_NO_PASID, when corresponding cached pasid entry is cleared, + * it returns false so that vtd_as is reserved as it's owned by PCI + * sub-system. For other pasid, it returns true so vtd_as is removed. + */ +static gboolean vtd_flush_pasid_locked(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPASIDCacheInfo *pc_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + VTDPASIDEntry pe; + uint16_t did; + uint32_t pasid; + int ret; + + if (!pc_entry->valid) { + return false; + } + did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + goto remove; + } + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + if (pc_info->pasid !=3D pasid) { + return false; + } + /* fall through */ + case VTD_PASID_CACHE_DOMSI: + if (pc_info->did !=3D did) { + return false; + } + /* fall through */ + case VTD_PASID_CACHE_GLOBAL_INV: + break; + default: + error_setg(&error_fatal, "invalid pc_info->type for flush"); + } + + /* + * pasid cache invalidation may indicate a present pasid entry to pres= ent + * pasid entry modification. To cover such case, vIOMMU emulator needs= to + * fetch latest guest pasid entry and compares with cached pasid entry, + * then update pasid cache. + */ + ret =3D vtd_dev_get_pe_from_pasid(vtd_as, pasid, &pe); + if (ret) { + /* + * No valid pasid entry in guest memory. e.g. pasid entry was modi= fied + * to be either all-zero or non-present. Either case means existing + * pasid cache should be removed. + */ + goto remove; + } + + /* + * Update cached pasid entry if it's stale compared to what's in guest + * memory. + */ + if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { + pc_entry->pasid_entry =3D pe; + } + return false; + +remove: + pc_entry->valid =3D false; + + /* + * Don't remove address space of PCI_NO_PASID which is created for PCI + * sub-system. + */ + if (vtd_as->pasid =3D=3D PCI_NO_PASID) { + return false; + } + return true; +} + +/* + * For a PASID cache invalidation, this function handles below scenarios: + * a) a present cached pasid entry needs to be removed + * b) a present cached pasid entry needs to be updated + */ +static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) +{ + if (!s->flts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + vtd_iommu_lock(s); + /* + * a,b): loop all the existing vtd_as instances for pasid cache removal + or update. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, vtd_flush_pasid_loc= ked, + pc_info); + vtd_iommu_unlock(s); +} + +static bool vtd_process_pasid_desc(IntelIOMMUState *s, + VTDInvDesc *inv_desc) +{ + uint16_t did; + uint32_t pasid; + VTDPASIDCacheInfo pc_info; + uint64_t mask[4] =3D {VTD_INV_DESC_PASIDC_RSVD_VAL0, VTD_INV_DESC_ALL_= ONE, + VTD_INV_DESC_ALL_ONE, VTD_INV_DESC_ALL_ONE}; + + if (!vtd_inv_desc_reserved_check(s, inv_desc, mask, true, + __func__, "pasid cache inv")) { + return false; + } + + did =3D VTD_INV_DESC_PASIDC_DID(inv_desc); + pasid =3D VTD_INV_DESC_PASIDC_PASID(inv_desc); + + switch (VTD_INV_DESC_PASIDC_G(inv_desc)) { + case VTD_INV_DESC_PASIDC_G_DSI: + trace_vtd_pasid_cache_dsi(did); + pc_info.type =3D VTD_PASID_CACHE_DOMSI; + pc_info.did =3D did; + break; + + case VTD_INV_DESC_PASIDC_G_PASID_SI: + /* PASID selective implies a DID selective */ + trace_vtd_pasid_cache_psi(did, pasid); + pc_info.type =3D VTD_PASID_CACHE_PASIDSI; + pc_info.did =3D did; + pc_info.pasid =3D pasid; + break; + + case VTD_INV_DESC_PASIDC_G_GLOBAL: + trace_vtd_pasid_cache_gsi(); + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + break; + + default: + error_report_once("invalid granularity field in PASID-cache invali= date " + "descriptor, hi: 0x%"PRIx64" lo: 0x%" PRIx64, + inv_desc->val[1], inv_desc->val[0]); + return false; + } + + vtd_pasid_cache_sync(s, &pc_info); + return true; +} + static bool vtd_process_inv_iec_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { @@ -3274,6 +3451,13 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 + case VTD_INV_DESC_PC: + trace_vtd_inv_desc("pasid-cache", inv_desc.val[1], inv_desc.val[0]= ); + if (!vtd_process_pasid_desc(s, &inv_desc)) { + return false; + } + break; + case VTD_INV_DESC_PIOTLB: trace_vtd_inv_desc("p-iotlb", inv_desc.val[1], inv_desc.val[0]); if (!vtd_process_piotlb_desc(s, &inv_desc)) { @@ -3309,16 +3493,6 @@ static bool vtd_process_inv_desc(IntelIOMMUState *s) } break; =20 - /* - * TODO: the entity of below two cases will be implemented in future s= eries. - * To make guest (which integrates scalable mode support patch set in - * iommu driver) work, just return true is enough so far. - */ - case VTD_INV_DESC_PC: - if (s->scalable_mode) { - break; - } - /* fallthrough */ default: error_report_once("%s: invalid inv desc: hi=3D%"PRIx64", lo=3D%"PR= Ix64 " (unknown type)", __func__, inv_desc.hi, diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ac9e1a10aa..ae5bbfcdc0 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,9 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_gsi(void) "" +vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 +vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755844978; cv=none; d=zohomail.com; s=zohoarc; b=lTKPaJ2mUCqYVzFSzhaJIdrvak4ZpOM/jOdNzAwpiJVmoAfjIrN3CRqcrE2wj71BhYWVYFnVrJ7abbb2u8dG/A4TMG13H1QehS5jqEvqDjS3+Xsik95ZOyC8RblcMZuCcRKd7xrhauIougJTmOMRTqpmA9G3txcsvegCkPEkp08= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755844978; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qxvaVfejPozv7z16wgC9Q+2eTaVyr3yfYs3tgzNn8Pc=; b=eGvNmwpPG2YpJP3c1xnfq4ltnGdXOrz/co+l2dcrNDwznhExKRMp4A3sdCBnvUzbw47n9GYmnKUYvnOcdTGgOmEW/VmNGwoqiZPYYykQB5YfMxFREIpaT580+n7sMk/7H4b8XJRFlr3eUr3//km5T3rtCHp5oCJxwxT+NBJCHos= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755844978719529.0959942126403; Thu, 21 Aug 2025 23:42:58 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTh-00086w-0M; Fri, 22 Aug 2025 02:42:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTf-000868-7D for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:19 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTY-0000lZ-Jc for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:18 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:12 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:08 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844933; x=1787380933; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=LfrC8XPlME7rgvU2pHuZGqdNFskAahIu0MKI2S1IxLI=; b=F4l9cWBYrmisqjNzkSfIRwG6vB1X+Is+s3IXu5LN7R/f9109WUL3hMXo tWLjzpL3QoizYkOMgQCZeWhG5lBksXUqB4rVf+JFvgJkjj/ucM7h8KA6x R8U8bnOC0jYGhqgXamsYGrpqOeV+PyKrU1ikpajJpSPweKmFX/glP0t9X /Dsap5lksGPez20fdmhC0vvQLSk1ZEgw91XpYa+w4CMeuDyG63Emw5xH+ 8rGYO6HQuIfAWG1lxCPkR1/X/T6WpyFQLqrzXip2uZjr+G49t8hvwouIf 1m6AtQjxHFpfqpHbn1l6NQZuH/SMWfhcP0wi4Tm12JYbq9QwV+sgoC8DU w==; X-CSE-ConnectionGUID: HB5ULAiUT/OYpJrAWtOpaw== X-CSE-MsgGUID: kbzOGE41ToG/zDulqOZunw== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851928" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851928" X-CSE-ConnectionGUID: Qy/kPDBJR0ic7iVxKEfJbQ== X-CSE-MsgGUID: TYECliqyTc6KKlsYSEvPBA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168244996" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v5 12/21] intel_iommu: Handle PASID entry addition Date: Fri, 22 Aug 2025 02:40:50 -0400 Message-ID: <20250822064101.123526-13-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755844981949116600 Content-Type: text/plain; charset="utf-8" When guest creates new PASID entries, QEMU will capture the guest pasid selective pasid cache invalidation, walk through each passthrough device and each pasid, when a match is found, identify an existing vtd_as or create a new one and update its corresponding cached pasid entry. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 + hw/i386/intel_iommu.c | 176 ++++++++++++++++++++++++++++++++- 2 files changed, 175 insertions(+), 3 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index b9b76dd996..fb2a919e87 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -559,6 +559,7 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_CTX_ENTRY_LEGACY_SIZE 16 #define VTD_CTX_ENTRY_SCALABLE_SIZE 32 =20 +#define VTD_SM_CONTEXT_ENTRY_PDTS(x) extract64((x)->val[0], 9, 3) #define VTD_SM_CONTEXT_ENTRY_RID2PASID_MASK 0xfffff #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL @@ -589,6 +590,7 @@ typedef struct VTDPASIDCacheInfo { #define VTD_PASID_TABLE_BITS_MASK (0x3fULL) #define VTD_PASID_TABLE_INDEX(pasid) ((pasid) & VTD_PASID_TABLE_BITS_MASK) #define VTD_PASID_ENTRY_FPD (1ULL << 1) /* Fault Processing Disa= ble */ +#define VTD_PASID_TBL_ENTRY_NUM (1ULL << 6) =20 /* PASID Granular Translation Type Mask */ #define VTD_PASID_ENTRY_P 1ULL diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a2ee6d684e..7d2c9feae7 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -826,6 +826,11 @@ static inline bool vtd_pe_type_check(IntelIOMMUState *= s, VTDPASIDEntry *pe) } } =20 +static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTDContextEntry *ce) +{ + return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; @@ -1647,9 +1652,9 @@ static gboolean vtd_find_as_by_sid_and_iommu_pasid(gp= ointer key, gpointer value, } =20 /* Translate iommu pasid to vtd_as */ -static inline -VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, - uint16_t sid, uint32_t pas= id) +static VTDAddressSpace *vtd_as_from_iommu_pasid_locked(IntelIOMMUState *s, + uint16_t sid, + uint32_t pasid) { struct vtd_as_raw_key key =3D { .sid =3D sid, @@ -3220,10 +3225,172 @@ remove: return true; } =20 +/* + * This function walks over PASID range within [start, end) in a single + * PASID table for entries matching @info type/did, then retrieve/create + * vtd_as and fill associated pasid entry cache. + */ +static void vtd_sm_pasid_table_walk_one(IntelIOMMUState *s, + dma_addr_t pt_base, + int start, + int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDEntry pe; + int pasid =3D start; + + while (pasid < end) { + if (!vtd_get_pe_in_pasid_leaf_table(s, pasid, pt_base, &pe) + && vtd_pe_present(&pe)) { + int bus_n =3D pci_bus_num(info->bus), devfn =3D info->devfn; + uint16_t sid =3D PCI_BUILD_BDF(bus_n, devfn); + VTDPASIDCacheEntry *pc_entry; + VTDAddressSpace *vtd_as; + + vtd_iommu_lock(s); + /* + * When indexed by rid2pasid, vtd_as should have been created, + * e.g., by PCI subsystem. For other iommu pasid, we need to + * create vtd_as dynamically. Other iommu pasid is same value + * as PCI's pasid, so it's used as input of vtd_find_add_as(). + */ + vtd_as =3D vtd_as_from_iommu_pasid_locked(s, sid, pasid); + vtd_iommu_unlock(s); + if (!vtd_as) { + vtd_as =3D vtd_find_add_as(s, info->bus, devfn, pasid); + } + + if ((info->type =3D=3D VTD_PASID_CACHE_DOMSI || + info->type =3D=3D VTD_PASID_CACHE_PASIDSI) && + (info->did !=3D VTD_SM_PASID_ENTRY_DID(&pe))) { + /* + * VTD_PASID_CACHE_DOMSI and VTD_PASID_CACHE_PASIDSI + * requires domain id check. If domain id check fail, + * go to next pasid. + */ + pasid++; + continue; + } + + pc_entry =3D &vtd_as->pasid_cache_entry; + /* + * pasid cache update and clear are handled in + * vtd_flush_pasid_locked(), only care new pasid entry here. + */ + if (!pc_entry->valid) { + pc_entry->pasid_entry =3D pe; + pc_entry->valid =3D true; + } + } + pasid++; + } +} + +/* + * In VT-d scalable mode translation, PASID dir + PASID table is used. + * This function aims at looping over a range of PASIDs in the given + * two level table to identify the pasid config in guest. + */ +static void vtd_sm_pasid_table_walk(IntelIOMMUState *s, + dma_addr_t pdt_base, + int start, int end, + VTDPASIDCacheInfo *info) +{ + VTDPASIDDirEntry pdire; + int pasid =3D start; + int pasid_next; + dma_addr_t pt_base; + + while (pasid < end) { + pasid_next =3D + (pasid + VTD_PASID_TBL_ENTRY_NUM) & ~(VTD_PASID_TBL_ENTRY_NUM= - 1); + pasid_next =3D pasid_next < end ? pasid_next : end; + + if (!vtd_get_pdire_from_pdir_table(pdt_base, pasid, &pdire) + && vtd_pdire_present(&pdire)) { + pt_base =3D pdire.val & VTD_PASID_TABLE_BASE_ADDR_MASK; + vtd_sm_pasid_table_walk_one(s, pt_base, pasid, pasid_next, inf= o); + } + pasid =3D pasid_next; + } +} + +static void vtd_replay_pasid_bind_for_dev(IntelIOMMUState *s, + int start, int end, + VTDPASIDCacheInfo *info) +{ + VTDContextEntry ce; + + if (!vtd_dev_to_context_entry(s, pci_bus_num(info->bus), info->devfn, + &ce)) { + uint32_t max_pasid; + + max_pasid =3D vtd_sm_ce_get_pdt_entry_num(&ce) * VTD_PASID_TBL_ENT= RY_NUM; + if (end > max_pasid) { + end =3D max_pasid; + } + vtd_sm_pasid_table_walk(s, + VTD_CE_GET_PASID_DIR_TABLE(&ce), + start, + end, + info); + } +} + +/* + * This function replays the guest pasid bindings by walking the two level + * guest PASID table. For each valid pasid entry, it finds or creates a + * vtd_as and caches pasid entry in vtd_as. + */ +static void vtd_replay_guest_pasid_bindings(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info) +{ + /* + * Currently only Requests-without-PASID is supported, as vIOMMU doesn= 't + * support RPS(RID-PASID Support), pasid scope is fixed to [0, 1). + */ + int start =3D 0, end =3D 1; + VTDHostIOMMUDevice *vtd_hiod; + VTDPASIDCacheInfo walk_info; + GHashTableIter as_it; + + switch (pc_info->type) { + case VTD_PASID_CACHE_PASIDSI: + start =3D pc_info->pasid; + end =3D pc_info->pasid + 1; + /* fall through */ + case VTD_PASID_CACHE_DOMSI: + case VTD_PASID_CACHE_GLOBAL_INV: + /* loop all assigned devices */ + break; + default: + error_setg(&error_fatal, "invalid pc_info->type for replay"); + } + + /* + * In this replay, one only needs to care about the devices which are + * backed by host IOMMU. Those devices have a corresponding vtd_hiod + * in s->vtd_host_iommu_dev. For devices not backed by host IOMMU, it + * is not necessary to replay the bindings since their cache could be + * re-created in the future DMA address translation. + * + * VTD translation callback never accesses vtd_hiod and its correspond= ing + * cached pasid entry, so no iommu lock needed here. + */ + walk_info =3D *pc_info; + g_hash_table_iter_init(&as_it, s->vtd_host_iommu_dev); + while (g_hash_table_iter_next(&as_it, NULL, (void **)&vtd_hiod)) { + walk_info.bus =3D vtd_hiod->bus; + walk_info.devfn =3D vtd_hiod->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + } +} + /* * For a PASID cache invalidation, this function handles below scenarios: * a) a present cached pasid entry needs to be removed * b) a present cached pasid entry needs to be updated + * c) a present cached pasid entry needs to be created */ static void vtd_pasid_cache_sync(IntelIOMMUState *s, VTDPASIDCacheInfo *pc= _info) { @@ -3239,6 +3406,9 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s, = VTDPASIDCacheInfo *pc_info) g_hash_table_foreach_remove(s->vtd_address_spaces, vtd_flush_pasid_loc= ked, pc_info); vtd_iommu_unlock(s); + + /* c): loop all passthrough device for new pasid entries */ + vtd_replay_guest_pasid_bindings(s, pc_info); } =20 static bool vtd_process_pasid_desc(IntelIOMMUState *s, --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845177; cv=none; d=zohomail.com; s=zohoarc; b=g4YqCHPZlaod6RkCGgfZFTIn9zivmH+q2rabnKxpepF+NLBtx6KpWapj4cTDM0hdVkLjmRMv/O6FBVFgMi3Fs8Mw/mx+XuzHB9BZ1G0IeTpP2ZmQZT3T+b1UIA4DUnzoIDYH0cRyGidPvQq/np8NoJXrH5xF1oYITf+nKk6Muk4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845177; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=j2qBb5SMeIf/ua7R4CfKXta7IlExaUbViVhYI4Sj2Jc=; b=Ai+q0NDEuJoeUAhYXl/Qn3OK/yB+UPY9wXytUforW0ie8/xbNI2AlkqUOa4CZI21CTSh543IsOFF7+zCNGAWHW/svSJUHpLL/+VCJxwOR9xd3bfW++wNmQx9c73YX+UV+60Co4nrG4JNfff/VRgv1F75l/DoV91Xo9M4PSkCgXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175584517780913.605185025200285; Thu, 21 Aug 2025 23:46:17 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTi-00087F-8J; Fri, 22 Aug 2025 02:42:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTf-00086a-Sh for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:19 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTd-0000ms-OX for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:19 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:16 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:12 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844938; x=1787380938; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=TjcSiYOFGErYkuxb0F+W0qo6CJQ3SHvdw/xJfxSWw98=; b=iD3iJ5jkaIt7fSwZ5qsQ6hnk4AjqOlttQJ4dG8HCod7rp8R9pH0DgiVr WJCnJfVcGYByv6cI2rHdTgMEMFwdK7ETa6j3OkwnFLleJ4v8cth/QTXNs ks8ndWmBjlSokqP7vm5mXuZoPzF1iLa9NbzlHGEXN+nahpcr+bh2cRakU 1WyJBnDETRC7kiuRE1KWrvizCqXExDm7W5WeIbcbJRKbqjGPkC30AM+sC dBfL8LPJyPS1d3FNEnLyTzfyr8jTjilE7gvC29ZkBi01tTRIpe4u6CIW+ j88vjqnIMc4PzsHKJcdVUfrAL7ORf02QcL33IivjZM9kSrClzgg/1DiYY A==; X-CSE-ConnectionGUID: /jEegJDhSwqGEymf3PzPhg== X-CSE-MsgGUID: 5HuzbMUETj6hBLlf5WHnfg== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851940" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851940" X-CSE-ConnectionGUID: xd8bp4wJSweM5w25WxofWw== X-CSE-MsgGUID: D7bfccMFQDa4QnouymoD1Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245020" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v5 13/21] intel_iommu: Introduce a new pasid cache invalidation type FORCE_RESET Date: Fri, 22 Aug 2025 02:40:51 -0400 Message-ID: <20250822064101.123526-14-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845179114116600 Content-Type: text/plain; charset="utf-8" FORCE_RESET is different from GLOBAL_INV which updates pasid cache if underlying pasid entry is still valid, it drops all the pasid caches. FORCE_RESET isn't a VTD spec defined invalidation type for pasid cache, only used internally in system level reset. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 9 +++++++++ hw/i386/intel_iommu.c | 25 +++++++++++++++++++++++++ hw/i386/trace-events | 1 + 3 files changed, 35 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index fb2a919e87..c510b09d1a 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -569,6 +569,15 @@ typedef enum VTDPCInvType { VTD_PASID_CACHE_DOMSI =3D VTD_INV_DESC_PASIDC_G_DSI, VTD_PASID_CACHE_PASIDSI =3D VTD_INV_DESC_PASIDC_G_PASID_SI, VTD_PASID_CACHE_GLOBAL_INV =3D VTD_INV_DESC_PASIDC_G_GLOBAL, + + /* + * Internally used PASID cache invalidation type starts here, + * 0x10 is large enough as invalidation type in pc_inv_desc + * is 2bits in size. + */ + + /* Reset all PASID cache entries, used in system level reset */ + VTD_PASID_CACHE_FORCE_RESET =3D 0x10, } VTDPCInvType; =20 typedef struct VTDPASIDCacheInfo { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7d2c9feae7..af384ce7f0 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -87,6 +87,8 @@ struct vtd_iotlb_key { static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); + static void vtd_panic_require_caching_mode(void) { error_report("We need to set caching-mode=3Don for intel-iommu to enab= le " @@ -391,6 +393,7 @@ static void vtd_reset_caches(IntelIOMMUState *s) vtd_iommu_lock(s); vtd_reset_iotlb_locked(s); vtd_reset_context_cache_locked(s); + vtd_pasid_cache_reset_locked(s); vtd_iommu_unlock(s); } =20 @@ -3183,6 +3186,8 @@ static gboolean vtd_flush_pasid_locked(gpointer key, = gpointer value, /* fall through */ case VTD_PASID_CACHE_GLOBAL_INV: break; + case VTD_PASID_CACHE_FORCE_RESET: + goto remove; default: error_setg(&error_fatal, "invalid pc_info->type for flush"); } @@ -3225,6 +3230,23 @@ remove: return true; } =20 +static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info; + + trace_vtd_pasid_cache_reset(); + + pc_info.type =3D VTD_PASID_CACHE_FORCE_RESET; + + /* + * Reset pasid cache is a big hammer, so use g_hash_table_foreach_remo= ve + * which will free all vtd_as instances except those created for PCI + * sub-system. + */ + g_hash_table_foreach_remove(s->vtd_address_spaces, + vtd_flush_pasid_locked, &pc_info); +} + /* * This function walks over PASID range within [start, end) in a single * PASID table for entries matching @info type/did, then retrieve/create @@ -3363,6 +3385,9 @@ static void vtd_replay_guest_pasid_bindings(IntelIOMM= UState *s, case VTD_PASID_CACHE_GLOBAL_INV: /* loop all assigned devices */ break; + case VTD_PASID_CACHE_FORCE_RESET: + /* For force reset, no need to go further replay */ + return; default: error_setg(&error_fatal, "invalid pc_info->type for replay"); } diff --git a/hw/i386/trace-events b/hw/i386/trace-events index ae5bbfcdc0..c8a936eb46 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -24,6 +24,7 @@ vtd_inv_qi_head(uint16_t head) "read head %d" vtd_inv_qi_tail(uint16_t head) "write tail %d" vtd_inv_qi_fetch(void) "" vtd_context_cache_reset(void) "" +vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845012; cv=none; d=zohomail.com; s=zohoarc; b=FFpDmADnNvtk+JV6Fwrye9v0Fh1M8/qClCbC4CioHtOcY2Id6rfeXhUM8KDnFtXObY0iZKOUo2tkYiPwzgrwf5GjLWlV7tSz/5/XfMCNsgvuzx4rTcVj9RuMrj8HB6GMTzBfjKlgGERUEdeXzLIFC0q/l8jZecJAiIye6Bw8yV4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845012; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=qpBAXyVvr5ThY/tBN3DSPUipjLCcScF+SfqU3EdQlv4=; b=gS4TsXz0gr/b2CicS380qOxTgjjQxoeAtsu5o3QiG6ln+B+yP6D/c1fvq5C+yoyczY7dOaD0BfkzSJYZrTi/F9mdSWQWXX0kPkO4IFnjdB8lwuV/G2myRYF0YE0HPyBvl+Hqxc3NgZhNSUjPFKmL+hICEwNiO2RUjGY2btBhTCM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845012566466.71056240676023; Thu, 21 Aug 2025 23:43:32 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTk-000888-Ng; Fri, 22 Aug 2025 02:42:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTj-00087X-Ff for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:23 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTh-0000nA-Ij for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:23 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:20 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:16 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844941; x=1787380941; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CM4/rc33HVYVP7f5qjK7i+zLcSyCBlsoXm/qLpfCczE=; b=VbbrcLbZe8Smq7XmG4M0BQtcivML6gtvOY/f+KsYRX1h7/0mQV22WW75 o2shUAN1B3yzR75al3jXLOstI4Xmv4++8uyVecXfPzUT/BBHSUUeRYKSZ hk7396dciDE1GTQ0sMiv4ZDq4/hgKIaQCKyF1OTNFrEloygFwnTcmd6Jm 7Wdh/+aPxPxS3aqeTgviIXpfWV6nboCEwe/zxpwSv1TIqc3QgJoRvqKOo irhzqxFqAKoB0g4tNhGWY765463Jf9TnPeP7c8U92sr4en1qqMkfikLYE J3qb2oCu4FwCnv0TA08VH5/PDIAs4KHmQPc7UZsuKTLIjFJum34HmCgE7 g==; X-CSE-ConnectionGUID: lYXMjY33RBCOuOp7RKD8lg== X-CSE-MsgGUID: Ky3q7c0fQAa6stVhFu0YZg== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851946" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851946" X-CSE-ConnectionGUID: 3/J8RsnqQ5e/ZTFNX5tsNg== X-CSE-MsgGUID: Xvsde5IEQn2MBhDdWf6T7w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245026" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 14/21] intel_iommu: Stick to system MR for IOMMUFD backed host device when x-fls=on Date: Fri, 22 Aug 2025 02:40:52 -0400 Message-ID: <20250822064101.123526-15-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845013737116600 Content-Type: text/plain; charset="utf-8" When guest in scalable mode and x-flts=3Don, we stick to system MR for IOMM= UFD backed host device. Then its default hwpt contains GPA->HPA mappings which = is used directly if PGTT=3DPT and used as nested parent if PGTT=3DFLT. Otherwi= se fallback to original processing. Suggested-by: Yi Liu Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index af384ce7f0..15582977b8 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -1773,6 +1773,28 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, V= TDContextEntry *ce, =20 } =20 +static VTDHostIOMMUDevice *vtd_find_hiod_iommufd(IntelIOMMUState *s, + VTDAddressSpace *as) +{ + struct vtd_as_key key =3D { + .bus =3D as->bus, + .devfn =3D as->devfn, + }; + VTDHostIOMMUDevice *vtd_hiod =3D g_hash_table_lookup(s->vtd_host_iommu= _dev, + &key); + + if (vtd_hiod && vtd_hiod->hiod && + object_dynamic_cast(OBJECT(vtd_hiod->hiod), + TYPE_HOST_IOMMU_DEVICE_IOMMUFD)) { + return vtd_hiod; + } + return NULL; +} + +/* + * vtd_switch_address_space() calls vtd_as_pt_enabled() to determine which + * MR to switch to. Switch to system MR if return true, iommu MR otherwise. + */ static bool vtd_as_pt_enabled(VTDAddressSpace *as) { IntelIOMMUState *s; @@ -1781,6 +1803,18 @@ static bool vtd_as_pt_enabled(VTDAddressSpace *as) assert(as); =20 s =3D as->iommu_state; + + /* + * When guest in scalable mode and x-flts=3Don, we stick to system MR + * for IOMMUFD backed host device. Then its default hwpt contains + * GPA->HPA mappings which is used directly if PGTT=3DPT and used as + * nested parent if PGTT=3DFLT. Otherwise fallback to original + * processing. + */ + if (s->root_scalable && s->flts && vtd_find_hiod_iommufd(s, as)) { + return true; + } + if (vtd_dev_to_context_entry(s, pci_bus_num(as->bus), as->devfn, &ce)) { /* --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845065; cv=none; d=zohomail.com; s=zohoarc; b=RKuIMe4TaggCAYHvYsGPbnd9hmW/JyNqBdfBv3+Hvszh/fqCP3198e8i+jvC/OD4zP5zeAGF6oG+1weQ/LhIP1JttyVhv1AOCSsFr/VxYU+D8+gdCYYWuRCACGnLPwDW+U/TblazZkZcGJJ1f24Gs9l3IsoJy5yfzygU3gNv8/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845065; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=gnkNcJ2a1L6ZIYJvnGaBiG8Tu26ChLKbi2DVeXg5dx4=; b=BPDibGg7LzGCZgTxplTenpleWwVcM3X8eIM4gmxFG5GsibewBIDTivzO5MKb2BJISTQnLDBkzq76qw1vf9P+DwW4R/Pw70op0ZeM1A2qeWrgBS0eGy49e3he8Catu571rZXgeSuTHE3WlX8eKoT2cJRPaPMSOe/D8msoMrFKUqQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845065639138.98254239314542; Thu, 21 Aug 2025 23:44:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLTr-0008Iv-9d; Fri, 22 Aug 2025 02:42:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTo-0008HH-UZ for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:29 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTk-0000nA-VH for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:28 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:24 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:20 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844945; x=1787380945; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E2k9IesyLrRoiWHNFAi3+P635Y5FqMq/Tb/iQoZtYy4=; b=OcrHTHkkSFN+k3UebKnx5zNX1EhJueun6aot7qzEwz7nR/52tcGpmSCm qdvc0a54i+jgNn9NAYgswFFT88tIMJCJ2PEgYwSopUGoW6lwyI5enIsgW PRz1OGoLmsjY5fgu6HI1MjOIH++q1UsNe4LdAfIxh3immW3O46XTtr5jh JTV09dnar0gyxMEZ5OzAIxOGV674U6sDF12BCQ1HAv7MXKeN/fH3iBH7k CemAVmFSkqnIouqLGJgzl0HdjgdsmML9trDd35hKyD+bK+iv60EP4FKLf cpykYeXeoMQ3usM/b1+Sy0tuOI936QWP1KHMmlEBYjFSU+uhJJ5E+AB3W A==; X-CSE-ConnectionGUID: d/ye2EWfQqm0FCYUQMNMHg== X-CSE-MsgGUID: Xb9hwYqjQgC0WSO/4lexPw== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851955" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851955" X-CSE-ConnectionGUID: gWU9wkm+Tw2d+Kljscz0lA== X-CSE-MsgGUID: KEX0tdopQoatwmlyc72jpQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245035" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan , Yi Sun Subject: [PATCH v5 15/21] intel_iommu: Bind/unbind guest page table to host Date: Fri, 22 Aug 2025 02:40:53 -0400 Message-ID: <20250822064101.123526-16-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845066235116600 Content-Type: text/plain; charset="utf-8" This captures the guest PASID table entry modifications and propagates the changes to host to attach a hwpt with type determined per guest IOMMU mode and PGTT configuration. When PGTT is Pass-through(100b), the hwpt on host side is a stage-2 page table(GPA->HPA). When PGTT is First-stage Translation only(001b), vIOMMU reuse hwpt(GPA->HPA) provided by VFIO as nested parent to construct nested page table. When guest decides to use legacy mode then vIOMMU switches the MRs of the device's AS, hence the IOAS created by VFIO container would be switched to using the IOMMU_NOTIFIER_IOTLB_EVENTS since the MR is switched to IOMMU MR. So it is able to support shadowing the guest IO page table. Co-Authored-by: Yi Liu Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 14 ++- include/hw/i386/intel_iommu.h | 1 + hw/i386/intel_iommu.c | 221 ++++++++++++++++++++++++++++++++- hw/i386/trace-events | 3 + 4 files changed, 233 insertions(+), 6 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index c510b09d1a..61e35dbdc0 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -564,6 +564,12 @@ typedef struct VTDRootEntry VTDRootEntry; #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL0(aw) (0x1e0ULL | ~VTD_HAW_MASK(aw)) #define VTD_SM_CONTEXT_ENTRY_RSVD_VAL1 0xffffffffffe00000ULL =20 +typedef enum VTDPASIDOp { + VTD_PASID_BIND, + VTD_PASID_UPDATE, + VTD_PASID_UNBIND, +} VTDPASIDOp; + typedef enum VTDPCInvType { /* VTD spec defined PASID cache invalidation type */ VTD_PASID_CACHE_DOMSI =3D VTD_INV_DESC_PASIDC_G_DSI, @@ -612,8 +618,12 @@ typedef struct VTDPASIDCacheInfo { #define VTD_SM_PASID_ENTRY_AW 7ULL /* Adjusted guest-address-widt= h */ #define VTD_SM_PASID_ENTRY_DID(x) extract64((x)->val[1], 0, 16) =20 -#define VTD_SM_PASID_ENTRY_FLPM 3ULL -#define VTD_SM_PASID_ENTRY_FLPTPTR (~0xfffULL) +#define VTD_SM_PASID_ENTRY_FSPTPTR (~0xfffULL) +#define VTD_SM_PASID_ENTRY_SRE_BIT(x) extract64((x)->val[2], 0, 1) +/* 00: 4-level paging, 01: 5-level paging, 10-11: Reserved */ +#define VTD_SM_PASID_ENTRY_FSPM(x) extract64((x)->val[2], 2, 2) +#define VTD_SM_PASID_ENTRY_WPE_BIT(x) extract64((x)->val[2], 4, 1) +#define VTD_SM_PASID_ENTRY_EAFE_BIT(x) extract64((x)->val[2], 7, 1) =20 /* First Level Paging Structure */ /* Masks for First Level Paging Entry */ diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 0e3826f6f0..2affab36b2 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -104,6 +104,7 @@ struct VTDAddressSpace { PCIBus *bus; uint8_t devfn; uint32_t pasid; + uint32_t s1_hwpt; AddressSpace as; IOMMUMemoryRegion iommu; MemoryRegion root; /* The root container of the device */ diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 15582977b8..a10ee8eb4f 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -20,6 +20,7 @@ */ =20 #include "qemu/osdep.h" +#include CONFIG_DEVICES /* CONFIG_IOMMUFD */ #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qapi/error.h" @@ -41,6 +42,9 @@ #include "migration/vmstate.h" #include "trace.h" #include "system/iommufd.h" +#ifdef CONFIG_IOMMUFD +#include +#endif =20 /* context entry operations */ #define VTD_CE_GET_RID2PASID(ce) \ @@ -50,10 +54,9 @@ =20 /* pe operations */ #define VTD_PE_GET_TYPE(pe) ((pe)->val[0] & VTD_SM_PASID_ENTRY_PGTT) -#define VTD_PE_GET_FL_LEVEL(pe) \ - (4 + (((pe)->val[2] >> 2) & VTD_SM_PASID_ENTRY_FLPM)) #define VTD_PE_GET_SL_LEVEL(pe) \ (2 + (((pe)->val[0] >> 2) & VTD_SM_PASID_ENTRY_AW)) +#define VTD_PE_GET_FL_LEVEL(pe) (VTD_SM_PASID_ENTRY_FSPM(pe) + 4) =20 /* * PCI bus number (or SID) is not reliable since the device is usaully @@ -834,6 +837,31 @@ static inline uint32_t vtd_sm_ce_get_pdt_entry_num(VTD= ContextEntry *ce) return 1U << (VTD_SM_CONTEXT_ENTRY_PDTS(ce) + 7); } =20 +static inline dma_addr_t vtd_pe_get_flpt_base(VTDPASIDEntry *pe) +{ + return pe->val[2] & VTD_SM_PASID_ENTRY_FSPTPTR; +} + +/* + * Stage-1 IOVA address width: 48 bits for 4-level paging(FSPM=3D00) + * 57 bits for 5-level paging(FSPM=3D01) + */ +static inline uint32_t vtd_pe_get_fl_aw(VTDPASIDEntry *pe) +{ + return 48 + VTD_SM_PASID_ENTRY_FSPM(pe) * 9; +} + +static inline bool vtd_pe_pgtt_is_pt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_PT); +} + +/* check if pgtt is first stage translation */ +static inline bool vtd_pe_pgtt_is_flt(VTDPASIDEntry *pe) +{ + return (VTD_PE_GET_TYPE(pe) =3D=3D VTD_SM_PASID_ENTRY_FLT); +} + static inline bool vtd_pdire_present(VTDPASIDDirEntry *pdire) { return pdire->val & 1; @@ -1131,7 +1159,7 @@ static dma_addr_t vtd_get_iova_pgtbl_base(IntelIOMMUS= tate *s, if (s->root_scalable) { vtd_ce_get_pasid_entry(s, ce, &pe, pasid); if (s->flts) { - return pe.val[2] & VTD_SM_PASID_ENTRY_FLPTPTR; + return pe.val[2] & VTD_SM_PASID_ENTRY_FSPTPTR; } else { return pe.val[0] & VTD_SM_PASID_ENTRY_SLPTPTR; } @@ -1766,7 +1794,7 @@ static bool vtd_dev_pt_enabled(IntelIOMMUState *s, VT= DContextEntry *ce, */ return false; } - return (VTD_PE_GET_TYPE(&pe) =3D=3D VTD_SM_PASID_ENTRY_PT); + return vtd_pe_pgtt_is_pt(&pe); } =20 return (vtd_ce_get_type(ce) =3D=3D VTD_CONTEXT_TT_PASS_THROUGH); @@ -2433,6 +2461,178 @@ static void vtd_context_global_invalidate(IntelIOMM= UState *s) vtd_iommu_replay_all(s); } =20 +#ifdef CONFIG_IOMMUFD +static void vtd_init_s1_hwpt_data(struct iommu_hwpt_vtd_s1 *vtd, + VTDPASIDEntry *pe) +{ + memset(vtd, 0, sizeof(*vtd)); + + vtd->flags =3D (VTD_SM_PASID_ENTRY_SRE_BIT(pe) ? IOMMU_VTD_S1_SRE : 0= ) | + (VTD_SM_PASID_ENTRY_WPE_BIT(pe) ? IOMMU_VTD_S1_WPE : 0) | + (VTD_SM_PASID_ENTRY_EAFE_BIT(pe) ? IOMMU_VTD_S1_EAFE : 0= ); + vtd->addr_width =3D vtd_pe_get_fl_aw(pe); + vtd->pgtbl_addr =3D (uint64_t)vtd_pe_get_flpt_base(pe); +} + +static int vtd_create_s1_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDPASIDEntry *pe, uint32_t *s1_hwpt, + Error **errp) +{ + struct iommu_hwpt_vtd_s1 vtd; + + vtd_init_s1_hwpt_data(&vtd, pe); + + return !iommufd_backend_alloc_hwpt(idev->iommufd, idev->devid, + idev->hwpt_id, 0, IOMMU_HWPT_DATA_V= TD_S1, + sizeof(vtd), &vtd, s1_hwpt, errp); +} + +static void vtd_destroy_s1_hwpt(HostIOMMUDeviceIOMMUFD *idev, + VTDAddressSpace *vtd_as) +{ + if (!vtd_as->s1_hwpt) { + return; + } + iommufd_backend_free_id(idev->iommufd, vtd_as->s1_hwpt); + vtd_as->s1_hwpt =3D 0; +} + +static int vtd_device_attach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + VTDPASIDEntry *pe =3D &vtd_as->pasid_cache_entry.pasid_entry; + uint32_t hwpt_id; + int ret; + + /* + * We can get here only if flts=3Don, the supported PGTT is FLT and PT. + * Catch invalid PGTT when processing invalidation request to avoid + * attaching to wrong hwpt. + */ + if (!vtd_pe_pgtt_is_flt(pe) && !vtd_pe_pgtt_is_pt(pe)) { + error_setg(errp, "Invalid PGTT type"); + return -EINVAL; + } + + if (vtd_pe_pgtt_is_flt(pe)) { + /* Should fail if the FLPT base is 0 */ + if (!vtd_pe_get_flpt_base(pe)) { + error_setg(errp, "FLPT base is 0"); + return -EINVAL; + } + + if (vtd_create_s1_hwpt(idev, pe, &hwpt_id, errp)) { + return -EINVAL; + } + } else { + hwpt_id =3D idev->hwpt_id; + } + + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, hwpt_id, errp); + trace_vtd_device_attach_hwpt(idev->devid, vtd_as->pasid, hwpt_id, ret); + if (!ret) { + vtd_destroy_s1_hwpt(idev, vtd_as); + if (vtd_pe_pgtt_is_flt(pe)) { + vtd_as->s1_hwpt =3D hwpt_id; + } + } else if (vtd_pe_pgtt_is_flt(pe)) { + iommufd_backend_free_id(idev->iommufd, hwpt_id); + } + + return ret; +} + +static int vtd_device_detach_iommufd(VTDHostIOMMUDevice *vtd_hiod, + VTDAddressSpace *vtd_as, Error **errp) +{ + HostIOMMUDeviceIOMMUFD *idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->h= iod); + uint32_t pasid =3D vtd_as->pasid; + int ret; + + if (vtd_hiod->iommu_state->dmar_enabled) { + ret =3D !host_iommu_device_iommufd_detach_hwpt(idev, errp); + trace_vtd_device_detach_hwpt(idev->devid, pasid, ret); + } else { + ret =3D !host_iommu_device_iommufd_attach_hwpt(idev, idev->hwpt_id= , errp); + trace_vtd_device_reattach_def_hwpt(idev->devid, pasid, idev->hwpt_= id, + ret); + } + + if (!ret) { + vtd_destroy_s1_hwpt(idev, vtd_as); + } + + return ret; +} + +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op, + Error **errp) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(s, vtd_as); + int ret; + + if (!vtd_hiod) { + /* No need to go further, e.g. for emulated device */ + return 0; + } + + if (vtd_as->pasid !=3D PCI_NO_PASID) { + error_setg(errp, "Non-rid_pasid %d not supported yet", vtd_as->pas= id); + return -EINVAL; + } + + switch (op) { + case VTD_PASID_UPDATE: + case VTD_PASID_BIND: + { + ret =3D vtd_device_attach_iommufd(vtd_hiod, vtd_as, errp); + break; + } + case VTD_PASID_UNBIND: + { + ret =3D vtd_device_detach_iommufd(vtd_hiod, vtd_as, errp); + break; + } + default: + error_setg(errp, "Unknown VTDPASIDOp!!!"); + break; + } + + return ret; +} +#else +static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op, + Error **errp) +{ + return 0; +} +#endif + +static int vtd_bind_guest_pasid_report_err(VTDAddressSpace *vtd_as, + VTDPASIDOp op) +{ + Error *local_err =3D NULL; + int ret; + + /* + * vIOMMU calls into kernel to do BIND/UNBIND, the failure reason + * can be kernel, QEMU bug or invalid guest config. None of them + * should be reported to guest in PASID cache invalidation + * processing path. But at least, we can report it to QEMU console. + * + * TODO: for invalid guest config, DMA translation fault will be + * caught by host and passed to QEMU to inject to guest in future. + */ + ret =3D vtd_bind_guest_pasid(vtd_as, op, &local_err); + if (ret) { + error_report_err(local_err); + } + + return ret; +} + /* Do a context-cache device-selective invalidation. * @func_mask: FM field after shifting */ @@ -3248,10 +3448,20 @@ static gboolean vtd_flush_pasid_locked(gpointer key= , gpointer value, */ if (!vtd_pasid_entry_compare(&pe, &pc_entry->pasid_entry)) { pc_entry->pasid_entry =3D pe; + if (vtd_bind_guest_pasid_report_err(vtd_as, VTD_PASID_UPDATE)) { + /* + * In case update binding fails, tear down existing binding to + * catch invalid pasid entry config during DMA translation. + */ + goto remove; + } } return false; =20 remove: + if (vtd_bind_guest_pasid_report_err(vtd_as, VTD_PASID_UNBIND)) { + return false; + } pc_entry->valid =3D false; =20 /* @@ -3336,6 +3546,9 @@ static void vtd_sm_pasid_table_walk_one(IntelIOMMUSta= te *s, if (!pc_entry->valid) { pc_entry->pasid_entry =3D pe; pc_entry->valid =3D true; + if (vtd_bind_guest_pasid_report_err(vtd_as, VTD_PASID_BIND= )) { + pc_entry->valid =3D false; + } } } pasid++; diff --git a/hw/i386/trace-events b/hw/i386/trace-events index c8a936eb46..1c31b9a873 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -73,6 +73,9 @@ vtd_warn_invalid_qi_tail(uint16_t tail) "tail 0x%"PRIx16 vtd_warn_ir_vector(uint16_t sid, int index, int vec, int target) "sid 0x%"= PRIx16" index %d vec %d (should be: %d)" vtd_warn_ir_trigger(uint16_t sid, int index, int trig, int target) "sid 0x= %"PRIx16" index %d trigger %d (should be: %d)" vtd_reset_exit(void) "" +vtd_device_attach_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwpt_id, = int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" +vtd_device_detach_hwpt(uint32_t dev_id, uint32_t pasid, int ret) "dev_id %= d pasid %d ret: %d" +vtd_device_reattach_def_hwpt(uint32_t dev_id, uint32_t pasid, uint32_t hwp= t_id, int ret) "dev_id %d pasid %d hwpt_id %d, ret: %d" =20 # amd_iommu.c amdvi_evntlog_fail(uint64_t addr, uint32_t head) "error: fail to write at = addr 0x%"PRIx64" + offset 0x%"PRIx32 --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755844982; cv=none; d=zohomail.com; s=zohoarc; b=ks1vWgTGe3aY3SaHsdInxlLP9UYYC6MVWSq7+ykjkSzBfQdMhUBKCM9VG3jUMqr52nRd2uEM0/CF9W8V7AU1WxJejGJwaxL/I5Y8o0jFPqBYeWnguduyKmHlRmz/C01w/8Ql6yEc0CdV2auun+bw45TD1vgfSCftFCbEZ/mZB/Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755844982; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=RYIIw5DUYyAycIV2TeIQ5qf8JzNpYuID/sGcWqGxseY=; b=B9vdr2sYKpwkqV9lyn3pllhT8msnoqu7XbzE1Erw8jFUcNpHlINGwkuNapx5DG87roPlbECW/i23UDlHnfVhzx5uIVEGMQlj5XQsvXG0Wb223g2OdZfotVLI9Kkxnrz1P5zMnd1Xie7KPTQbE1eciJj2G5QAxl7MjpPizdpQPzQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755844982458553.4783202205831; Thu, 21 Aug 2025 23:43:02 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLUC-0000ge-N8; Fri, 22 Aug 2025 02:42:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLU8-0000Ry-Hi for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:48 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLTz-0000nA-Df for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:47 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:28 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:24 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844959; x=1787380959; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=R/ULxv/UtpGeLbXYBtcgxCGmuswd03BDnnhqDFNvkBo=; b=eOjNnL6NIsfEHEYFvrEd5hDiHUVetXxFdYnoofP5vctobCO6lNe5a9qs /MnJT+Hwb4Td+M+ma1KZalm5bEeI6E/AcjPOSUsRoxjjl/SyC+tpWVuGb yNFw/mjhz8TfchV9mTCe5rbWRdvJPD+6OqYoVMjrgCA/JYFb2DAIy/OHp 14D9MgdQYffBxx1j7Zi5+scsb2LIHlyKjpX6BZg8c4vEZcoe972IHdsok YKghEnmNzm4Zu742myJ2inkst6VRMb8GaPtNy8O6JILwHu0yY+MFbVTtv y63qEey6YTtE7ee3bxZRyDCriNCj9h+jNnd4qay/SDevoyeBZElP/3pUH Q==; X-CSE-ConnectionGUID: CVgdAnhDT9KDYYVit+Pv0Q== X-CSE-MsgGUID: 17Ga26mrQA6IuQD+IyyuVg== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851961" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851961" X-CSE-ConnectionGUID: pmph73UrTyKZCDeHRNEMAw== X-CSE-MsgGUID: tjkQLvGWTiiaSmhi5yA64g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245050" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan Subject: [PATCH v5 16/21] intel_iommu: Replay pasid bindings after context cache invalidation Date: Fri, 22 Aug 2025 02:40:54 -0400 Message-ID: <20250822064101.123526-17-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755844983112116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This replays guest pasid bindings after context cache invalidation. This is a behavior to ensure safety. Actually, programmer should issue pasid cache invalidation with proper granularity after issuing a context cache invalidation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 2 ++ hw/i386/intel_iommu.c | 42 ++++++++++++++++++++++++++++++++++ hw/i386/trace-events | 1 + 3 files changed, 45 insertions(+) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 61e35dbdc0..8af1004888 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -584,6 +584,8 @@ typedef enum VTDPCInvType { =20 /* Reset all PASID cache entries, used in system level reset */ VTD_PASID_CACHE_FORCE_RESET =3D 0x10, + /* Invalidate all PASID entries in a device */ + VTD_PASID_CACHE_DEVSI, } VTDPCInvType; =20 typedef struct VTDPASIDCacheInfo { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index a10ee8eb4f..6c0e502d1c 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -91,6 +91,10 @@ static void vtd_address_space_refresh_all(IntelIOMMUStat= e *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); +static void vtd_pasid_cache_sync(IntelIOMMUState *s, + VTDPASIDCacheInfo *pc_info); +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn); =20 static void vtd_panic_require_caching_mode(void) { @@ -2442,6 +2446,8 @@ static void vtd_iommu_replay_all(IntelIOMMUState *s) =20 static void vtd_context_global_invalidate(IntelIOMMUState *s) { + VTDPASIDCacheInfo pc_info; + trace_vtd_inv_desc_cc_global(); /* Protects context cache */ vtd_iommu_lock(s); @@ -2459,6 +2465,9 @@ static void vtd_context_global_invalidate(IntelIOMMUS= tate *s) * VT-d emulation codes. */ vtd_iommu_replay_all(s); + + pc_info.type =3D VTD_PASID_CACHE_GLOBAL_INV; + vtd_pasid_cache_sync(s, &pc_info); } =20 #ifdef CONFIG_IOMMUFD @@ -2691,6 +2700,15 @@ static void vtd_context_device_invalidate(IntelIOMMU= State *s, * happened. */ vtd_address_space_sync(vtd_as); + /* + * Per spec, context flush should also be followed with PASID + * cache and iotlb flush. In order to work with a guest which + * doesn't follow spec and missed PASID cache flush, we have + * vtd_pasid_cache_devsi() to invalidate PASID caches of the + * passthrough device. Host iommu driver would flush piotlb + * when a pasid unbind is pass down to it. + */ + vtd_pasid_cache_devsi(s, vtd_as->bus, devfn); } } } @@ -3422,6 +3440,11 @@ static gboolean vtd_flush_pasid_locked(gpointer key,= gpointer value, break; case VTD_PASID_CACHE_FORCE_RESET: goto remove; + case VTD_PASID_CACHE_DEVSI: + if (pc_info->bus !=3D vtd_as->bus || pc_info->devfn !=3D vtd_as->d= evfn) { + return false; + } + break; default: error_setg(&error_fatal, "invalid pc_info->type for flush"); } @@ -3635,6 +3658,11 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, case VTD_PASID_CACHE_FORCE_RESET: /* For force reset, no need to go further replay */ return; + case VTD_PASID_CACHE_DEVSI: + walk_info.bus =3D pc_info->bus; + walk_info.devfn =3D pc_info->devfn; + vtd_replay_pasid_bind_for_dev(s, start, end, &walk_info); + return; default: error_setg(&error_fatal, "invalid pc_info->type for replay"); } @@ -3683,6 +3711,20 @@ static void vtd_pasid_cache_sync(IntelIOMMUState *s,= VTDPASIDCacheInfo *pc_info) vtd_replay_guest_pasid_bindings(s, pc_info); } =20 +static void vtd_pasid_cache_devsi(IntelIOMMUState *s, + PCIBus *bus, uint16_t devfn) +{ + VTDPASIDCacheInfo pc_info; + + trace_vtd_pasid_cache_devsi(devfn); + + pc_info.type =3D VTD_PASID_CACHE_DEVSI; + pc_info.bus =3D bus; + pc_info.devfn =3D devfn; + + vtd_pasid_cache_sync(s, &pc_info); +} + static bool vtd_process_pasid_desc(IntelIOMMUState *s, VTDInvDesc *inv_desc) { diff --git a/hw/i386/trace-events b/hw/i386/trace-events index 1c31b9a873..830b11f68b 100644 --- a/hw/i386/trace-events +++ b/hw/i386/trace-events @@ -28,6 +28,7 @@ vtd_pasid_cache_reset(void) "" vtd_pasid_cache_gsi(void) "" vtd_pasid_cache_dsi(uint16_t domain) "Domain selective PC invalidation dom= ain 0x%"PRIx16 vtd_pasid_cache_psi(uint16_t domain, uint32_t pasid) "PASID selective PC i= nvalidation domain 0x%"PRIx16" pasid 0x%"PRIx32 +vtd_pasid_cache_devsi(uint16_t devfn) "Dev selective PC invalidation dev: = 0x%"PRIx16 vtd_re_not_present(uint8_t bus) "Root entry bus %"PRIu8" not present" vtd_ce_not_present(uint8_t bus, uint8_t devfn) "Context entry bus %"PRIu8"= devfn %"PRIu8" not present" vtd_iotlb_page_hit(uint16_t sid, uint64_t addr, uint64_t slpte, uint16_t d= omain) "IOTLB page hit sid 0x%"PRIx16" iova 0x%"PRIx64" slpte 0x%"PRIx64" d= omain 0x%"PRIx16 --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845083; cv=none; d=zohomail.com; s=zohoarc; b=TaNWZVc5dDmpq8QmvMLQ9FJIR5v0vnhZtWJyxkKqCKBu5heGOYm3PqD4biQ/e4pEgBuwHtTaX+/xLv+xTiES3cI9RJog26H1B4HL1/YQ+BED27nFhYoQPP2pQzGgfUyUpybqCiw2rDI7ZtXYpfXrL+F34ovFqYwlEu+S2ldnzlY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845083; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=BZZnxVQPt5Yg4zLo3k+oINjB5ykA+nEdS2kpNpnFwKk=; b=HdBqrCTvQ0k1Z7Q+ZbjSiEXzuIzmca8LVFvu9CBFyLvTeiGzddtAaucIsSV1HMIj1mkE6PQ1HikOKByvJO2sn4qM/r++QnWM21LkXajlCTBCko379Mqop2GPl3/UhrxR1IuBanr3iRz6JJ+wA+QHZ1BHVRjzu7qMgk8dFHNxCLo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845083572356.2877435169502; Thu, 21 Aug 2025 23:44:43 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLUA-0000ZG-4T; Fri, 22 Aug 2025 02:42:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLU7-0000Sx-Nm for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:47 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLU3-0000ng-PI for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:47 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:32 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:28 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844964; x=1787380964; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HcRsaorrxtQn6LTXs2bSotlAWLAHM+2B4HRRScXSLVM=; b=AE625uc7r+xlIwhduy0+S4I5ouwWMaPRND5ADs9KelZ1EL7J+2keMk+J ZEI17aG4Xg7Df74cp5JU72k1/ITYkqSea6kYCskXUb3w74+RXgLBTaAxM XqhFvxTgNBL80CurPtnfwQwUuuxPtY0ABfGNmfDigW92o/QKo68TE7fIc +AUjASl6o611/nToABBAKzifumPT8vqxUuBoVQwviqHYwPC8AJ6j/k0mz Wy7xfRMRlGSUrVIpeFNMx3yKxdAxF01POoWoeYcFUz+FnPSKWtTcNwy0E ooK8CHaKeS7Zw+g5SeTmXj/1AjRHxngm1qXJa5JQCJ7wFiTLX5vjtRo+7 w==; X-CSE-ConnectionGUID: z6+U6+amSCy2RVI34UcXPQ== X-CSE-MsgGUID: dKc9P3DPT4OI5495TI8SOw== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851968" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851968" X-CSE-ConnectionGUID: UEdekUykSl2MPAx8DIuIjA== X-CSE-MsgGUID: kRL6T4lpSMqj6eH3/keWTA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245061" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Yi Sun , Zhenzhong Duan Subject: [PATCH v5 17/21] intel_iommu: Propagate PASID-based iotlb invalidation to host Date: Fri, 22 Aug 2025 02:40:55 -0400 Message-ID: <20250822064101.123526-18-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845084359116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu This traps the guest PASID-based iotlb invalidation request and propagate it to host. Intel VT-d 3.0 supports nested translation in PASID granularity. Guest SVA support could be implemented by configuring nested translation on specific pasid. This is also known as dual stage DMA translation. Under such configuration, guest owns the GVA->GPA translation which is configured as stage-1 page table on host side for a specific pasid, and host owns GPA->HPA translation. As guest owns stage-1 translation table, piotlb invalidation should be propagated to host since host IOMMU will cache first level page table related mappings during DMA address translation. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu_internal.h | 6 +++ hw/i386/intel_iommu.c | 95 +++++++++++++++++++++++++++++++++- 2 files changed, 99 insertions(+), 2 deletions(-) diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h index 8af1004888..c1a9263651 100644 --- a/hw/i386/intel_iommu_internal.h +++ b/hw/i386/intel_iommu_internal.h @@ -596,6 +596,12 @@ typedef struct VTDPASIDCacheInfo { uint16_t devfn; } VTDPASIDCacheInfo; =20 +typedef struct VTDPIOTLBInvInfo { + uint16_t domain_id; + uint32_t pasid; + struct iommu_hwpt_vtd_s1_invalidate *inv_data; +} VTDPIOTLBInvInfo; + /* PASID Table Related Definitions */ #define VTD_PASID_DIR_BASE_ADDR_MASK (~0xfffULL) #define VTD_PASID_TABLE_BASE_ADDR_MASK (~0xfffULL) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6c0e502d1c..7efa22f4ec 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -2611,12 +2611,99 @@ static int vtd_bind_guest_pasid(VTDAddressSpace *vt= d_as, VTDPASIDOp op, =20 return ret; } + +static void +vtd_invalidate_piotlb_locked(VTDAddressSpace *vtd_as, + struct iommu_hwpt_vtd_s1_invalidate *cache) +{ + IntelIOMMUState *s =3D vtd_as->iommu_state; + VTDHostIOMMUDevice *vtd_hiod =3D vtd_find_hiod_iommufd(s, vtd_as); + HostIOMMUDeviceIOMMUFD *idev; + uint32_t entry_num =3D 1; /* Only implement one request for simplicity= */ + Error *local_err =3D NULL; + + if (!vtd_hiod || !vtd_as->s1_hwpt) { + return; + } + idev =3D HOST_IOMMU_DEVICE_IOMMUFD(vtd_hiod->hiod); + + if (!iommufd_backend_invalidate_cache(idev->iommufd, vtd_as->s1_hwpt, + IOMMU_HWPT_INVALIDATE_DATA_VTD_S= 1, + sizeof(*cache), &entry_num, cach= e, + &local_err)) { + /* Something wrong in kernel, but trying to continue */ + error_report_err(local_err); + } +} + +/* + * This function is a loop function for the s->vtd_address_spaces + * list with VTDPIOTLBInvInfo as execution filter. It propagates + * the piotlb invalidation to host. + */ +static void vtd_flush_host_piotlb_locked(gpointer key, gpointer value, + gpointer user_data) +{ + VTDPIOTLBInvInfo *piotlb_info =3D user_data; + VTDAddressSpace *vtd_as =3D value; + VTDPASIDCacheEntry *pc_entry =3D &vtd_as->pasid_cache_entry; + uint32_t pasid; + uint16_t did; + + /* Replay only fills pasid entry cache for passthrough device */ + if (!pc_entry->valid || + !vtd_pe_pgtt_is_flt(&pc_entry->pasid_entry)) { + return; + } + + if (vtd_as_to_iommu_pasid_locked(vtd_as, &pasid)) { + return; + } + + did =3D VTD_SM_PASID_ENTRY_DID(&pc_entry->pasid_entry); + + if (piotlb_info->domain_id =3D=3D did && piotlb_info->pasid =3D=3D pas= id) { + vtd_invalidate_piotlb_locked(vtd_as, piotlb_info->inv_data); + } +} + +static void +vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool ih) +{ + struct iommu_hwpt_vtd_s1_invalidate cache_info =3D { 0 }; + VTDPIOTLBInvInfo piotlb_info; + + cache_info.addr =3D addr; + cache_info.npages =3D npages; + cache_info.flags =3D ih ? IOMMU_VTD_INV_FLAGS_LEAF : 0; + + piotlb_info.domain_id =3D domain_id; + piotlb_info.pasid =3D pasid; + piotlb_info.inv_data =3D &cache_info; + + /* + * Go through each vtd_as instance in s->vtd_address_spaces, find out + * the affected host device which need host piotlb invalidation. Piotlb + * invalidation should check pasid cache per architecture point of vie= w. + */ + g_hash_table_foreach(s->vtd_address_spaces, + vtd_flush_host_piotlb_locked, &piotlb_info); +} #else static int vtd_bind_guest_pasid(VTDAddressSpace *vtd_as, VTDPASIDOp op, Error **errp) { return 0; } + +static void +vtd_flush_host_piotlb_all_locked(IntelIOMMUState *s, + uint16_t domain_id, uint32_t pasid, + hwaddr addr, uint64_t npages, bool ih) +{ +} #endif =20 static int vtd_bind_guest_pasid_report_err(VTDAddressSpace *vtd_as, @@ -3295,6 +3382,7 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_pasid, &info); + vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, 0, (uint64_t)-1,= 0); vtd_iommu_unlock(s); =20 QLIST_FOREACH(vtd_as, &s->vtd_as_with_notifiers, next) { @@ -3316,7 +3404,8 @@ static void vtd_piotlb_pasid_invalidate(IntelIOMMUSta= te *s, } =20 static void vtd_piotlb_page_invalidate(IntelIOMMUState *s, uint16_t domain= _id, - uint32_t pasid, hwaddr addr, uint8_= t am) + uint32_t pasid, hwaddr addr, uint8_= t am, + bool ih) { VTDIOTLBPageInvInfo info; =20 @@ -3328,6 +3417,7 @@ static void vtd_piotlb_page_invalidate(IntelIOMMUStat= e *s, uint16_t domain_id, vtd_iommu_lock(s); g_hash_table_foreach_remove(s->iotlb, vtd_hash_remove_by_page_piotlb, &info); + vtd_flush_host_piotlb_all_locked(s, domain_id, pasid, addr, 1 << am, i= h); vtd_iommu_unlock(s); =20 vtd_iotlb_page_invalidate_notify(s, domain_id, addr, am, pasid); @@ -3359,7 +3449,8 @@ static bool vtd_process_piotlb_desc(IntelIOMMUState *= s, case VTD_INV_DESC_PIOTLB_PSI_IN_PASID: am =3D VTD_INV_DESC_PIOTLB_AM(inv_desc->val[1]); addr =3D (hwaddr) VTD_INV_DESC_PIOTLB_ADDR(inv_desc->val[1]); - vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am); + vtd_piotlb_page_invalidate(s, domain_id, pasid, addr, am, + VTD_INV_DESC_PIOTLB_IH(inv_desc->val[1]= )); break; =20 default: --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845135; cv=none; d=zohomail.com; s=zohoarc; b=g7bUeBV0yHDy7/1FFNIw3Hz/IQyxV0mRSrCAqvJBNDnYuu1yOeiWRIL3TV4Su1wFkJC6trW4q7qRvfQZkdwxGx2yJk+zp+i+Rn1emsanLc143DU+MLon9FdDtOKn/nYpgAu7RdMk5W92xCZWfsDJBxnfDd8Ox1fkNn3FvUWXT68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845135; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=2eDSY+Si1d1e7slZvdO7USHWohdv6EWvb3H/wiPjrIQ=; b=FF5pWsAKAlXjbGrAD/N9UMoXig/3cGT5PJ4X89nklkE5AXpv9DvFgSiPx/e5vViqY48BMx4zbY5VFftaoTGTZn4vKAeWNB/Ha1yAN3aTfg/0PJlve/HPl1acmz0/z0nZJpOaYi9J1lbaL+zHUJt6ZlkKkdwLmB0uBwisfy90hCA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845135100743.5056211081433; Thu, 21 Aug 2025 23:45:35 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLUW-0001Ur-U5; Fri, 22 Aug 2025 02:43:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLUC-0000kN-OZ for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:53 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLU9-0000o0-6R for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:52 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:36 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:33 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844969; x=1787380969; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YGc1ym5GP8K6lgnpnL4SI6a+DyLbM5yHs1cSu2dhHcs=; b=W0Mi7i+Vtq4Byy/ITElDB6mnhmHH3cSXAqt4e2yzMxPFedqtLhYYRijE Trh01QewA32p41H5AqQno3NpT/wo2N+fjjTO56l8gmRl0j1/ofaVlaq9O g2T5CXLNVwPSw1XIgWKl1n3RXDdzmy0RAkLQibUsbA4EYGO/lt8ttaS6n Fo4GjUlHOSeqAc8ACfJ+oOK8EoZErduNPq61wPkmkA67jPmYHQfrRoB7f fV3Ssd41yzRl1ZkhKTkdcrMjbAo6ajB8z17QzHAaXwhy0acsjA1Q5Jpcy 0X4M6TrkRlvts5M4+zuEBPWvK3lQK6SliKpw8ghcaCKkYGqsdy0QsSNPJ Q==; X-CSE-ConnectionGUID: ZnxlVBHTRLK2/hGjR62PEA== X-CSE-MsgGUID: Pn4cGPOqQpeyMshgDkLZ4w== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851980" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851980" X-CSE-ConnectionGUID: 179WktfvR1KACe8cLm7UAg== X-CSE-MsgGUID: smPXZzKXR9ahJ2RzuOLUxg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245078" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 18/21] intel_iommu: Replay all pasid bindings when either SRTP or TE bit is changed Date: Fri, 22 Aug 2025 02:40:56 -0400 Message-ID: <20250822064101.123526-19-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845136784116600 Content-Type: text/plain; charset="utf-8" From: Yi Liu When either 'Set Root Table Pointer' or 'Translation Enable' bit is changed, all pasid bindings on host side become stale and need to be updated. Introduce a helper function vtd_replay_pasid_bindings_all() to go through a= ll pasid entries in all passthrough devices to update host side bindings. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger --- hw/i386/intel_iommu.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 7efa22f4ec..f9cb13e945 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -89,6 +89,7 @@ struct vtd_iotlb_key { =20 static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); +static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s); =20 static void vtd_pasid_cache_reset_locked(IntelIOMMUState *s); static void vtd_pasid_cache_sync(IntelIOMMUState *s, @@ -3050,6 +3051,7 @@ static void vtd_handle_gcmd_srtp(IntelIOMMUState *s) vtd_set_clear_mask_long(s, DMAR_GSTS_REG, 0, VTD_GSTS_RTPS); vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_replay_pasid_bindings_all(s); } =20 /* Set Interrupt Remap Table Pointer */ @@ -3084,6 +3086,7 @@ static void vtd_handle_gcmd_te(IntelIOMMUState *s, bo= ol en) =20 vtd_reset_caches(s); vtd_address_space_refresh_all(s); + vtd_replay_pasid_bindings_all(s); } =20 /* Handle Interrupt Remap Enable/Disable */ @@ -3777,6 +3780,17 @@ static void vtd_replay_guest_pasid_bindings(IntelIOM= MUState *s, } } =20 +static void vtd_replay_pasid_bindings_all(IntelIOMMUState *s) +{ + VTDPASIDCacheInfo pc_info =3D { .type =3D VTD_PASID_CACHE_GLOBAL_INV }; + + if (!s->flts || !s->root_scalable || !s->dmar_enabled) { + return; + } + + vtd_replay_guest_pasid_bindings(s, &pc_info); +} + /* * For a PASID cache invalidation, this function handles below scenarios: * a) a present cached pasid entry needs to be removed --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845019; cv=none; d=zohomail.com; s=zohoarc; b=TKRqlHhgczODQ733CejOaubuIMQBFnCMHN98m1cWT1eQDrflOeZLNcLN5Pllp2NpOJX9eAMGuV0NTHqGQQJyzlA1/0Xnbay6HRPd6da/nbHKdVtCB3feGLcN+FG2jFKyEUGLZIMKLvOG2bbpJydeN0KCWr5vw+0fGC3IWJB4rPw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845019; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=w3HymMPJ2q8F50lS7g6BuNjLs7Tu9m9RbiJwt/ICOZ0=; b=Hw/FwKuAOVMx4riM4DKY3LWQlJj2nM7NJXujSAB3v5sW2mzCBrpZa/lfGH1nzKLM/NltUjgUIF8hdrWoKKKd5XyY5xEfQZXbwfc0xw37DtWwf47eNhGfAhorNdSSJqHbLd2UPu70FT84lgGda2+qWd8sOopYd06MLzTINavc4Gw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845019432584.2548574421979; Thu, 21 Aug 2025 23:43:39 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLUJ-00019H-FR; Fri, 22 Aug 2025 02:42:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLUA-0000dv-Mn for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:50 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLU8-0000ng-9m for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:42:50 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:40 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:37 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844968; x=1787380968; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mUU9OMMJ/1zTbxE4IweHoAT8lJKpLVKsUXa0W5k5u1I=; b=iUB6lacKUJ+As4cF37Yy2kXOV1HfFCbU2HNlhW+u3uZ418KR5JXnLdZe IgqeeLcFblna+4lAwAH3eiSbdM9vHttpwP3soTiuXXHekOsnSGWM5U6/0 RMnTdl8192P23/xrPqWwquICBYMpGSoQMpjkRO+8rwdf1VoRq241+W4DH WuXQOLjZoG1EJ0XZGYtmTmnmdNXRvM9KNlmP8QOokcw62eDIlP35EiYc2 1Ev+V9ZPjJGcf4XUWv9qhsEw1la3irh2qhEXqMmxDQfhj90iOzGmcYiWy w6IMQauNo8N7adi1j1OsD7SsdN5EaExQcK3w9GZIQm4aI3tzj2zKo3mwh A==; X-CSE-ConnectionGUID: I5CCE4pKRoqNpcOxD1YQrQ== X-CSE-MsgGUID: GJ7xhqbKRa+0fRKDA0G8Og== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851987" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851987" X-CSE-ConnectionGUID: rd1+3vbjTl6RIjUoQMs/Wg== X-CSE-MsgGUID: ED41qg/dQH2J2sF6wCdOeA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245093" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 19/21] vfio: Add a new element bypass_ro in VFIOContainerBase Date: Fri, 22 Aug 2025 02:40:57 -0400 Message-ID: <20250822064101.123526-20-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845021945124100 Content-Type: text/plain; charset="utf-8" When bypass_ro is true, readonly memory section is bypassed from mapping in the container. This is a preparing patch to workaround Intel ERRATA_772415. Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-container-base.h | 1 + hw/vfio/listener.c | 21 ++++++++++++++------- 2 files changed, 15 insertions(+), 7 deletions(-) diff --git a/include/hw/vfio/vfio-container-base.h b/include/hw/vfio/vfio-c= ontainer-base.h index bded6e993f..31fd784d76 100644 --- a/include/hw/vfio/vfio-container-base.h +++ b/include/hw/vfio/vfio-container-base.h @@ -51,6 +51,7 @@ typedef struct VFIOContainerBase { QLIST_HEAD(, VFIODevice) device_list; GList *iova_ranges; NotifierWithReturn cpr_reboot_notifier; + bool bypass_ro; } VFIOContainerBase; =20 typedef struct VFIOGuestIOMMU { diff --git a/hw/vfio/listener.c b/hw/vfio/listener.c index 903dfd8bf2..5fa2bb7f1a 100644 --- a/hw/vfio/listener.c +++ b/hw/vfio/listener.c @@ -76,8 +76,13 @@ static bool vfio_log_sync_needed(const VFIOContainerBase= *bcontainer) return true; } =20 -static bool vfio_listener_skipped_section(MemoryRegionSection *section) +static bool vfio_listener_skipped_section(MemoryRegionSection *section, + bool bypass_ro) { + if (bypass_ro && section->readonly) { + return true; + } + return (!memory_region_is_ram(section->mr) && !memory_region_is_iommu(section->mr)) || memory_region_is_protected(section->mr) || @@ -365,9 +370,9 @@ static bool vfio_known_safe_misalignment(MemoryRegionSe= ction *section) } =20 static bool vfio_listener_valid_section(MemoryRegionSection *section, - const char *name) + bool bypass_ro, const char *name) { - if (vfio_listener_skipped_section(section)) { + if (vfio_listener_skipped_section(section, bypass_ro)) { trace_vfio_listener_region_skip(name, section->offset_within_address_space, section->offset_within_address_space + @@ -494,7 +499,8 @@ void vfio_container_region_add(VFIOContainerBase *bcont= ainer, int ret; Error *err =3D NULL; =20 - if (!vfio_listener_valid_section(section, "region_add")) { + if (!vfio_listener_valid_section(section, bcontainer->bypass_ro, + "region_add")) { return; } =20 @@ -655,7 +661,8 @@ static void vfio_listener_region_del(MemoryListener *li= stener, int ret; bool try_unmap =3D true; =20 - if (!vfio_listener_valid_section(section, "region_del")) { + if (!vfio_listener_valid_section(section, bcontainer->bypass_ro, + "region_del")) { return; } =20 @@ -812,7 +819,7 @@ static void vfio_dirty_tracking_update(MemoryListener *= listener, container_of(listener, VFIODirtyRangesListener, listener); hwaddr iova, end; =20 - if (!vfio_listener_valid_section(section, "tracking_update") || + if (!vfio_listener_valid_section(section, false, "tracking_update") || !vfio_get_section_iova_range(dirty->bcontainer, section, &iova, &end, NULL)) { return; @@ -1206,7 +1213,7 @@ static void vfio_listener_log_sync(MemoryListener *li= stener, int ret; Error *local_err =3D NULL; =20 - if (vfio_listener_skipped_section(section)) { + if (vfio_listener_skipped_section(section, false)) { return; } =20 --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845035; cv=none; d=zohomail.com; s=zohoarc; b=YI4yP0kJDIfgMVHY/I2rH47dUfrB/jVB+ECdYSbhy0Emg9v4SHO92IwObmigQ30gfLbX2ctUT6rQOpyjQY7iU4KNbAt7VRR9yF9bZX+ewWa4pp5gDnCYdyCJ3xV0cOFV4khT07e+Pghf0BBtPa47DcadNRuJcQp+OlkFRODuXCo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845035; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=QJw/qDyto9GLn+AsXfrqRgIJvIwQhCQMhDuHjiaDlPc=; b=OcMJmeiNcap5DHknjJMYPHCd1mbzY3rQireB7JzSDA4BTaGOJQsEIrm3knQbtT0mNjSM7OtuwsTQHdkesAEmsp9Q0+uJhrk3/CY4JGgDua8G33sOLFPXoxfFY8QTcvilWG+33dOogHf+mPF4f5ArtRTWbeErPZdXkLjpqii7Nd8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845035127770.5669655182473; Thu, 21 Aug 2025 23:43:55 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLUg-0001iq-MM; Fri, 22 Aug 2025 02:43:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLUM-0001QF-BV for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:43:02 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLUI-0000nA-DO for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:43:02 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:44 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:41 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844978; x=1787380978; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9a1YhvmlEOpMvs9x4Pr2A/KegPOPcR6QNiYdIJrtzkA=; b=JlIr8bQkV0UArgwHqgdTUBrlYm3bVnopktedsVyjq8tx8QU//DFJ6z+w 4Ks+R0mL4LMZxC6Nfq8UDTlWbmvcL04Lzy1Zg8vDuwrSzKfU+R5vRE60Z GYkX6hAPB3iBwUquKj8oZ5i/xoQv08X2F/XYHjZsh6T59SGCxMclywi0f +sHtxoLsUgwVfg/ZpAzneXv8PsCcgPzp82wi1QQ+n5ApEGbwaoYNAYXMU 2hCAd/M6Kv0RyG4jNwZOgss2y24WAop8bPGtw7xKQaTaXlQXRyX2xu5CR ob8Xh5UIZYh0Zt1ZmBqrECH9Bja1D3/sFtIFzIXYnTqKVVl1bVNWHdlXB g==; X-CSE-ConnectionGUID: zbs1qJ/hSNCb8ABM1eTX8g== X-CSE-MsgGUID: wCV8qFeLTgma+YYqW37psA== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68851997" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68851997" X-CSE-ConnectionGUID: vbTWbG2QTRu1vj+4Sxf4yA== X-CSE-MsgGUID: BiqBSZz6SYqLygEna18VSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245115" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 20/21] Workaround for ERRATA_772415_SPR17 Date: Fri, 22 Aug 2025 02:40:58 -0400 Message-ID: <20250822064101.123526-21-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845037950124100 Content-Type: text/plain; charset="utf-8" On a system influenced by ERRATA_772415, IOMMU_HW_INFO_VTD_ERRATA_772415_SP= R17 is repored by IOMMU_DEVICE_GET_HW_INFO. Due to this errata, even the readon= ly range mapped on stage-2 page table could still be written. Reference from 4th Gen Intel Xeon Processor Scalable Family Specification Update, Errata Details, SPR17. https://edc.intel.com/content/www/us/en/design/products-and-solutions/proce= ssors-and-chipsets/eagle-stream/sapphire-rapids-specification-update/ Also copied the SPR17 details from above link: "Problem: When remapping hardware is configured by system software in scalable mode as Nested (PGTT=3D011b) and with PWSNP field Set in the PASID-table-entry, it may Set Accessed bit and Dirty bit (and Extended Access bit if enabled) in first-stage page-table entries even when second-stage mappings indicate that corresponding first-stage page-table is Read-Only. Implication: Due to this erratum, pages mapped as Read-only in second-stage page-tables may be modified by remapping hardware Access/Dirty bit updates. Workaround: None identified. System software enabling nested translations for a VM should ensure that there are no read-only pages in the corresponding second-stage mappings." Signed-off-by: Zhenzhong Duan --- hw/vfio/iommufd.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/hw/vfio/iommufd.c b/hw/vfio/iommufd.c index e503c232e1..59735e878c 100644 --- a/hw/vfio/iommufd.c +++ b/hw/vfio/iommufd.c @@ -324,6 +324,7 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *vb= asedev, { ERRP_GUARD(); IOMMUFDBackend *iommufd =3D vbasedev->iommufd; + struct iommu_hw_info_vtd vtd; uint32_t type, flags =3D 0; uint64_t hw_caps; VFIOIOASHwpt *hwpt; @@ -371,10 +372,15 @@ static bool iommufd_cdev_autodomains_get(VFIODevice *= vbasedev, * instead. */ if (!iommufd_backend_get_device_info(vbasedev->iommufd, vbasedev->devi= d, - &type, NULL, 0, &hw_caps, errp)) { + &type, &vtd, sizeof(vtd), &hw_cap= s, + errp)) { return false; } =20 + if (vtd.flags & IOMMU_HW_INFO_VTD_ERRATA_772415_SPR17) { + container->bcontainer.bypass_ro =3D true; + } + if (hw_caps & IOMMU_HW_CAP_DIRTY_TRACKING) { flags =3D IOMMU_HWPT_ALLOC_DIRTY_TRACKING; } --=20 2.47.1 From nobody Sat Nov 15 03:13:41 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1755845084; cv=none; d=zohomail.com; s=zohoarc; b=bH9cjVLfYgVRC6q7dePzGm76psh7iMwnjanm2Gs+JROeAL5lDtXZLmWtxL8DlKaI+grW3uvgxM+yfIFSu5vt+0dNF/uMNavs06OTnyvpEdkWBQG/jgMcGzLy9Cp0Q8BAMUQf21lPL8WAe+NFWnp3GUawy1znVrFBeofMUIFDJY4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755845084; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=LHtCiJUPqS/3I3AfRDsPYT+22ajaadVCNm4AaP/L6BI=; b=e3nQYMmiCBiSwSudIwaaymaMgJuB6BwO+lcI3FRJYTKcqiq+Kqdv8HwctABsZKA/aS1AokpVTMHFlrEHQ0KpeAK4VDe5rhzf8QXS6YfUK5KFOfdpJ3dYpObce+XW52knc3HoXc3Mv6gb/wTuWVjf0VR8EbmF9iK1sqPPwz7MjvQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755845084889634.6876353587738; Thu, 21 Aug 2025 23:44:44 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1upLUl-00024e-CX; Fri, 22 Aug 2025 02:43:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLUU-0001fD-Mv for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:43:14 -0400 Received: from mgamail.intel.com ([192.198.163.9]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1upLUM-0000ng-JT for qemu-devel@nongnu.org; Fri, 22 Aug 2025 02:43:09 -0400 Received: from orviesa009.jf.intel.com ([10.64.159.149]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:48 -0700 Received: from unknown (HELO gnr-sp-2s-612.sh.intel.com) ([10.112.230.229]) by orviesa009-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Aug 2025 23:42:45 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1755844983; x=1787380983; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=/+84F15DZwB+iKxNYTViwNHHGJz87FSax8HKySO0EEA=; b=GJ7IIUx1USJjzR1ex5jIzD4nkrOFqAWNEwr9SP9FtjQm9dnMqMoA1B51 KSOkKeKlPzQF6nW83DbGA3cwHytxyDrKRQv7KUnIsdy+ZJik1rcNzUD/Z hT3t2IP5TIOeCWvzz91zvXYeF5zdSUg4B3r95SAN1V/ukvUysAY9v/2EV upDq6kskWmeb+0RcHHk+Z4GFYiFLKQycq4R9a38rJMDd3RHt5rg9jaZtA iuWYs22BCJx1UhR9zDuKPZNsBBvVB+7q7PZp+tiKuDkNmxUBBJFQOyeqc cIpCs7ltDVKe0aQPBAdz5z4tpFmhdZWamTffFgK0gWFmgc5gnUdm16ibO Q==; X-CSE-ConnectionGUID: 4Pcy55wVQhewsAi+3al6KA== X-CSE-MsgGUID: P/p9EN+sSty6Ymw27i8veQ== X-IronPort-AV: E=McAfee;i="6800,10657,11529"; a="68852007" X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="68852007" X-CSE-ConnectionGUID: rtqc+s3ETCGj8jtnSkozJA== X-CSE-MsgGUID: 9pZO+WIDQhuKLeQjahmDhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.17,309,1747724400"; d="scan'208";a="168245133" From: Zhenzhong Duan To: qemu-devel@nongnu.org Cc: alex.williamson@redhat.com, clg@redhat.com, eric.auger@redhat.com, mst@redhat.com, jasowang@redhat.com, peterx@redhat.com, ddutile@redhat.com, jgg@nvidia.com, nicolinc@nvidia.com, joao.m.martins@oracle.com, clement.mathieu--drif@eviden.com, kevin.tian@intel.com, yi.l.liu@intel.com, chao.p.peng@intel.com, Zhenzhong Duan Subject: [PATCH v5 21/21] intel_iommu: Enable host device when x-flts=on in scalable mode Date: Fri, 22 Aug 2025 02:40:59 -0400 Message-ID: <20250822064101.123526-22-zhenzhong.duan@intel.com> X-Mailer: git-send-email 2.47.1 In-Reply-To: <20250822064101.123526-1-zhenzhong.duan@intel.com> References: <20250822064101.123526-1-zhenzhong.duan@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.198.163.9; envelope-from=zhenzhong.duan@intel.com; helo=mgamail.intel.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1755845086144116600 Content-Type: text/plain; charset="utf-8" Now that all infrastructures of supporting passthrough device running with stage-1 translation are there, enable it now. Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Yi Liu --- hw/i386/intel_iommu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index f9cb13e945..04a412d460 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -5222,6 +5222,8 @@ static bool vtd_check_hiod(IntelIOMMUState *s, VTDHos= tIOMMUDevice *vtd_hiod, "when x-flts=3Don"); return false; } + + return true; #endif =20 error_setg(errp, "host IOMMU is incompatible with stage-1 translation"= ); --=20 2.47.1