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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v3 06/47] hw/arm/xlnx-versal: gem: refactor creation Date: Thu, 21 Aug 2025 15:03:05 +0200 Message-ID: <20250821130354.125971-7-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821130354.125971-1-luc.michel@amd.com> References: <20250821130354.125971-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F6:EE_|MW3PR12MB4459:EE_ X-MS-Office365-Filtering-Correlation-Id: 3798532c-ce37-4c10-c174-08dde0b34282 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?7j0bA5/6QBFRLRVdQP9oFguiw3JVrQYEJ4Eh8E+96xSLurtZV5MuHF40Hxwx?= =?us-ascii?Q?jgwpix95yVk0fZk7aXGwVDhEfumEX/+ff99kkxzn9xrMZGg++TyqJJ6rVsxW?= =?us-ascii?Q?8WRUaS+BoBCzJrRt60PosGmmUZ8thiMo3S41BR3y06wtfz6e1qGj4C9i3taa?= =?us-ascii?Q?mOPekOHR41X6G4ZMhQbpu4w08ygASYkE2MJxeRQhzAdawZzeNtaWGgP8QwMR?= =?us-ascii?Q?+GDy/drSHddDityROVzh/JdZ+fd5d01/CI8rTGHj0YxiVINaBUmui5UBVgfR?= =?us-ascii?Q?bnNgPt3SX2F/xW7KQzjrXYOWbK9/rfydmFQjX1WtXUWAL+E1D46VoOe1OwC0?= =?us-ascii?Q?ewOqBhP5uQRHkkXhFTKHNRgLQvUSE+smV9a2/IMgzecmBvCCCzKQUmRMsvOq?= =?us-ascii?Q?+KUANcfunEa4/flxTtj4ULuUq1trUnokWdR5011v5a8sACASQWYV7PHdZGbj?= =?us-ascii?Q?SfbhtadO5ElKjQEfBen5nMR6fB/gexZ3UpH+9B1Ho+e8MAv9wn8XcWnSSgRF?= =?us-ascii?Q?jjsUmhIzUWkM/A7MjqP9ZF//SNlm2dbD3LT4O0spAEl5yQBBj92YhWuryMJR?= =?us-ascii?Q?2BqTgof0Wuxpdf1UIWknGiV5bMPqocRdRmb3g1f+ndJek/6jyzYDV6qLZbB+?= =?us-ascii?Q?xu7s5SaA47AsV5xMG+D9eflMsZstjUegSolG/MXqUSiPMczwpASeChKZS8wd?= =?us-ascii?Q?yg472G4ToTQzKhuDM7WXeIdNzLXwcJdZ2uMUkocDhmGx0OAwDv7uJK/J4cDZ?= =?us-ascii?Q?eQkWHB/d/KFjiX7bwWB9e3iE+dPevpNfKqvJ9a0LZx49+ZHiq/8J/PEyMyeB?= =?us-ascii?Q?nBxoR+yDb2OOCEeVTgS3DgBZS5R8/b2t1VYocA+qUA7R0Ssb4WtjtI/qM06f?= =?us-ascii?Q?i3TmRUfNBmWLOQWoV9crXGhiFGE7Cf6MLrykd/MIHhYK/DejvlE4/Ppgpe10?= =?us-ascii?Q?YS0hMHCZdSWWHgV3gLJ/y59hdZBqkBazkpOs6+lv+V5j3RlNzbcC1K0Yw/IR?= =?us-ascii?Q?/MzJZ+u0MXNF6y/05zVXsomXXlq8vLWUWpombek7zpUNOLO1yU7StzIAVdWv?= =?us-ascii?Q?db/uxlqDAqFETUEOzdd7ZDZQU1KXW98JpCWHjgNYgjrSf13+uCeBqHln9xQd?= =?us-ascii?Q?QOeA/3ga/AmTBzoNqhXCduH3HOm+OvDeqC23qJl6ELuyV4Up5qO+kaOEOmeh?= =?us-ascii?Q?YBax0GPI4Kef0oVdXMOVM0WQ07B3WuK9PuxuDDWYi5GNWXpR0p+8NPwHTRtY?= =?us-ascii?Q?uUiYvVcFzlCfvstEQJ7no7Meify+RwXRIc2Z8yAw6Lv7zotN50UimtxYutFR?= =?us-ascii?Q?KzYT3yk+F0KLlS2xrKkzwZEtgWfHX1pyiAAJPr6Ki/9hlPMqf2HmntIEeSTv?= =?us-ascii?Q?ykSdgzWfo7mTih3KxfmIPXwVBRIwNeP782NdSm7nIwqE1Ttiiqo/VLT4ZtM8?= =?us-ascii?Q?7DR8yCVQYzxA4OuzD9vwjbRKvghGH0gUnXg2sJkILCfV5U0QLEHbKzQODVF0?= =?us-ascii?Q?vjvO60v+dEX1g70=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2025 13:04:27.4760 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 3798532c-ce37-4c10-c174-08dde0b34282 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F6.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MW3PR12MB4459 Received-SPF: permerror client-ip=2a01:111:f403:2406::631; envelope-from=Luc.Michel@amd.com; helo=NAM02-SN1-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755781576771116600 Content-Type: text/plain; charset="utf-8" Refactor the GEM ethernet controllers creation using the VersalMap structure. Note that the connection to the CRL is removed for now and will be re-added by next commits. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-versal.h | 3 - hw/arm/xlnx-versal-virt.c | 54 ------------- hw/arm/xlnx-versal.c | 151 +++++++++++++++++++++++++---------- 3 files changed, 108 insertions(+), 100 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 4a7a2d85aac..1fcc2b623da 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -16,11 +16,10 @@ #include "hw/sysbus.h" #include "hw/cpu/cluster.h" #include "hw/or-irq.h" #include "hw/intc/arm_gicv3.h" #include "hw/dma/xlnx-zdma.h" -#include "hw/net/cadence_gem.h" #include "hw/rtc/xlnx-zynqmp-rtc.h" #include "qom/object.h" #include "hw/usb/xlnx-usb-subsystem.h" #include "hw/misc/xlnx-versal-xramc.h" #include "hw/nvram/xlnx-bbram.h" @@ -76,12 +75,10 @@ struct Versal { =20 struct { MemoryRegion mr_ocm; =20 struct { - CadenceGEMState gem[XLNX_VERSAL_NR_GEMS]; - OrIRQState gem_irq_orgate[XLNX_VERSAL_NR_GEMS]; XlnxZDMA adma[XLNX_VERSAL_NR_ADMAS]; VersalUsb2 usb; } iou; =20 /* Real-time Processing Unit. */ diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index f546ec10f6f..fa2d875f0ae 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -36,11 +36,10 @@ struct VersalVirt { =20 void *fdt; int fdt_size; struct { uint32_t gic; - uint32_t ethernet_phy[2]; uint32_t clk_125Mhz; uint32_t clk_25Mhz; uint32_t usb; uint32_t dwc; } phandle; @@ -55,23 +54,19 @@ struct VersalVirt { }; =20 static void fdt_create(VersalVirt *s) { MachineClass *mc =3D MACHINE_GET_CLASS(s); - int i; =20 s->fdt =3D create_device_tree(&s->fdt_size); if (!s->fdt) { error_report("create_device_tree() failed"); exit(1); } =20 /* Allocate all phandles. */ s->phandle.gic =3D qemu_fdt_alloc_phandle(s->fdt); - for (i =3D 0; i < ARRAY_SIZE(s->phandle.ethernet_phy); i++) { - s->phandle.ethernet_phy[i] =3D qemu_fdt_alloc_phandle(s->fdt); - } s->phandle.clk_25Mhz =3D qemu_fdt_alloc_phandle(s->fdt); s->phandle.clk_125Mhz =3D qemu_fdt_alloc_phandle(s->fdt); =20 s->phandle.usb =3D qemu_fdt_alloc_phandle(s->fdt); s->phandle.dwc =3D qemu_fdt_alloc_phandle(s->fdt); @@ -207,58 +202,10 @@ static void fdt_add_usb_xhci_nodes(VersalVirt *s) qemu_fdt_setprop_cell(s->fdt, name, "phandle", s->phandle.dwc); qemu_fdt_setprop_string(s->fdt, name, "maximum-speed", "high-speed"); g_free(name); } =20 -static void fdt_add_fixed_link_nodes(VersalVirt *s, char *gemname, - uint32_t phandle) -{ - char *name =3D g_strdup_printf("%s/fixed-link", gemname); - - qemu_fdt_add_subnode(s->fdt, name); - qemu_fdt_setprop_cell(s->fdt, name, "phandle", phandle); - qemu_fdt_setprop(s->fdt, name, "full-duplex", NULL, 0); - qemu_fdt_setprop_cell(s->fdt, name, "speed", 1000); - g_free(name); -} - -static void fdt_add_gem_nodes(VersalVirt *s) -{ - uint64_t addrs[] =3D { MM_GEM1, MM_GEM0 }; - unsigned int irqs[] =3D { VERSAL_GEM1_IRQ_0, VERSAL_GEM0_IRQ_0 }; - const char clocknames[] =3D "pclk\0hclk\0tx_clk\0rx_clk"; - const char compat_gem[] =3D "cdns,zynqmp-gem\0cdns,gem"; - int i; - - for (i =3D 0; i < ARRAY_SIZE(addrs); i++) { - char *name =3D g_strdup_printf("/ethernet@%" PRIx64, addrs[i]); - qemu_fdt_add_subnode(s->fdt, name); - - fdt_add_fixed_link_nodes(s, name, s->phandle.ethernet_phy[i]); - qemu_fdt_setprop_string(s->fdt, name, "phy-mode", "rgmii-id"); - qemu_fdt_setprop_cell(s->fdt, name, "phy-handle", - s->phandle.ethernet_phy[i]); - qemu_fdt_setprop_cells(s->fdt, name, "clocks", - s->phandle.clk_25Mhz, s->phandle.clk_25Mhz, - s->phandle.clk_125Mhz, s->phandle.clk_125Mh= z); - qemu_fdt_setprop(s->fdt, name, "clock-names", - clocknames, sizeof(clocknames)); - qemu_fdt_setprop_cells(s->fdt, name, "interrupts", - GIC_FDT_IRQ_TYPE_SPI, irqs[i], - GIC_FDT_IRQ_FLAGS_LEVEL_HI, - GIC_FDT_IRQ_TYPE_SPI, irqs[i], - GIC_FDT_IRQ_FLAGS_LEVEL_HI); - qemu_fdt_setprop_sized_cells(s->fdt, name, "reg", - 2, addrs[i], 2, 0x1000); - qemu_fdt_setprop(s->fdt, name, "compatible", - compat_gem, sizeof(compat_gem)); - qemu_fdt_setprop_cell(s->fdt, name, "#address-cells", 1); - qemu_fdt_setprop_cell(s->fdt, name, "#size-cells", 0); - g_free(name); - } -} - static void fdt_add_zdma_nodes(VersalVirt *s) { const char clocknames[] =3D "clk_main\0clk_apb"; const char compat[] =3D "xlnx,zynqmp-dma-1.0"; int i; @@ -607,11 +554,10 @@ static void versal_virt_init(MachineState *machine) &error_abort); } =20 fdt_create(s); versal_set_fdt(&s->soc, s->fdt); - fdt_add_gem_nodes(s); fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); fdt_add_zdma_nodes(s); fdt_add_usb_xhci_nodes(s); fdt_add_rtc_node(s); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index b963a05935b..062f9a91a6c 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -27,10 +27,11 @@ #include "system/device_tree.h" #include "hw/arm/fdt.h" #include "hw/char/pl011.h" #include "hw/net/xlnx-versal-canfd.h" #include "hw/sd/sdhci.h" +#include "hw/net/cadence_gem.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 =20 @@ -49,10 +50,18 @@ typedef struct VersalMap { VersalSimplePeriphMap canfd[4]; size_t num_canfd; =20 VersalSimplePeriphMap sdhci[2]; size_t num_sdhci; + + struct VersalGemMap { + VersalSimplePeriphMap map; + size_t num_prio_queue; + const char *phy_mode; + const uint32_t speed; + } gem[3]; + size_t num_gem; } VersalMap; =20 static const VersalMap VERSAL_MAP =3D { .uart[0] =3D { 0xff000000, 18 }, .uart[1] =3D { 0xff010000, 19 }, @@ -63,10 +72,14 @@ static const VersalMap VERSAL_MAP =3D { .num_canfd =3D 2, =20 .sdhci[0] =3D { 0xf1040000, 126 }, .sdhci[1] =3D { 0xf1050000, 128 }, .num_sdhci =3D 2, + + .gem[0] =3D { { 0xff0c0000, 56 }, 2, "rgmii-id", 1000 }, + .gem[1] =3D { { 0xff0d0000, 58 }, 2, "rgmii-id", 1000 }, + .num_gem =3D 2, }; =20 static const VersalMap *VERSION_TO_MAP[] =3D { [VERSAL_VER_VERSAL] =3D &VERSAL_MAP, }; @@ -109,10 +122,22 @@ static void versal_sysbus_connect_irq(Versal *s, SysB= usDevice *sbd, } =20 sysbus_connect_irq(sbd, sbd_idx, irq); } =20 +static void versal_qdev_connect_gpio_out(Versal *s, DeviceState *dev, + int dev_idx, int irq_idx) +{ + qemu_irq irq =3D versal_get_irq(s, irq_idx); + + if (irq =3D=3D NULL) { + return; + } + + qdev_connect_gpio_out(dev, dev_idx, irq); +} + static inline char *versal_fdt_add_subnode(Versal *s, const char *path, uint64_t at, const char *compat, size_t compat_sz) { char *p; @@ -138,10 +163,25 @@ static inline char *versal_fdt_add_simple_subnode(Ver= sal *s, const char *path, =20 qemu_fdt_setprop_sized_cells(s->cfg.fdt, p, "reg", 2, addr, 2, len); return p; } =20 +static inline DeviceState *create_or_gate(Versal *s, Object *parent, + const char *name, uint16_t num_l= ines, + int irq_idx) +{ + DeviceState *or; + + or =3D qdev_new(TYPE_OR_IRQ); + qdev_prop_set_uint16(or, "num-lines", num_lines); + object_property_add_child(parent, name, OBJECT(or)); + qdev_realize_and_unref(or, NULL, &error_abort); + versal_qdev_connect_gpio_out(s, or, 0, irq_idx); + + return or; +} + static void versal_create_apu_cpus(Versal *s) { int i; =20 object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, @@ -375,50 +415,80 @@ static void versal_create_usbs(Versal *s, qemu_irq *p= ic) =20 mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); memory_region_add_subregion(&s->mr_ps, MM_USB2_CTRL_REGS, mr); } =20 -static void versal_create_gems(Versal *s, qemu_irq *pic) +static void versal_create_gem(Versal *s, + const struct VersalGemMap *map) { + DeviceState *dev; + MemoryRegion *mr; + DeviceState *or; int i; + g_autofree char *node; + g_autofree char *phy_node; + int phy_phandle; + const char compatible[] =3D "cdns,zynqmp-gem\0cdns,gem"; + const char clocknames[] =3D "pclk\0hclk\0tx_clk\0rx_clk"; + g_autofree uint32_t *irq_prop; =20 - for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { - static const int irqs[] =3D { VERSAL_GEM0_IRQ_0, VERSAL_GEM1_IRQ_0= }; - static const uint64_t addrs[] =3D { MM_GEM0, MM_GEM1 }; - char *name =3D g_strdup_printf("gem%d", i); - DeviceState *dev; - MemoryRegion *mr; - OrIRQState *or_irq; - - object_initialize_child(OBJECT(s), name, &s->lpd.iou.gem[i], - TYPE_CADENCE_GEM); - or_irq =3D &s->lpd.iou.gem_irq_orgate[i]; - object_initialize_child(OBJECT(s), "gem-irq-orgate[*]", - or_irq, TYPE_OR_IRQ); - dev =3D DEVICE(&s->lpd.iou.gem[i]); - qemu_configure_nic_device(dev, true, NULL); - object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); - object_property_set_int(OBJECT(dev), "num-priority-queues", 2, - &error_abort); - object_property_set_int(OBJECT(or_irq), - "num-lines", 2, &error_fatal); - qdev_realize(DEVICE(or_irq), NULL, &error_fatal); - qdev_connect_gpio_out(DEVICE(or_irq), 0, pic[irqs[i]]); - - object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), - &error_abort); - sysbus_realize(SYS_BUS_DEVICE(dev), &error_fatal); - - mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); - memory_region_add_subregion(&s->mr_ps, addrs[i], mr); - - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(DEVICE= (or_irq), 0)); - sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, qdev_get_gpio_in(DEVICE= (or_irq), 1)); - g_free(name); + dev =3D qdev_new(TYPE_CADENCE_GEM); + object_property_add_child(OBJECT(s), "gem[*]", OBJECT(dev)); + + qemu_configure_nic_device(dev, true, NULL); + object_property_set_int(OBJECT(dev), "phy-addr", 23, &error_abort); + object_property_set_int(OBJECT(dev), "num-priority-queues", + map->num_prio_queue, &error_abort); + + object_property_set_link(OBJECT(dev), "dma", OBJECT(&s->mr_ps), + &error_abort); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(&s->mr_ps, map->map.addr, mr); + + /* + * The GEM controller exposes one IRQ line per priority queue. In Vers= al + * family devices, those are OR'ed together. + */ + or =3D create_or_gate(s, OBJECT(dev), "irq-orgate", + map->num_prio_queue, map->map.irq); + + for (i =3D 0; i < map->num_prio_queue; i++) { + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, qdev_get_gpio_in(or, i)= ); + } + + node =3D versal_fdt_add_simple_subnode(s, "/ethernet", map->map.addr, = 0x1000, + compatible, sizeof(compatible)); + phy_node =3D g_strdup_printf("%s/fixed-link", node); + phy_phandle =3D qemu_fdt_alloc_phandle(s->cfg.fdt); + + /* Fixed link PHY node */ + qemu_fdt_add_subnode(s->cfg.fdt, phy_node); + qemu_fdt_setprop_cell(s->cfg.fdt, phy_node, "phandle", phy_phandle); + qemu_fdt_setprop(s->cfg.fdt, phy_node, "full-duplex", NULL, 0); + qemu_fdt_setprop_cell(s->cfg.fdt, phy_node, "speed", map->speed); + + qemu_fdt_setprop_string(s->cfg.fdt, node, "phy-mode", map->phy_mode); + qemu_fdt_setprop_cell(s->cfg.fdt, node, "phy-handle", phy_phandle); + qemu_fdt_setprop_cells(s->cfg.fdt, node, "clocks", + s->phandle.clk_25mhz, s->phandle.clk_25mhz, + s->phandle.clk_125mhz, s->phandle.clk_125mhz); + qemu_fdt_setprop(s->cfg.fdt, node, "clock-names", + clocknames, sizeof(clocknames)); + + irq_prop =3D g_new(uint32_t, map->num_prio_queue * 3); + for (i =3D 0; i < map->num_prio_queue; i++) { + irq_prop[3 * i] =3D cpu_to_be32(GIC_FDT_IRQ_TYPE_SPI); + irq_prop[3 * i + 1] =3D cpu_to_be32(map->map.irq); + irq_prop[3 * i + 2] =3D cpu_to_be32(GIC_FDT_IRQ_FLAGS_LEVEL_HI); } + qemu_fdt_setprop(s->cfg.fdt, node, "interrupts", irq_prop, + sizeof(uint32_t) * map->num_prio_queue * 3); } =20 + static void versal_create_admas(Versal *s, qemu_irq *pic) { int i; =20 for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { @@ -900,18 +970,10 @@ static void versal_create_crl(Versal *s, qemu_irq *pi= c) object_property_set_link(OBJECT(&s->lpd.crl), name, OBJECT(&s->lpd.rpu.cpu[i]), &error_abort); } =20 - for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { - g_autofree gchar *name =3D g_strdup_printf("gem[%d]", i); - - object_property_set_link(OBJECT(&s->lpd.crl), - name, OBJECT(&s->lpd.iou.gem[i]), - &error_abort); - } - for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { g_autofree gchar *name =3D g_strdup_printf("adma[%d]", i); =20 object_property_set_link(OBJECT(&s->lpd.crl), name, OBJECT(&s->lpd.iou.adma[i]), @@ -1095,12 +1157,15 @@ static void versal_realize(DeviceState *dev, Error = **errp) =20 for (i =3D 0; i < map->num_sdhci; i++) { versal_create_sdhci(s, &map->sdhci[i]); } =20 + for (i =3D 0; i < map->num_gem; i++) { + versal_create_gem(s, &map->gem[i]); + } + versal_create_usbs(s, pic); - versal_create_gems(s, pic); versal_create_admas(s, pic); versal_create_pmc_apb_irq_orgate(s, pic); versal_create_rtc(s, pic); versal_create_trng(s, pic); versal_create_xrams(s, pic); --=20 2.50.1