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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v3 38/47] hw/arm/xlnx-versal: add the target field in IRQ descriptor Date: Thu, 21 Aug 2025 15:03:37 +0200 Message-ID: <20250821130354.125971-39-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821130354.125971-1-luc.michel@amd.com> References: <20250821130354.125971-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017095:EE_|PH0PR12MB7814:EE_ X-MS-Office365-Filtering-Correlation-Id: cf3934b5-b976-43b4-5b49-08dde0b365aa X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|376014|1800799024|36860700013; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?DJnEZ/kr9RGZWSYoXVwOAAXWuojfydlsGlGBthF4MTtVLbdOFXNwuImTyFmy?= =?us-ascii?Q?4r1XLavo1GucUdIafIKRYUHBLo03IyPxP5SGbfgKtdCfoTxhDsIAcz0Ig1D7?= =?us-ascii?Q?z6Z23YEkLcTNMzvJiokqQxfyo0ut3CbmRYJfdhAj9j1Nuh087DrdWwrtlBcK?= =?us-ascii?Q?NJL76fRasXJwbivAdGwos26lhXK112Utq3wKXO/XDuCeBsfoqZPdwxIbuH14?= =?us-ascii?Q?gW2BLsop51MZBA2qKY5vZMmrQqXuuqSPryl42LmUMH4R992u+s5gsnSF5giQ?= =?us-ascii?Q?XHL0+ALZWVRL1Hql0qpThtShUerWmZqCJoS82ipnL8b8nZOsOXQdRhhwsMrb?= =?us-ascii?Q?cyDtSiVNCKxGqogdZvsIgvvJER+uYPvCjLkCM/Tl3Xv8cw7smgov6ZF/r0cj?= =?us-ascii?Q?EplLJM0/WDYmBZ6Q66vus44FZz5bSRWjsq02fOmCK967Dsq6Y1ndiqha/A4C?= =?us-ascii?Q?CvoXo/Uo4qQczOXgC13eKiWPOL+SZf+GfjrK32m2zeKx8ous5hh7apJKYXP7?= =?us-ascii?Q?mkZ9yTf2mknXnA6QnONtJjtJS3VLDQrgpWVsjvHc9R/5tn9ApGYLVhGgzWKn?= =?us-ascii?Q?QOZFm04ROaW3iX5kvJQvu2y76/sC1NZ3fbMov3/4uzeSV3CMEdn/ona3volo?= =?us-ascii?Q?vEHbs/npgGP/U8vOmUDglKPapXLsVctHIgIJgiTSmZtk1HYBXApzWkIixtBE?= =?us-ascii?Q?ROX5XyWU//QfluwrVGMOxRUVOKzEPu5q1UDi7SBK/ICKEcjqESVBM/iYEz7I?= =?us-ascii?Q?mTf0UlYuQPKAqe7zvM4k18HPXDqRvGKk5A4HxpX9p9bZOnsNTMst6m0BcsrP?= =?us-ascii?Q?ql+FjXgtXwoQRXMgfkEEY41QBR9JNUwXOycT5ayncqqtb85A9ZfAqAdVKuDW?= =?us-ascii?Q?a0UbfPCcHDoz7DK3VwuNVfIHyob5wrq0NtbG9L1iqzNDnBow2nTlRbyhBqV9?= =?us-ascii?Q?7kJ7mAFHQjyyGq6vBBVo/35G1/4azMwErhrlzDlzi5ab+KIkotyCzw9nC5oG?= =?us-ascii?Q?F4bc/cXph1+qU+JKdNcRC6nEYuk1CWmypvOn+abGgZpzpiXuOmAxpXgz0lCI?= =?us-ascii?Q?XRdWuimSSPaN6G6CYBdVO6xGY6r9a1CN+4qBMRF+ZzVNhislmCL7x+9v5yiL?= =?us-ascii?Q?gE9d2FmesMlkHlseolQxYuOTwt65q3w404xA3WsVIrzIL8pIQ2pr3Yhro12U?= =?us-ascii?Q?tuYAPrUDhO9zKNZBab/qdVbKXALHhghXeexKsviDnxWQeYKlarzO+baueHA0?= =?us-ascii?Q?2xS6TGGBdxpGZa5/QVcFtJfHjF7pQbLId2sKAWAL5WSaqNKCZE5749S4nvnI?= =?us-ascii?Q?BOwzX/IJPlNg1pf1A5g7eLAHsFHL6q1uBAIIjnVLi5dZTKuY3wiS4NAJPME2?= =?us-ascii?Q?D91mE8igoCfXlrZmRN3bHc+NsmtWg/8RmSdRE5Wl89mE7hDI/YfzfP2HG8uo?= =?us-ascii?Q?r3haX+BrIH0QjTK8/R5XupurGXvXNiZxiVgBga3YFt9ogcKo2Hkj18TFOqS7?= =?us-ascii?Q?MvZZeR5cpjMPfFDZVubH1054DxFiMYPsHohs?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(376014)(1800799024)(36860700013); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2025 13:05:26.5101 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: cf3934b5-b976-43b4-5b49-08dde0b365aa X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017095.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH0PR12MB7814 Received-SPF: permerror client-ip=2a01:111:f403:200a::624; envelope-from=Luc.Michel@amd.com; helo=NAM12-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755782457042116600 Content-Type: text/plain; charset="utf-8" Add the target field in the IRQ descriptor. This allows to target an IRQ to another IRQ controller than the GIC(s). Other supported targets are the PMC PPU1 CPU interrupt controller and the EAM (Error management) device. Those two devices are currently not implemented so IRQs targeting those will be left unconnected. This is in preparation for versal2. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- hw/arm/xlnx-versal.c | 41 +++++++++++++++++++++++++++++++++++++++-- 1 file changed, 39 insertions(+), 2 deletions(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 2eb0fa77515..b6d99f5e103 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -50,18 +50,30 @@ #include "hw/cpu/cluster.h" #include "hw/arm/bsa.h" =20 /* * IRQ descriptor to catch the following cases: + * - An IRQ can either connect to the GICs, to the PPU1 intc, or the the= EAM * - Multiple devices can connect to the same IRQ. They are OR'ed togeth= er. */ FIELD(VERSAL_IRQ, IRQ, 0, 16) +FIELD(VERSAL_IRQ, TARGET, 16, 2) FIELD(VERSAL_IRQ, ORED, 18, 1) FIELD(VERSAL_IRQ, OR_IDX, 19, 4) /* input index on the IRQ OR gate */ =20 +typedef enum VersalIrqTarget { + IRQ_TARGET_GIC, + IRQ_TARGET_PPU1, + IRQ_TARGET_EAM, +} VersalIrqTarget; + +#define PPU1_IRQ(irq) ((IRQ_TARGET_PPU1 << R_VERSAL_IRQ_TARGET_SHIFT) | (i= rq)) +#define EAM_IRQ(irq) ((IRQ_TARGET_EAM << R_VERSAL_IRQ_TARGET_SHIFT) | (irq= )) #define OR_IRQ(irq, or_idx) \ (R_VERSAL_IRQ_ORED_MASK | ((or_idx) << R_VERSAL_IRQ_OR_IDX_SHIFT) | (i= rq)) +#define PPU1_OR_IRQ(irq, or_idx) \ + ((IRQ_TARGET_PPU1 << R_VERSAL_IRQ_TARGET_SHIFT) | OR_IRQ(irq, or_idx)) =20 typedef struct VersalSimplePeriphMap { uint64_t addr; int irq; } VersalSimplePeriphMap; @@ -412,19 +424,27 @@ static qemu_irq versal_get_gic_irq(Versal *s, int irq= _idx) * Or gates are placed under the /soc/irq-or-gates QOM container. */ static qemu_irq versal_get_irq_or_gate_in(Versal *s, int irq_idx, qemu_irq target_irq) { + static const char *TARGET_STR[] =3D { + [IRQ_TARGET_GIC] =3D "gic", + [IRQ_TARGET_PPU1] =3D "ppu1", + [IRQ_TARGET_EAM] =3D "eam", + }; + + VersalIrqTarget target; Object *container =3D versal_get_child(s, "irq-or-gates"); DeviceState *dev; g_autofree char *name; int idx, or_idx; =20 idx =3D FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ); or_idx =3D FIELD_EX32(irq_idx, VERSAL_IRQ, OR_IDX); + target =3D FIELD_EX32(irq_idx, VERSAL_IRQ, TARGET); =20 - name =3D g_strdup_printf("irq[%d]", idx); + name =3D g_strdup_printf("%s-irq[%d]", TARGET_STR[target], idx); dev =3D DEVICE(object_resolve_path_at(container, name)); =20 if (dev =3D=3D NULL) { dev =3D qdev_new(TYPE_OR_IRQ); object_property_add_child(container, name, OBJECT(dev)); @@ -436,16 +456,33 @@ static qemu_irq versal_get_irq_or_gate_in(Versal *s, = int irq_idx, return qdev_get_gpio_in(dev, or_idx); } =20 static qemu_irq versal_get_irq(Versal *s, int irq_idx) { + VersalIrqTarget target; qemu_irq irq; bool ored; =20 + target =3D FIELD_EX32(irq_idx, VERSAL_IRQ, TARGET); ored =3D FIELD_EX32(irq_idx, VERSAL_IRQ, ORED); =20 - irq =3D versal_get_gic_irq(s, irq_idx); + switch (target) { + case IRQ_TARGET_EAM: + /* EAM not implemented */ + return NULL; + + case IRQ_TARGET_PPU1: + /* PPU1 CPU not implemented */ + return NULL; + + case IRQ_TARGET_GIC: + irq =3D versal_get_gic_irq(s, irq_idx); + break; + + default: + g_assert_not_reached(); + } =20 if (ored) { irq =3D versal_get_irq_or_gate_in(s, irq_idx, irq); } =20 --=20 2.50.1