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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v3 02/47] hw/arm/xlnx-versal: prepare for FDT creation Date: Thu, 21 Aug 2025 15:03:01 +0200 Message-ID: <20250821130354.125971-3-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821130354.125971-1-luc.michel@amd.com> References: <20250821130354.125971-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|DM4PR12MB5793:EE_ X-MS-Office365-Filtering-Correlation-Id: 037bf804-cbcb-480d-861d-08dde0b33872 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|82310400026|376014; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?EoSUxZrfZMChpvOEhDi5rgE0CKyMce2JyoZutVet7s/Qymlb64wcSkGRng+F?= =?us-ascii?Q?kLZIB96mRbnR5cG86X5PhS/rkBIuPe1AUazleR8PZ1hKBAC2JqodvVKKpABW?= =?us-ascii?Q?o9SRtGD+zd0wD4n3x1R/fvSPl7hJ/7cP9K0YcdMYqaSR8qeUe8Uf6/ly5GoS?= =?us-ascii?Q?lnEAfOJ42LIOFS6YVlws/RLR0GgcoU9u0x0WZv4l3d3u6MxpeQIMvGyZLGnv?= =?us-ascii?Q?heCMk7aBqAPglj9ME5qGEUisBJREw7QyjOJJl2E/GLlQv6Qaa0Qk/y8im4m8?= =?us-ascii?Q?xZF3r0CZA8Flf1gy3bEAN6xIAcym564Bd8GuMB0+hbWhB3O6/ewi4ihhkVbd?= =?us-ascii?Q?CmL+U1iWMFNshF1KG2RCnb92JUnAg1gl/RX8AJ96Hb9/fLKcleI4Ti2zM8RA?= =?us-ascii?Q?oP0VN6eLzx0oJn8yUQJUtSBE1hn4B1OrPEg19PdFhwMnPCIPGTJ+6Cdne7vm?= =?us-ascii?Q?jZaa9xTu6a+XR/Cmfw8r+8tHfd1G42KJdahleXknKHiozSBBek7nQMndZjcY?= =?us-ascii?Q?7eqiGfIqvP+D0jxtlb0AM2dN1tpC9wz3+d/bZtend4G+4BZoP5GZr6BiA493?= =?us-ascii?Q?TEv/nVxTpHpUgHkbarB5Uv3qictqrlJaU4mZpPY1Ok7kQFJTpuO1E0C3yNhY?= =?us-ascii?Q?Z+cFZvnZiYjlhAAKqAsNMtSNdxV/B57VaSWlqrrng2LEIbfvh+YSb8ar3ay9?= =?us-ascii?Q?g8QYgHftI9dHmH70W11FkaMF8avOUgpQXXLs7LWhuuhSa1kEriCEQXCsbVdw?= =?us-ascii?Q?6tw5WSBIu7Xqb+ociDcNtrb1Le4OiXoDuLXQl0LB1jy1kPHzMu3AFtVBQcmv?= =?us-ascii?Q?hgXZ64inBjYHwpnTw6O5h8hgyrraZNLp1LP8lrvSjDBGCMpamM3vx+TsVxzq?= =?us-ascii?Q?u7bQf9dvndZgmythbWCuwfat07AGlpUQ7umCwdGB+6o6Qbph6NeEu7qs9nUv?= =?us-ascii?Q?Y0f+eTtORKTSZBJx3c9YyNK7ykVOXWGGfH41aJfxqqtWfnztiH6pZzQWF1IW?= =?us-ascii?Q?kgknEV8xNMX6zKk+i5p77KATxvt21h8ftgaExbTEbT90QCmJcOT9XXxVKkwb?= =?us-ascii?Q?dyt/dW/2rQBlMSweyGI+0CjHJdCZZEnFUKZjOw5Z7gKj/dBle44oZ5I1Rbke?= =?us-ascii?Q?Zgi/dkbsDERDmgrHPqzBE2I62Icsem6IehruWMGKoSCkigXuqLhvdpADUI6p?= =?us-ascii?Q?8+aH1Y6Y/CKKa4y7poSbefyGhbAhZf7QAsqnbRoW4QsN/+CVfPgIWMNasH9/?= =?us-ascii?Q?+v1AsKcLZHjBrZweHKdjkbfItlziVT+IGbTo7qMOUX49bkp/L2Vh7hhluqzd?= =?us-ascii?Q?lgayGTMeS6kpv5GrBEn10f2OrJP9oVMl5WLFKFUVCKSJfpDI/95qzRiDxORx?= =?us-ascii?Q?706vqV1VOZX+Dsz5AMlJN7P0OhMrxcEEl+LMEiffTdNIHwonHO2v9FQidx/8?= =?us-ascii?Q?oexG3sOAT+gNI8mIVnaodgUOf8NntGlauKWWRysV9/7+sEGV8sQDEdaDCiQk?= =?us-ascii?Q?pEQvrYay3Cno2LnfUUFPzbSEM0YeOqx4otAG?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(82310400026)(376014); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2025 13:04:10.6517 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 037bf804-cbcb-480d-861d-08dde0b33872 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5793 Received-SPF: permerror client-ip=2a01:111:f403:2009::627; envelope-from=Luc.Michel@amd.com; helo=NAM10-BN7-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755781714570116600 Content-Type: text/plain; charset="utf-8" The following commits will move FDT creation logic from the xlnx-versal-virt machine to the xlnx-versal SoC itself. Prepare this by passing the FDT handle to the SoC before it is realized. If no FDT is passed, a dummy one is created internally as a stub to the fdt function calls. For now the SoC only creates the two clock nodes. The ones from the xlnx-versal virt machine are renamed with a `old-' prefix and will be removed once they are not referenced anymore. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-versal.h | 12 ++++++++++++ hw/arm/xlnx-versal-virt.c | 11 +++++++---- hw/arm/xlnx-versal.c | 30 ++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 1f92e314d6c..f2a62b43552 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -134,21 +134,33 @@ struct Versal { XlnxVersalCFrameBcastReg cframe_bcast; =20 OrIRQState apb_irq_orgate; } pmc; =20 + struct { + uint32_t clk_25mhz; + uint32_t clk_125mhz; + } phandle; + struct { MemoryRegion *mr_ddr; + void *fdt; } cfg; }; =20 struct VersalClass { SysBusDeviceClass parent; =20 VersalVersion version; }; =20 +static inline void versal_set_fdt(Versal *s, void *fdt) +{ + g_assert(!qdev_is_realized(DEVICE(s))); + s->cfg.fdt =3D fdt; +} + /* Memory-map and IRQ definitions. Copied a subset from * auto-generated files. */ =20 #define VERSAL_GIC_MAINT_IRQ 9 #define VERSAL_TIMER_VIRT_IRQ 11 diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index adadbb72902..69f3bb401b9 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -1,9 +1,10 @@ /* * Xilinx Versal Virtual board. * * Copyright (c) 2018 Xilinx Inc. + * Copyright (c) 2025 Advanced Micro Devices, Inc. * Written by Edgar E. Iglesias * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 or * (at your option) any later version. @@ -695,14 +696,13 @@ static void versal_virt_init(MachineState *machine) &error_abort); object_property_set_link(OBJECT(&s->soc), "canbus0", OBJECT(s->canbus[= 0]), &error_abort); object_property_set_link(OBJECT(&s->soc), "canbus1", OBJECT(s->canbus[= 1]), &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); =20 fdt_create(s); - create_virtio_regions(s); + versal_set_fdt(&s->soc, s->fdt); fdt_add_gem_nodes(s); fdt_add_uart_nodes(s); fdt_add_canfd_nodes(s); fdt_add_gic_nodes(s); fdt_add_timer_nodes(s); @@ -712,12 +712,15 @@ static void versal_virt_init(MachineState *machine) fdt_add_rtc_node(s); fdt_add_bbram_node(s); fdt_add_efuse_ctrl_node(s); fdt_add_efuse_cache_node(s); fdt_add_cpu_nodes(s, psci_conduit); - fdt_add_clk_node(s, "/clk125", 125000000, s->phandle.clk_125Mhz); - fdt_add_clk_node(s, "/clk25", 25000000, s->phandle.clk_25Mhz); + fdt_add_clk_node(s, "/old-clk125", 125000000, s->phandle.clk_125Mhz); + fdt_add_clk_node(s, "/old-clk25", 25000000, s->phandle.clk_25Mhz); + + sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); + create_virtio_regions(s); =20 /* Make the APU cpu address space visible to virtio and other * modules unaware of multiple address-spaces. */ memory_region_add_subregion_overlap(get_system_memory(), 0, &s->soc.fpd.apu.mr, 0); diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 4da656318f6..7bb55751e5c 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -22,10 +22,12 @@ #include "hw/misc/unimp.h" #include "hw/arm/xlnx-versal.h" #include "qemu/log.h" #include "target/arm/cpu-qom.h" #include "target/arm/gtimer.h" +#include "system/device_tree.h" +#include "hw/arm/fdt.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 =20 @@ -917,14 +919,42 @@ static void versal_unimp(Versal *s) qdev_connect_gpio_out_named(DEVICE(&s->pmc.iou.slcr), SYSBUS_DEVICE_GPIO_IRQ, 0, gpio_in); } =20 +static uint32_t fdt_add_clk_node(Versal *s, const char *name, + unsigned int freq_hz) +{ + uint32_t phandle; + + phandle =3D qemu_fdt_alloc_phandle(s->cfg.fdt); + + qemu_fdt_add_subnode(s->cfg.fdt, name); + qemu_fdt_setprop_cell(s->cfg.fdt, name, "phandle", phandle); + qemu_fdt_setprop_cell(s->cfg.fdt, name, "clock-frequency", freq_hz); + qemu_fdt_setprop_cell(s->cfg.fdt, name, "#clock-cells", 0x0); + qemu_fdt_setprop_string(s->cfg.fdt, name, "compatible", "fixed-clock"); + qemu_fdt_setprop(s->cfg.fdt, name, "u-boot,dm-pre-reloc", NULL, 0); + + return phandle; +} + static void versal_realize(DeviceState *dev, Error **errp) { Versal *s =3D XLNX_VERSAL_BASE(dev); qemu_irq pic[XLNX_VERSAL_NR_IRQS]; + const VersalMap *map =3D versal_get_map(s); + size_t i; + + if (s->cfg.fdt =3D=3D NULL) { + int fdt_size; + + s->cfg.fdt =3D create_device_tree(&fdt_size); + } + + s->phandle.clk_25mhz =3D fdt_add_clk_node(s, "/clk25", 25 * 1000 * 100= 0); + s->phandle.clk_125mhz =3D fdt_add_clk_node(s, "/clk125", 125 * 1000 * = 1000); =20 versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); versal_create_rpu_cpus(s); versal_create_uarts(s, pic); --=20 2.50.1