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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v3 28/47] hw/arm/xlnx-versal: ddr: refactor creation Date: Thu, 21 Aug 2025 15:03:27 +0200 Message-ID: <20250821130354.125971-29-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821130354.125971-1-luc.michel@amd.com> References: <20250821130354.125971-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017090:EE_|MN0PR12MB5787:EE_ X-MS-Office365-Filtering-Correlation-Id: 022e971c-f3fe-42dc-60c3-08dde0b35f99 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|1800799024|36860700013|376014|82310400026; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?57xuWx7zoZpKz6lybu6jvWK3FKFCK7J1XUT8U8b6LvSD8cRvDhxqKMWsMbiT?= =?us-ascii?Q?2MBFM8EgqAccZjT28XSxXJYii18WPtm+A3vVMcUTPdQbWYqIx7uMi+BShdjO?= =?us-ascii?Q?ARoWKE/mI2belbkHZy8Xu3G6nm/zlBonFw36PKW8p1F9VAjHGAVK5j+k60mo?= =?us-ascii?Q?OPodIqEdmch0a/wSpRqZt9fnvU6jxDFmjgLKPKK+k5KY/0fcSbqgWPN19e0g?= =?us-ascii?Q?57BlimqK1NqwQ8RNLAfysr+5attFN3bQDVoBlW5A3Wj5K/dNXonRigWRTp7T?= =?us-ascii?Q?Z7HMouqez0sy7glyKnS5s1ccrteqUMDnAsyn3MOn4fQ3ixAWQ3xnWNyFYq+0?= =?us-ascii?Q?iL5xasDFQTbw4FQeoS7jmMasBgjnzvLuO0fJ4a6exOzpDD11cKl43MFhrzfW?= =?us-ascii?Q?0lNefTQDLuzTBaf/8Q3nTBBR7cdL7y/V9TUP48eJdDI2KTAzE0UhVQq6hpdX?= =?us-ascii?Q?Kn02m5DJDyVM+gDkmDTK6pqtDD6g7WoV2HvFkk4zz4kQdUr6sPvoM0WZ5QPL?= =?us-ascii?Q?nRO0Eb+Q5rRF9tFqz9APKYUHnDX67+GR7Msw69DpY8EiVFJF49sQEKdoU8FE?= =?us-ascii?Q?PAOf7KxhGnMihAk/Eo/Tg26Z/KPXOEwmEc/C93NPlNnR4+e2Yk0zboAfXzTd?= =?us-ascii?Q?fRbt4uQ4TVk3bSNz+ypI24cch86TwW8Bly0wicRFPE9YPvGMG5HMT07PfaYh?= =?us-ascii?Q?X4/OKKNLTZw43yhyB5XftBJWnRxCGHRCS5WEZeUeJ3Q2mRJMehZO5dl/XR0g?= =?us-ascii?Q?qJQ1hroCZLuDZy2eloopxE3uE76YINYEGELLYwKOTkMoP8kVPvmQI9MwutWA?= =?us-ascii?Q?lfnqcotEaGsznv9cUymHcEmAwKwC5RzOxw1xIV5XA3xro1mPuqajm/lvdUx1?= =?us-ascii?Q?ZLaCVGSFIE1B0TNaTcl6B0xI6OP+SzotLmylTjcZD+xSeWKJ/N51J2szajEy?= =?us-ascii?Q?OG2a6Qo6YXWcJ9TU+Eb08W1Rr9AJtVEHl7L3isOBdqvGQigNkXPBJ0R798eC?= =?us-ascii?Q?Fsmsn2ZTBYTZyUj+SiE4jAfGW0+YHTemnUPCkUl43xYY6sYhg4ufkLFklSJq?= =?us-ascii?Q?ChoV4G0Dr0p1Web/xBqCN20s7qa6sndOqkMol+bpS3PtJN00aX9RRSEiFp0D?= =?us-ascii?Q?k/A9hCEf+Bx8X/C/BAlKMxFOYVdMvtrd0U9ci7ig27l9uTaE7HEgkVb21z6v?= =?us-ascii?Q?cd7EF7oNcwF2RftXMVwmHkubXJBdGGalXsAF+4cyTJgocBNsc0oSCTGX6fyV?= =?us-ascii?Q?rUzAvxYcyHJEG7vz+l89gt7LJU3tqcxiNe5wIq0AYTfhiZ2TPnUvm2u2zXAG?= =?us-ascii?Q?I576rIB+OyZXjMBVHdp0jWqEyGWtykydFrdlm6Lt7xPMIYZSUcD60++/14c7?= =?us-ascii?Q?pYG1xImoEJFQqRW5IoMKa5fb+WQvZVnbLgmIQye+zHw1RXDN9QaA16WiZSxC?= =?us-ascii?Q?PdJvNKCebUVEL5ePM6YoPiilFpNeBUz+5iHpBmzJKot99oFPtfZMLn6O3Str?= =?us-ascii?Q?FRC2QbY7tSnoKUtyyfIy52OG2ufZp4fn6yu1?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(1800799024)(36860700013)(376014)(82310400026); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2025 13:05:16.3316 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 022e971c-f3fe-42dc-60c3-08dde0b35f99 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017090.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB5787 Received-SPF: permerror client-ip=2a01:111:f403:2412::602; envelope-from=Luc.Michel@amd.com; helo=NAM10-MW2-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755781634415124100 Content-Type: text/plain; charset="utf-8" Refactor the DDR aperture regions creation using the VersalMap structure. Device creation and FDT node creation are split into two functions because the later must happen during ARM virtual bootloader modify_dtb callback. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-versal.h | 7 +--- hw/arm/xlnx-versal-virt.c | 79 +----------------------------------- hw/arm/xlnx-versal.c | 73 ++++++++++++++++++++++----------- 3 files changed, 53 insertions(+), 106 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index e1d6e545495..39bc414c85c 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -41,15 +41,10 @@ struct Versal { =20 /*< public >*/ GArray *intc; MemoryRegion mr_ps; =20 - struct { - /* 4 ranges to access DDR. */ - MemoryRegion mr_ddr_ranges[4]; - } noc; - struct { uint32_t clk_25mhz; uint32_t clk_125mhz; uint32_t gic; } phandle; @@ -71,10 +66,12 @@ static inline void versal_set_fdt(Versal *s, void *fdt) { g_assert(!qdev_is_realized(DEVICE(s))); s->cfg.fdt =3D fdt; } =20 +void versal_fdt_add_memory_nodes(Versal *s, uint64_t ram_size); + DeviceState *versal_get_boot_cpu(Versal *s); void versal_sdhci_plug_card(Versal *s, int sd_idx, BlockBackend *blk); void versal_efuse_attach_drive(Versal *s, BlockBackend *blk); void versal_bbram_attach_drive(Versal *s, BlockBackend *blk); void versal_ospi_create_flash(Versal *s, int flash_idx, const char *flash_= mdl, diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index a3945625014..9490c625816 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -104,92 +104,17 @@ static void fdt_nop_memory_nodes(void *fdt, Error **e= rrp) n++; } g_strfreev(node_path); } =20 -static void fdt_add_memory_nodes(VersalVirt *s, void *fdt, uint64_t ram_si= ze) -{ - /* Describes the various split DDR access regions. */ - static const struct { - uint64_t base; - uint64_t size; - } addr_ranges[] =3D { - { MM_TOP_DDR, MM_TOP_DDR_SIZE }, - { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, - { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, - { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } - }; - uint64_t mem_reg_prop[8] =3D {0}; - uint64_t size =3D ram_size; - Error *err =3D NULL; - char *name; - int i; - - fdt_nop_memory_nodes(fdt, &err); - if (err) { - error_report_err(err); - return; - } - - name =3D g_strdup_printf("/memory@%x", MM_TOP_DDR); - for (i =3D 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { - uint64_t mapsize; - - mapsize =3D size < addr_ranges[i].size ? size : addr_ranges[i].siz= e; - - mem_reg_prop[i * 2] =3D addr_ranges[i].base; - mem_reg_prop[i * 2 + 1] =3D mapsize; - size -=3D mapsize; - } - qemu_fdt_add_subnode(fdt, name); - qemu_fdt_setprop_string(fdt, name, "device_type", "memory"); - - switch (i) { - case 1: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1]); - break; - case 2: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1], - 2, mem_reg_prop[2], - 2, mem_reg_prop[3]); - break; - case 3: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1], - 2, mem_reg_prop[2], - 2, mem_reg_prop[3], - 2, mem_reg_prop[4], - 2, mem_reg_prop[5]); - break; - case 4: - qemu_fdt_setprop_sized_cells(fdt, name, "reg", - 2, mem_reg_prop[0], - 2, mem_reg_prop[1], - 2, mem_reg_prop[2], - 2, mem_reg_prop[3], - 2, mem_reg_prop[4], - 2, mem_reg_prop[5], - 2, mem_reg_prop[6], - 2, mem_reg_prop[7]); - break; - default: - g_assert_not_reached(); - } - g_free(name); -} - static void versal_virt_modify_dtb(const struct arm_boot_info *binfo, void *fdt) { VersalVirt *s =3D container_of(binfo, VersalVirt, binfo); =20 - fdt_add_memory_nodes(s, fdt, binfo->ram_size); + fdt_nop_memory_nodes(s->fdt, &error_abort); + versal_fdt_add_memory_nodes(&s->soc, binfo->ram_size); } =20 static void *versal_virt_get_dtb(const struct arm_boot_info *binfo, int *fdt_size) { diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 367e6ba5458..00cea784442 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -113,10 +113,15 @@ typedef struct VersalCpuClusterMap { } VersalCpuClusterMap; =20 typedef struct VersalMap { VersalMemMap ocm; =20 + struct VersalDDRMap { + VersalMemMap chan[4]; + size_t num_chan; + } ddr; + VersalCpuClusterMap apu; VersalCpuClusterMap rpu; =20 VersalSimplePeriphMap uart[2]; size_t num_uart; @@ -217,10 +222,18 @@ static const VersalMap VERSAL_MAP =3D { .ocm =3D { .addr =3D 0xfffc0000, .size =3D 0x40000, }, =20 + .ddr =3D { + .chan[0] =3D { .addr =3D 0x0, .size =3D 2 * GiB }, + .chan[1] =3D { .addr =3D 0x800000000ull, .size =3D 32 * GiB }, + .chan[2] =3D { .addr =3D 0xc00000000ull, .size =3D 256 * GiB }, + .chan[3] =3D { .addr =3D 0x10000000000ull, .size =3D 734 * GiB }, + .num_chan =3D 4, + }, + .apu =3D { .name =3D "apu", .cpu_model =3D ARM_CPU_TYPE_NAME("cortex-a72"), .num_cluster =3D 1, .num_core =3D 2, @@ -1475,50 +1488,62 @@ static inline void versal_create_crl(Versal *s) sysbus_mmio_get_region(SYS_BUS_DEVICE(dev)= , 0)); =20 versal_sysbus_connect_irq(s, SYS_BUS_DEVICE(dev), 0, map->crl.irq); } =20 -/* This takes the board allocated linear DDR memory and creates aliases +/* + * This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ -static void versal_map_ddr(Versal *s) +static void versal_map_ddr(Versal *s, const struct VersalDDRMap *map) { uint64_t size =3D memory_region_size(s->cfg.mr_ddr); - /* Describes the various split DDR access regions. */ - static const struct { - uint64_t base; - uint64_t size; - } addr_ranges[] =3D { - { MM_TOP_DDR, MM_TOP_DDR_SIZE }, - { MM_TOP_DDR_2, MM_TOP_DDR_2_SIZE }, - { MM_TOP_DDR_3, MM_TOP_DDR_3_SIZE }, - { MM_TOP_DDR_4, MM_TOP_DDR_4_SIZE } - }; uint64_t offset =3D 0; int i; =20 - assert(ARRAY_SIZE(addr_ranges) =3D=3D ARRAY_SIZE(s->noc.mr_ddr_ranges)= ); - for (i =3D 0; i < ARRAY_SIZE(addr_ranges) && size; i++) { - char *name; + for (i =3D 0; i < map->num_chan && size; i++) { uint64_t mapsize; + MemoryRegion *alias; + + mapsize =3D MIN(size, map->chan[i].size); =20 - mapsize =3D size < addr_ranges[i].size ? size : addr_ranges[i].siz= e; - name =3D g_strdup_printf("noc-ddr-range%d", i); /* Create the MR alias. */ - memory_region_init_alias(&s->noc.mr_ddr_ranges[i], OBJECT(s), - name, s->cfg.mr_ddr, - offset, mapsize); + alias =3D g_new(MemoryRegion, 1); + memory_region_init_alias(alias, OBJECT(s), "noc-ddr-range", + s->cfg.mr_ddr, offset, mapsize); =20 /* Map it onto the NoC MR. */ - memory_region_add_subregion(&s->mr_ps, addr_ranges[i].base, - &s->noc.mr_ddr_ranges[i]); + memory_region_add_subregion(&s->mr_ps, map->chan[i].addr, alias); offset +=3D mapsize; size -=3D mapsize; - g_free(name); } } =20 +void versal_fdt_add_memory_nodes(Versal *s, uint64_t size) +{ + const struct VersalDDRMap *map =3D &versal_get_map(s)->ddr; + g_autofree char *node; + g_autofree uint64_t *reg; + int i; + + reg =3D g_new(uint64_t, map->num_chan * 2); + + for (i =3D 0; i < map->num_chan && size; i++) { + uint64_t mapsize; + + mapsize =3D MIN(size, map->chan[i].size); + + reg[i * 2] =3D cpu_to_be64(map->chan[i].addr); + reg[i * 2 + 1] =3D cpu_to_be64(mapsize); + + size -=3D mapsize; + } + + node =3D versal_fdt_add_subnode(s, "/memory", 0, "memory", sizeof("mem= ory")); + qemu_fdt_setprop(s->cfg.fdt, node, "reg", reg, sizeof(uint64_t) * i * = 2); +} + static void versal_unimp_area(Versal *s, const char *name, MemoryRegion *mr, hwaddr base, hwaddr size) { DeviceState *dev =3D qdev_new(TYPE_UNIMPLEMENTED_DEVICE); @@ -1682,11 +1707,11 @@ static void versal_realize(DeviceState *dev, Error = **errp) versal_create_trng(s, &map->trng); versal_create_rtc(s, &map->rtc); versal_create_cfu(s, &map->cfu); versal_create_crl(s); =20 - versal_map_ddr(s); + versal_map_ddr(s, &map->ddr); versal_unimp(s); =20 /* Create the On Chip Memory (OCM). */ ocm =3D g_new(MemoryRegion, 1); memory_region_init_ram(ocm, OBJECT(s), "ocm", map->ocm.size, &error_fa= tal); --=20 2.50.1