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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v3 25/47] hw/arm/xlnx-versal: add support for GICv2 Date: Thu, 21 Aug 2025 15:03:24 +0200 Message-ID: <20250821130354.125971-26-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821130354.125971-1-luc.michel@amd.com> References: <20250821130354.125971-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000044F9:EE_|DM4PR12MB5913:EE_ X-MS-Office365-Filtering-Correlation-Id: 85678cca-d02f-46c6-bf6b-08dde0b354ab X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|36860700013|376014|82310400026|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?xQTstm42IBUEykLuihklSwXVZPxIWs45FQ5o0eCr7UraGqAYGV1BGoAmEwko?= =?us-ascii?Q?FIAgRXvFVpHlzrrzlb6MtNbn8uGT9cmlPkVwdduhZKcucfjQ/K30N/P7BWkR?= =?us-ascii?Q?9tahgYqZfTCLvjGBjG4jc0lNYaXMt/jUYhK04hfvVg868Wm0vo0bQ/AZW6OX?= =?us-ascii?Q?5oxCm4qKVaIt787izTxPruUstUTbKbge/IHCyNxPoLVD6GABIHKwZCj6G5p1?= =?us-ascii?Q?tiI7fCv6mYAnMsA4FbZ7bs7O+ay++c5jJtX1ZHMklejk/E7XKP+6FXm1yqrC?= =?us-ascii?Q?35rWrelDn8HWSFSwCylk9HmIYiUy81Z90Awvzvp56pv7Uj+TQMhAQtLmHQcB?= =?us-ascii?Q?j3t2bEH274MfCkawuEzXLB67rbRBbcFjAG8AR04PZbJ7vrHDVo4U0rZvhN4c?= =?us-ascii?Q?PAK4RA6Kq8k2/FKoPMAynUTpsvnsKGoiLZe/+KoCOwoje7Tk5avZGfQNssy7?= =?us-ascii?Q?srdOfP7hMQCK4nybTZFU4m654rUSu2KRt1CWrJqt05J2TBotGgvnnDpIdXUw?= =?us-ascii?Q?PfRB1jblqxYfQXB5aiLimkP2jxq4iheSWMuZUlQG7yGrZRkvTux49d0VwzXR?= =?us-ascii?Q?r+IAGqw0WI8VxcrsdGWgGIm1Qvn9Pe82QXxUsUM1gH8/zHQV9qz8xmjTbtVR?= =?us-ascii?Q?WXzUpcflUsAM49V3ytRWQn7n9BE8QMCp5eLiCvh0D9CGjVFNm7gd6rcTAq53?= =?us-ascii?Q?KLAT25tmx5svp871eGeC75kQktnYaYgnOqIHQa4xqhh+tXZvvFbUzgGit42Z?= =?us-ascii?Q?8NpSTFmiUsxK6f9c+gIPp7pqPyajkXwmnRuGbpqD29BY0sNVuIdTaC2SRPCI?= =?us-ascii?Q?ZRZVYmEO/4BGsaaZB2/Yc74Fb63AZKcWtckK2bIui07C/l3uHGboU+FB/rlV?= =?us-ascii?Q?ZuXQnhGMI0vTXgCbY3uTlUOR4GWt29psNCizccDu6wdtIT3zZuaYIaW1KPoG?= =?us-ascii?Q?jzAk1KYr+DExZeglj8gHLAPfd2g6vLhgj+i68bmyJMCGM/WNX8E5vZQ0lPtk?= =?us-ascii?Q?sOYYlrUjLdAmM0E181cG0Q16CF0r5Sa7hdiWF0NDYaCD9TmWemjrLTMlUqe1?= =?us-ascii?Q?YodmQ01aDBr7dw7/24thKGoxllhK6oOHsmau4gr3xgTCpxYy5Ht+Fwc5Wn4s?= =?us-ascii?Q?71fC7aRIStQUaeRS7+X+AOQBXxO1f5zsenOx57NGcr2+r0OaGBbL65BRjs04?= =?us-ascii?Q?1GO2oZoVWFB2avKkIblMUkEX+A50ImNWFrVXfdfz8MNxAMYMz3XwaNIkxyvO?= =?us-ascii?Q?qAlbZQvbiFodheMzuEPmmwiA96XENqS8ku6jt1wT75KBUtH5mS+x8BGTTzV4?= =?us-ascii?Q?DZfbBRQz9h9CV3qnB7kZqJCN2hbLuAKfrOMdGxflgYTCVSI1kHCN5GKXQs8J?= =?us-ascii?Q?DKQCKngMNJZv0IocdX9Td+tAh8ETgrjAfNQdXEJ8tDsJ297ewrIyqUUNFTBe?= =?us-ascii?Q?6e6T/yheTrgaAVdEvs6OJS9/0ceYYk3gREpgUW7JFwwVst0XCxQXzGfaWbFo?= =?us-ascii?Q?y0rLeQd8ux52peA=3D?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB04.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(36860700013)(376014)(82310400026)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2025 13:04:57.9433 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 85678cca-d02f-46c6-bf6b-08dde0b354ab X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000044F9.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB5913 Received-SPF: permerror client-ip=2a01:111:f403:2418::62c; envelope-from=Luc.Michel@amd.com; helo=NAM12-BN8-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755782125177116600 Content-Type: text/plain; charset="utf-8" Add support for GICv2 instantiation in the Versal SoC. This is in preparation for the RPU refactoring. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- hw/arm/xlnx-versal.c | 82 +++++++++++++++++++++++++++++++++----------- 1 file changed, 62 insertions(+), 20 deletions(-) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 60e90356b57..0137c81c57d 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -43,10 +43,11 @@ #include "hw/misc/xlnx-versal-cframe-reg.h" #include "hw/or-irq.h" #include "hw/misc/xlnx-versal-crl.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/intc/arm_gic.h" #include "hw/core/split-irq.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 @@ -72,10 +73,11 @@ typedef struct VersalSimplePeriphMap { =20 typedef struct VersalGicMap { int version; uint64_t dist; uint64_t redist; + uint64_t cpu_iface; uint64_t its; size_t num_irq; bool has_its; } VersalGicMap; =20 @@ -501,10 +503,14 @@ static void versal_create_gic_its(Versal *s, DeviceState *dev; SysBusDevice *sbd; g_autofree char *node_pat =3D NULL, *node =3D NULL; const char compatible[] =3D "arm,gic-v3-its"; =20 + if (map->gic.version !=3D 3) { + return; + } + if (!map->gic.has_its) { return; } =20 dev =3D qdev_new(TYPE_ARM_GICV3_ITS); @@ -540,49 +546,85 @@ static DeviceState *versal_create_gic(Versal *s, int first_cpu_idx, size_t num_cpu) { DeviceState *dev; SysBusDevice *sbd; - QList *redist_region_count; g_autofree char *node =3D NULL; g_autofree char *name =3D NULL; - const char compatible[] =3D "arm,gic-v3"; + const char gicv3_compat[] =3D "arm,gic-v3"; + const char gicv2_compat[] =3D "arm,cortex-a15-gic"; + + switch (map->gic.version) { + case 2: + dev =3D qdev_new(gic_class_name()); + break; + + case 3: + dev =3D qdev_new(gicv3_class_name()); + break; + + default: + g_assert_not_reached(); + } =20 - dev =3D qdev_new(gicv3_class_name()); name =3D g_strdup_printf("%s-gic[*]", map->name); object_property_add_child(OBJECT(s), name, OBJECT(dev)); sbd =3D SYS_BUS_DEVICE(dev); - qdev_prop_set_uint32(dev, "revision", 3); + qdev_prop_set_uint32(dev, "revision", map->gic.version); qdev_prop_set_uint32(dev, "num-cpu", num_cpu); qdev_prop_set_uint32(dev, "num-irq", map->gic.num_irq + 32); - - redist_region_count =3D qlist_new(); - qlist_append_int(redist_region_count, num_cpu); - qdev_prop_set_array(dev, "redist-region-count", redist_region_count); - qdev_prop_set_bit(dev, "has-security-extensions", true); - qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); - object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), &error_abo= rt); qdev_prop_set_uint32(dev, "first-cpu-index", first_cpu_idx); =20 + if (map->gic.version =3D=3D 3) { + QList *redist_region_count; + + redist_region_count =3D qlist_new(); + qlist_append_int(redist_region_count, num_cpu); + qdev_prop_set_array(dev, "redist-region-count", redist_region_coun= t); + qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); + object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), + &error_abort); + + } + sysbus_realize_and_unref(sbd, &error_fatal); =20 memory_region_add_subregion(mr, map->gic.dist, sysbus_mmio_get_region(sbd, 0)); - memory_region_add_subregion(mr, map->gic.redist, - sysbus_mmio_get_region(sbd, 1)); + + if (map->gic.version =3D=3D 3) { + memory_region_add_subregion(mr, map->gic.redist, + sysbus_mmio_get_region(sbd, 1)); + } else { + memory_region_add_subregion(mr, map->gic.cpu_iface, + sysbus_mmio_get_region(sbd, 1)); + } =20 if (map->dtb_expose) { - node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, compatib= le, - sizeof(compatible)); + if (map->gic.version =3D=3D 3) { + node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, + gicv3_compat, + sizeof(gicv3_compat)); + qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", + 2, map->gic.dist, + 2, 0x10000, + 2, map->gic.redist, + 2, GICV3_REDIST_SIZE * num_cpu); + } else { + node =3D versal_fdt_add_subnode(s, "/gic", map->gic.dist, + gicv2_compat, + sizeof(gicv2_compat)); + qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", + 2, map->gic.dist, + 2, 0x1000, + 2, map->gic.cpu_iface, + 2, 0x1000); + } + qemu_fdt_setprop_cell(s->cfg.fdt, node, "phandle", s->phandle.gic); qemu_fdt_setprop_cell(s->cfg.fdt, node, "#interrupt-cells", 3); - qemu_fdt_setprop_sized_cells(s->cfg.fdt, node, "reg", - 2, map->gic.dist, - 2, 0x10000, - 2, map->gic.redist, - 2, GICV3_REDIST_SIZE * num_cpu); qemu_fdt_setprop_cells(s->cfg.fdt, node, "interrupts", GIC_FDT_IRQ_TYPE_PPI, VERSAL_GIC_MAINT_IRQ, GIC_FDT_IRQ_FLAGS_LEVEL_HI); qemu_fdt_setprop(s->cfg.fdt, node, "interrupt-controller", NULL, 0= ); } --=20 2.50.1