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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v3 24/47] hw/arm/xlnx-versal: add support for multiple GICs Date: Thu, 21 Aug 2025 15:03:23 +0200 Message-ID: <20250821130354.125971-25-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250821130354.125971-1-luc.michel@amd.com> References: <20250821130354.125971-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001508:EE_|IA1PR12MB6259:EE_ X-MS-Office365-Filtering-Correlation-Id: 016471fe-12d6-483a-0524-08dde0b34edf X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|376014|82310400026|36860700013|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?VdNmN2iiB1J66MeYpvlkS4uBLSHwp/nfLsiPIUSRnymnEMWvXGXa/jQT+ePN?= =?us-ascii?Q?dkGFpmAL6tHojM5XaVNTYPsH7qWJtSlbgft26Fierysw0JtBuPRAYZCOCeEI?= =?us-ascii?Q?+k2Vriq4Ls+NuGLxdsieuTVlDspyCNFBWnLODaoeKQrkx8aVXK/bK2uRGbDe?= =?us-ascii?Q?h4e6amwpMNJYWyVwZS5qWERUkl4iKpKHCDHW+YsuBpcq1RwMmaiUfhSD7Xvj?= =?us-ascii?Q?Infs7kfduW6pkvrNP1zcswcS3sPQytHZEbMpytuzRNc6n7es2f+TW+tk/pml?= =?us-ascii?Q?BEOHGylo2StOM+MOkQHQSC4fqr9Bbm9JAv3K5vl9KOsGaLHuGlyPcmWd7Nnr?= =?us-ascii?Q?KD0zubM095OlUO5mtfRtTjBV0QOqPuvdEilRZUXLgTQ6iu9FpQ7Bg4urVSKQ?= =?us-ascii?Q?6uaSh28p6DDXQArBcIx1SdYZvq+XutxWhfk+IRZtF4jPXrDjh0J6x9JbTR++?= =?us-ascii?Q?QvlgP/7thfxu62ddivJHryTiA5pb8aYOe+4FVxwJko7ZTjJc+kot132Kcaug?= =?us-ascii?Q?ypmAHVFAfdgZqydNaRZ+7oECeFVffCHO/fp43JywOAJcK+osYJew7Mi2axZN?= =?us-ascii?Q?mGuOjqxNPDD7S1y7d4CaUl6u+JrDe3UhKIYSjZLXyzaZehOh2/acv3MAhjBe?= =?us-ascii?Q?QVZHL6ShWQoSRriUHpn0RUOpB87CzZKi8eLbNAeUHFQ2UJ+ZiNFsPyXEC8Zn?= =?us-ascii?Q?9i9mtjh6YheSBPgrHKW+jgr3DXxDfvPXUFqJRJUNVIRSaDgfuqgpzjDvtqOI?= =?us-ascii?Q?FMgjntxUYstAj+mU94ckIska+E0XsdIcnHHACzMY0fV3tmNIDyWCeQ4EwsKT?= =?us-ascii?Q?5S6yPz0UG7WzaAOml7LfE2CN5jPHgEH0K9sbevq9WkDNw6dKyxVGlHSJccR5?= =?us-ascii?Q?jgwbDnulNgVOmbCtcoeCE8Q91Yva/WtYy0V5BJRfmtx7YIweZCp09stUth9P?= =?us-ascii?Q?p0oGbIkORDXUnMgdlfVUHvUBKcsKjOKgBlu/yq4BdgfBY7CNJaJvU/narzne?= =?us-ascii?Q?ocRsCkklxzm8YjX5kDUIPHuXWGldY5f01Uq/YwY70YkcrOcQXeJRiq+RPg0I?= =?us-ascii?Q?gd55/yu1CgWisBkq/REsUqLCaadnj2K0zCDC1v7yxHuS+iCJCAnZQ2hJp0VU?= =?us-ascii?Q?M8UtzDIktLjINqSOCa8gkHMahExQpixiaEf+v2E48pUyVfOZEh7UCIR1225s?= =?us-ascii?Q?jig52/+5p/XD0Pli8oiApoEkU+fPGbOHs+QgE3IY0zeaAzoPSNef68J1bg9+?= =?us-ascii?Q?qfaxVxqvx7vT3tPs5Jl2KLFOgKtIpNOjaYyU8wJGfMhEB5+IEb0ZlHDL6xl+?= =?us-ascii?Q?NIAE/x887dv5Lrkfb9SSWw8NCdIypqC6LWyswZChgbW5Pw+cVwqX55uKPbNM?= =?us-ascii?Q?ap71QnlKfKs8dCiRJGRGxt/t+cZp9/WV43ORzIC2uWnVhuqxR3t78PAta6M3?= =?us-ascii?Q?I+OZcTby15dxryqnKdUAwmK6OVNbqG/9G9Ejt63dvnMWmGWR/qlmnYp2HROS?= =?us-ascii?Q?p3mB+sdAIw5vQ4rwmReRwbUez6Hn6ALyG+NV?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(376014)(82310400026)(36860700013)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 21 Aug 2025 13:04:48.2736 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 016471fe-12d6-483a-0524-08dde0b34edf X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001508.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA1PR12MB6259 Received-SPF: permerror client-ip=2a01:111:f403:2417::624; envelope-from=Luc.Michel@amd.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755781666614124100 Content-Type: text/plain; charset="utf-8" The Versal SoC contains two GICs: one GICv3 in the APU and one GICv2 in the RPU (currently not instantiated). To prepare for the GICv2 instantiation, add support for multiple GICs when connecting interrupts. When a GIC is created, the first-cpu-index property is set on it, and a pointer to the GIC is stored in the intc array. When connecting an IRQ, a TYPE_SPLIT_IRQ device is created with its num-lines property set to the number of GICs in the SoC. The split device is used to fan out the IRQ to all the GICs. Signed-off-by: Luc Michel Reviewed-by: Francisco Iglesias --- include/hw/arm/xlnx-versal.h | 1 + hw/arm/xlnx-versal.c | 55 +++++++++++++++++++++++++++++++++--- 2 files changed, 52 insertions(+), 4 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 9d9ccfb0014..984f9f2ccdd 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -40,10 +40,11 @@ OBJECT_DECLARE_TYPE(Versal, VersalClass, XLNX_VERSAL_BA= SE) struct Versal { /*< private >*/ SysBusDevice parent_obj; =20 /*< public >*/ + GArray *intc; MemoryRegion mr_ps; =20 struct { /* 4 ranges to access DDR. */ MemoryRegion mr_ddr_ranges[4]; diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index d11ff5aaf24..60e90356b57 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -43,10 +43,11 @@ #include "hw/misc/xlnx-versal-cframe-reg.h" #include "hw/or-irq.h" #include "hw/misc/xlnx-versal-crl.h" #include "hw/intc/arm_gicv3_common.h" #include "hw/intc/arm_gicv3_its_common.h" +#include "hw/core/split-irq.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") #define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 =20 @@ -315,10 +316,47 @@ static inline Object *versal_get_child_idx(Versal *s,= const char *child, g_autofree char *n =3D g_strdup_printf("%s[%zu]", child, idx); =20 return versal_get_child(s, n); } =20 +/* + * The SoC embeds multiple GICs. They all receives the same IRQ lines at t= he + * same index. This function creates a TYPE_SPLIT_IRQ device to fan out the + * given IRQ input to all the GICs. + * + * The TYPE_SPLIT_IRQ devices lie in the /soc/irq-splits QOM container + */ +static qemu_irq versal_get_gic_irq(Versal *s, int irq_idx) +{ + DeviceState *split; + Object *container =3D versal_get_child(s, "irq-splits"); + int idx =3D FIELD_EX32(irq_idx, VERSAL_IRQ, IRQ); + g_autofree char *name =3D g_strdup_printf("irq[%d]", idx); + + split =3D DEVICE(object_resolve_path_at(container, name)); + + if (split =3D=3D NULL) { + size_t i; + + split =3D qdev_new(TYPE_SPLIT_IRQ); + qdev_prop_set_uint16(split, "num-lines", s->intc->len); + object_property_add_child(container, name, OBJECT(split)); + qdev_realize_and_unref(split, NULL, &error_abort); + + for (i =3D 0; i < s->intc->len; i++) { + DeviceState *gic; + + gic =3D g_array_index(s->intc, DeviceState *, i); + qdev_connect_gpio_out(split, i, qdev_get_gpio_in(gic, idx)); + } + } else { + g_assert(FIELD_EX32(irq_idx, VERSAL_IRQ, ORED)); + } + + return qdev_get_gpio_in(split, 0); +} + /* * When the R_VERSAL_IRQ_ORED flag is set on an IRQ descriptor, this funct= ion is * used to return the corresponding or gate input IRQ. The or gate is crea= ted if * not already existant. * @@ -351,16 +389,14 @@ static qemu_irq versal_get_irq_or_gate_in(Versal *s, = int irq_idx, =20 static qemu_irq versal_get_irq(Versal *s, int irq_idx) { qemu_irq irq; bool ored; - DeviceState *gic; =20 ored =3D FIELD_EX32(irq_idx, VERSAL_IRQ, ORED); =20 - gic =3D DEVICE(versal_get_child_idx(s, "apu-gic", 0)); - irq =3D qdev_get_gpio_in(gic, irq_idx); + irq =3D versal_get_gic_irq(s, irq_idx); =20 if (ored) { irq =3D versal_get_irq_or_gate_in(s, irq_idx, irq); } =20 @@ -499,10 +535,11 @@ static void versal_create_gic_its(Versal *s, } =20 static DeviceState *versal_create_gic(Versal *s, const VersalCpuClusterMap *map, MemoryRegion *mr, + int first_cpu_idx, size_t num_cpu) { DeviceState *dev; SysBusDevice *sbd; QList *redist_region_count; @@ -523,10 +560,11 @@ static DeviceState *versal_create_gic(Versal *s, qdev_prop_set_array(dev, "redist-region-count", redist_region_count); =20 qdev_prop_set_bit(dev, "has-security-extensions", true); qdev_prop_set_bit(dev, "has-lpi", map->gic.has_its); object_property_set_link(OBJECT(dev), "sysmem", OBJECT(mr), &error_abo= rt); + qdev_prop_set_uint32(dev, "first-cpu-index", first_cpu_idx); =20 sysbus_realize_and_unref(sbd, &error_fatal); =20 memory_region_add_subregion(mr, map->gic.dist, sysbus_mmio_get_region(sbd, 0)); @@ -549,10 +587,12 @@ static DeviceState *versal_create_gic(Versal *s, qemu_fdt_setprop(s->cfg.fdt, node, "interrupt-controller", NULL, 0= ); } =20 versal_create_gic_its(s, map, dev, mr, node); =20 + g_array_append_val(s->intc, dev); + return dev; } =20 static void connect_gic_to_cpu(const VersalCpuClusterMap *map, DeviceState *gic, DeviceState *cpu, size_t = idx, @@ -606,13 +646,15 @@ static inline void versal_create_and_connect_gic(Vers= al *s, MemoryRegion *mr, DeviceState **cpus, size_t num_cpu) { DeviceState *gic; + int first_cpu_idx; size_t i; =20 - gic =3D versal_create_gic(s, map, mr, num_cpu); + first_cpu_idx =3D CPU(cpus[0])->cpu_index; + gic =3D versal_create_gic(s, map, mr, first_cpu_idx, num_cpu); =20 for (i =3D 0; i < num_cpu; i++) { connect_gic_to_cpu(map, gic, cpus[i], i, num_cpu); } } @@ -1535,10 +1577,14 @@ static void versal_realize(DeviceState *dev, Error = **errp) =20 s->phandle.clk_25mhz =3D fdt_add_clk_node(s, "/clk25", 25 * 1000 * 100= 0); s->phandle.clk_125mhz =3D fdt_add_clk_node(s, "/clk125", 125 * 1000 * = 1000); s->phandle.gic =3D qemu_fdt_alloc_phandle(s->cfg.fdt); =20 + container =3D object_new(TYPE_CONTAINER); + object_property_add_child(OBJECT(s), "irq-splits", container); + object_unref(container); + container =3D object_new(TYPE_CONTAINER); object_property_add_child(OBJECT(s), "irq-or-gates", container); object_unref(container); =20 qemu_fdt_setprop_cell(s->cfg.fdt, "/", "interrupt-parent", s->phandle.= gic); @@ -1710,10 +1756,11 @@ static void versal_base_init(Object *obj) =20 memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); + s->intc =3D g_array_new(false, false, sizeof(DeviceState *)); =20 num_can =3D versal_get_map(s)->num_canfd; s->cfg.canbus =3D g_new0(CanBusState *, num_can); =20 for (i =3D 0; i < num_can; i++) { --=20 2.50.1