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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a02:6b8:c0e:500:1:45:d181:d102; envelope-from=d.zhebryakov@yandex.ru; helo=forward102a.mail.yandex.net X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 21 Aug 2025 09:26:25 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @yandex.ru) X-ZM-MESSAGEID: 1755782863864116600 Content-Type: text/plain; charset="utf-8" Add support for passing TLB_BSWAP flag from powerpc booke206 MMU Fix instruction fetches from LE pages being treated as MMIO This change should not affect SPARC, as its instruction fetches are always = BE Signed-off-by: Danila Zhebryakov --- accel/tcg/cputlb.c | 12 +++++------- target/ppc/cpu.h | 4 ++++ target/ppc/mmu-booke.c | 5 +++++ target/ppc/mmu_helper.c | 17 +++++++++++++++-- target/ppc/translate.c | 29 ++++++++++++++++++++++++++++- 5 files changed, 57 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 841b54e41d..396e510f1b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1401,7 +1401,8 @@ static int probe_access_internal(CPUState *cpu, vaddr= addr, flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ - if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGN= ED)) + if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY + | TLB_CHECK_ALIGNED | TLB_BSWAP)) || (access_type !=3D MMU_INST_FETCH && force_mmio)) { *phost =3D NULL; return TLB_MMIO; @@ -1792,12 +1793,9 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Me= mOpIdx oi, mmu_watch_or_dirty(cpu, &l->page[1], type, ra); } =20 - /* - * Since target/sparc is the only user of TLB_BSWAP, and all - * Sparc accesses are aligned, any treatment across two pages - * would be arbitrary. Refuse it until there's a use. - */ - tcg_debug_assert((flags & TLB_BSWAP) =3D=3D 0); + if (unlikely(flags & TLB_BSWAP)) { + l->memop ^=3D MO_BSWAP; + } } =20 return crosspage; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6b90543811..127b05c865 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1186,6 +1186,10 @@ struct ppc_radix_page_info { uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; }; =20 +/*************************************************************************= ****/ +/* PowerPC usage of the PAGE_TARGET_1 bit for TLB little-endian bit */ +#define PAGE_LE PAGE_TARGET_1 + /*************************************************************************= ****/ /* Dynamic Execution Control Register */ =20 diff --git a/target/ppc/mmu-booke.c b/target/ppc/mmu-booke.c index 55e5dd7c6b..dc72bbf21f 100644 --- a/target/ppc/mmu-booke.c +++ b/target/ppc/mmu-booke.c @@ -357,6 +357,11 @@ found_tlb: } =20 *prot =3D 0; + + if (tlb->mas2 & MAS2_E) { + *prot |=3D PAGE_LE; + } + if (pr) { if (tlb->mas7_3 & MAS3_UR) { *prot |=3D PAGE_READ; diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ac60705402..20282edaaa 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -27,6 +27,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" +#include "exec/tlb-flags.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" @@ -1368,8 +1369,20 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int= size, =20 if (ppc_xlate(cpu, eaddr, access_type, &raddr, &page_size, &prot, mmu_idx, !probe)) { - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - prot, mmu_idx, 1UL << page_size); + if (prot & PAGE_LE) { + CPUTLBEntryFull full =3D { + .phys_addr =3D raddr & TARGET_PAGE_MASK, + .attrs =3D MEMTXATTRS_UNSPECIFIED, + .prot =3D prot, + .lg_page_size =3D ctz64(1UL << page_size), + .tlb_fill_flags =3D TLB_BSWAP + }; + tlb_set_page_full(cs, mmu_idx, eaddr & TARGET_PAGE_MASK, &full= ); + + } else { + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE= _MASK, + prot, mmu_idx, 1UL << page_size); + } return true; } if (probe) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 27f90c3cc5..8cf50a0221 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -24,7 +24,9 @@ #include "exec/target_page.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "accel/tcg/probe.h" #include "qemu/host-utils.h" +#include "exec/tlb-flags.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -219,6 +221,27 @@ static inline bool need_byteswap(const DisasContext *c= tx) #endif } =20 +#ifndef CONFIG_USER_ONLY +static bool is_page_little_endian(CPUPPCState *env, vaddr addr) +{ + CPUTLBEntryFull *full; + void *host; + int mmu_idx =3D ppc_env_mmu_index(env, true); + int flags; + + flags =3D probe_access_full_mmu(env, addr, 0, MMU_INST_FETCH, mmu_idx, + &host, &full); + assert(!(flags & TLB_INVALID_MASK)); + + return full->tlb_fill_flags & TLB_BSWAP; +} +#else +static bool is_page_little_endian(CPUPPCState *env, vaddr addr) +{ + return false; +} +#endif + /* True when active word size < size of target_long. */ #ifdef TARGET_PPC64 # define NARROW_MODE(C) (!(C)->sf_mode) @@ -6577,7 +6600,11 @@ static void ppc_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); =20 ctx->cia =3D pc =3D ctx->base.pc_next; - insn =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); + bool tlb_is_le =3D is_page_little_endian(env, ctx->base.pc_next); + + + insn =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx) + || tlb_is_le); ctx->base.pc_next =3D pc +=3D 4; =20 if (!is_prefix_insn(ctx, insn)) { --=20 2.47.2