From nobody Sat Nov 15 03:13:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=yandex.ru ARC-Seal: i=1; a=rsa-sha256; t=1755782862; cv=none; d=zohomail.com; s=zohoarc; b=dHVWUcUYKxEzV1EPpwUl016fOKfsc5ikKg0eEI9vnLt8XR/PI1QeDMkUw7eaAq6TfyeJd0vAnVSydbnTmHsiaRnHtzVRDjivyLNd3+VYXzwXEsUyPRAZoJKFJkhFPhlY7kyTsaQtQN8PIQ/x9erz1qqlP/kQxhxYfTpTBzwG0+U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755782862; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=iPwvSTCU2o8PPIdy3UyxyvI1GnJplS9Cch9VJRDYH4E=; b=FVwrMFCXUbxPk0sH+QFKs5TBKlR2a4QQn/cZtNshBTdHYOacIa0VKgPHQazxiB/TIWsD8jjhl2LWd9mlEExh5FnEF2fqLbT2jNcGJeLqeBIjxXXaKPLdJW9iNedHr88x+C5x9/VCs2N7hj3jiltZIgsFVUiSNKZCTv40WNd+BNQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175578286227981.7179269379559; Thu, 21 Aug 2025 06:27:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1up5JE-0000zY-CE; Thu, 21 Aug 2025 09:26:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1up3YW-00075b-66; Thu, 21 Aug 2025 07:34:08 -0400 Received: from forward100d.mail.yandex.net ([2a02:6b8:c41:1300:1:45:d181:d100]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1up3YO-0008Kc-W5; Thu, 21 Aug 2025 07:34:06 -0400 Received: from mail-nwsmtp-smtp-production-main-95.iva.yp-c.yandex.net (mail-nwsmtp-smtp-production-main-95.iva.yp-c.yandex.net [IPv6:2a02:6b8:c0c:ba25:0:640:6c71:0]) by forward100d.mail.yandex.net (Yandex) with ESMTPS id 960DEC0087; Thu, 21 Aug 2025 14:33:51 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-95.iva.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id mXRF5KIMdSw0-LgyCQBHa; Thu, 21 Aug 2025 14:33:51 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1755776031; bh=iPwvSTCU2o8PPIdy3UyxyvI1GnJplS9Cch9VJRDYH4E=; h=Message-ID:Date:In-Reply-To:Cc:Subject:References:To:From; b=WMYlrcPBnHBhGGDQFv5pviTGmb1FMJBT4vr/HsoHwfnpeBWMikImFDEI64Ge3iWFM XdWdt4R/LGJE2FRb+A+Z7vKhZQjHmgUGN2c3qz4S0toz8pWMSNX+F5UhJhg8KEE8C+ C5KAZ9y410nMMaWjQa/VYjTQ1IhAvUMkmG2L1eoQ= Authentication-Results: mail-nwsmtp-smtp-production-main-95.iva.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Danila Zhebryakov To: qemu-devel@nongnu.org Cc: Chinmay Rath , Nicholas Piggin , Riku Voipio , Ilya Leoshkevich , qemu-ppc@nongnu.org, Paolo Bonzini , David Hildenbrand , qemu-s390x@nongnu.org, Laurent Vivier , Thomas Huth , Richard Henderson , Danila Zhebryakov Subject: [PATCH 1/3] accel/tcg: Unify big- and little- endian atomic ops Date: Thu, 21 Aug 2025 14:33:45 +0300 Message-ID: <20250821113348.91339-2-d.zhebryakov@yandex.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250821113348.91339-1-d.zhebryakov@yandex.ru> References: <20250821113348.91339-1-d.zhebryakov@yandex.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a02:6b8:c41:1300:1:45:d181:d100; envelope-from=d.zhebryakov@yandex.ru; helo=forward100d.mail.yandex.net X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 21 Aug 2025 09:26:25 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @yandex.ru) X-ZM-MESSAGEID: 1755782863976116600 Content-Type: text/plain; charset="utf-8" Remove dedicated LE and BE atomic helpers. Use MO_BSWAP flag of the memop i= nstead. Adjust atomic_mmu_lookup to respect the TLB_BSWAP flag Signed-off-by: Danila Zhebryakov --- accel/tcg/atomic_common.c.inc | 27 +-- accel/tcg/atomic_template.h | 246 +++++++++------------------- accel/tcg/cputlb.c | 10 +- accel/tcg/tcg-runtime.h | 36 +--- accel/tcg/user-exec.c | 2 +- include/accel/tcg/cpu-ldst-common.h | 39 ++--- target/m68k/op_helper.c | 4 +- target/s390x/tcg/mem_helper.c | 6 +- tcg/tcg-op-ldst.c | 31 ++-- 9 files changed, 131 insertions(+), 270 deletions(-) diff --git a/accel/tcg/atomic_common.c.inc b/accel/tcg/atomic_common.c.inc index 6056598c23..4ce3bc3da1 100644 --- a/accel/tcg/atomic_common.c.inc +++ b/accel/tcg/atomic_common.c.inc @@ -42,19 +42,15 @@ static void atomic_trace_rmw_post(CPUArchState *env, ui= nt64_t addr, { return cpu_atomic_##OP##_mmu(env, addr, oldv, newv, oi, GETPC()); } =20 CMPXCHG_HELPER(cmpxchgb, uint32_t) -CMPXCHG_HELPER(cmpxchgw_be, uint32_t) -CMPXCHG_HELPER(cmpxchgw_le, uint32_t) -CMPXCHG_HELPER(cmpxchgl_be, uint32_t) -CMPXCHG_HELPER(cmpxchgl_le, uint32_t) +CMPXCHG_HELPER(cmpxchgw, uint32_t) +CMPXCHG_HELPER(cmpxchgl, uint32_t) =20 #ifdef CONFIG_ATOMIC64 -CMPXCHG_HELPER(cmpxchgq_be, uint64_t) -CMPXCHG_HELPER(cmpxchgq_le, uint64_t) +CMPXCHG_HELPER(cmpxchgq, uint64_t) #endif =20 #if HAVE_CMPXCHG128 -CMPXCHG_HELPER(cmpxchgo_be, Int128) -CMPXCHG_HELPER(cmpxchgo_le, Int128) +CMPXCHG_HELPER(cmpxchgo, Int128) #endif =20 #undef CMPXCHG_HELPER @@ -87,19 +83,14 @@ Int128 HELPER(nonatomic_cmpxchgo)(CPUArchState *env, ui= nt64_t addr, #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPERS(OP) \ ATOMIC_HELPER(glue(OP,b), uint32_t) \ - ATOMIC_HELPER(glue(OP,w_be), uint32_t) \ - ATOMIC_HELPER(glue(OP,w_le), uint32_t) \ - ATOMIC_HELPER(glue(OP,l_be), uint32_t) \ - ATOMIC_HELPER(glue(OP,l_le), uint32_t) \ - ATOMIC_HELPER(glue(OP,q_be), uint64_t) \ - ATOMIC_HELPER(glue(OP,q_le), uint64_t) + ATOMIC_HELPER(glue(OP,w), uint32_t) \ + ATOMIC_HELPER(glue(OP,l), uint32_t) \ + ATOMIC_HELPER(glue(OP,q), uint64_t) #else #define GEN_ATOMIC_HELPERS(OP) \ ATOMIC_HELPER(glue(OP,b), uint32_t) \ - ATOMIC_HELPER(glue(OP,w_be), uint32_t) \ - ATOMIC_HELPER(glue(OP,w_le), uint32_t) \ - ATOMIC_HELPER(glue(OP,l_be), uint32_t) \ - ATOMIC_HELPER(glue(OP,l_le), uint32_t) + ATOMIC_HELPER(glue(OP,w), uint32_t) \ + ATOMIC_HELPER(glue(OP,l), uint32_t) #endif =20 GEN_ATOMIC_HELPERS(fetch_add) diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index 08a475c10c..e51207c498 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -69,63 +69,84 @@ =20 /* Define host-endian atomic operations. Note that END is used within the ATOMIC_NAME macro, and redefined below. */ -#if DATA_SIZE =3D=3D 1 # define END -#elif HOST_BIG_ENDIAN -# define END _be -#else -# define END _le -#endif =20 ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, vaddr addr, ABI_TYPE cmpv, ABI_TYPE newv, MemOpIdx oi, uintptr_t retaddr) { + bool need_bswap =3D get_memop(oi) & MO_BSWAP; DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, - DATA_SIZE, retaddr); - DATA_TYPE ret; - + DATA_SIZE, retaddr, &need_bswap); + DATA_TYPE ret, ret_e; + if (need_bswap) { +#if DATA_SIZE =3D=3D 16 + ret =3D atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv)); +#else + ret =3D qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)); +#endif + ret_e =3D BSWAP(ret); + } else { #if DATA_SIZE =3D=3D 16 - ret =3D atomic16_cmpxchg(haddr, cmpv, newv); + ret =3D atomic16_cmpxchg(haddr, cmpv, newv); #else - ret =3D qatomic_cmpxchg__nocheck(haddr, cmpv, newv); + ret =3D qatomic_cmpxchg__nocheck(haddr, cmpv, newv); #endif + ret_e =3D ret; + } ATOMIC_MMU_CLEANUP; atomic_trace_rmw_post(env, addr, - VALUE_LOW(ret), - VALUE_HIGH(ret), - VALUE_LOW(newv), - VALUE_HIGH(newv), - oi); - return ret; + VALUE_LOW(ret), + VALUE_HIGH(ret), + VALUE_LOW(newv), + VALUE_HIGH(newv), + oi); + return ret_e; } =20 #if DATA_SIZE < 16 ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, vaddr addr, ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) { - DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, - DATA_SIZE, retaddr); - DATA_TYPE ret; + bool need_bswap =3D get_memop(oi) & MO_BSWAP; =20 - ret =3D qatomic_xchg__nocheck(haddr, val); + DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, + DATA_SIZE, retaddr, &need_bswap); + DATA_TYPE ret, ret_e; + + if (need_bswap) { + ret =3D qatomic_xchg__nocheck(haddr, BSWAP(val)); + ret_e =3D BSWAP(ret); + } else { + ret =3D qatomic_xchg__nocheck(haddr, val); + ret_e =3D ret; + } ATOMIC_MMU_CLEANUP; atomic_trace_rmw_post(env, addr, - VALUE_LOW(ret), - VALUE_HIGH(ret), - VALUE_LOW(val), - VALUE_HIGH(val), - oi); - return ret; + VALUE_LOW(ret), + VALUE_HIGH(ret), + VALUE_LOW(val), + VALUE_HIGH(val), + oi); + return ret_e; } =20 #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ { \ - DATA_TYPE *haddr, ret; \ - haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ - ret =3D qatomic_##X(haddr, val); \ + DATA_TYPE *haddr, ret, ret_e; \ + bool need_bswap =3D get_memop(oi) & MO_BSWAP; \ + haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, \ + retaddr, &need_bswap); \ + if (need_bswap) { \ + ret =3D qatomic_##X(haddr, BSWAP(val)); \ + ret_e =3D BSWAP(ret); \ + } \ + else { \ + ret =3D qatomic_##X(haddr, val); \ + ret_e =3D ret; \ + } \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, \ VALUE_LOW(ret), \ @@ -133,7 +154,7 @@ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, = \ VALUE_LOW(val), \ VALUE_HIGH(val), \ oi); \ - return ret; \ + return ret_e; \ } =20 GEN_ATOMIC_HELPER(fetch_add) @@ -155,147 +176,38 @@ GEN_ATOMIC_HELPER(xor_fetch) * Trace this load + RMW loop as a single RMW op. This way, regardless * of CF_PARALLEL's value, we'll trace just a read and a write. */ -#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ -ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ - ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ -{ \ - XDATA_TYPE *haddr, cmp, old, new, val =3D xval; \ - haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ - smp_mb(); \ - cmp =3D qatomic_read__nocheck(haddr); \ - do { \ - old =3D cmp; new =3D FN(old, val); \ - cmp =3D qatomic_cmpxchg__nocheck(haddr, old, new); \ - } while (cmp !=3D old); \ - ATOMIC_MMU_CLEANUP; \ - atomic_trace_rmw_post(env, addr, \ - VALUE_LOW(old), \ - VALUE_HIGH(old), \ - VALUE_LOW(xval), \ - VALUE_HIGH(xval), \ - oi); \ - return RET; \ -} - -GEN_ATOMIC_HELPER_FN(fetch_smin, MIN, SDATA_TYPE, old) -GEN_ATOMIC_HELPER_FN(fetch_umin, MIN, DATA_TYPE, old) -GEN_ATOMIC_HELPER_FN(fetch_smax, MAX, SDATA_TYPE, old) -GEN_ATOMIC_HELPER_FN(fetch_umax, MAX, DATA_TYPE, old) =20 -GEN_ATOMIC_HELPER_FN(smin_fetch, MIN, SDATA_TYPE, new) -GEN_ATOMIC_HELPER_FN(umin_fetch, MIN, DATA_TYPE, new) -GEN_ATOMIC_HELPER_FN(smax_fetch, MAX, SDATA_TYPE, new) -GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new) - -#undef GEN_ATOMIC_HELPER_FN -#endif /* DATA SIZE < 16 */ - -#undef END - -#if DATA_SIZE > 1 - -/* Define reverse-host-endian atomic operations. Note that END is used - within the ATOMIC_NAME macro. */ -#if HOST_BIG_ENDIAN -# define END _le -#else -# define END _be -#endif - -ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, vaddr addr, - ABI_TYPE cmpv, ABI_TYPE newv, - MemOpIdx oi, uintptr_t retaddr) -{ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, - DATA_SIZE, retaddr); - DATA_TYPE ret; - -#if DATA_SIZE =3D=3D 16 - ret =3D atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv)); -#else - ret =3D qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv)); -#endif - ATOMIC_MMU_CLEANUP; - atomic_trace_rmw_post(env, addr, - VALUE_LOW(ret), - VALUE_HIGH(ret), - VALUE_LOW(newv), - VALUE_HIGH(newv), - oi); - return BSWAP(ret); -} - -#if DATA_SIZE < 16 -ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, vaddr addr, ABI_TYPE val, - MemOpIdx oi, uintptr_t retaddr) -{ - DATA_TYPE *haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, - DATA_SIZE, retaddr); - ABI_TYPE ret; - - ret =3D qatomic_xchg__nocheck(haddr, BSWAP(val)); - ATOMIC_MMU_CLEANUP; - atomic_trace_rmw_post(env, addr, - VALUE_LOW(ret), - VALUE_HIGH(ret), - VALUE_LOW(val), - VALUE_HIGH(val), - oi); - return BSWAP(ret); -} - -#define GEN_ATOMIC_HELPER(X) \ -ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ - ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \ -{ \ - DATA_TYPE *haddr, ret; \ - haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ - ret =3D qatomic_##X(haddr, BSWAP(val)); \ - ATOMIC_MMU_CLEANUP; \ - atomic_trace_rmw_post(env, addr, \ - VALUE_LOW(ret), \ - VALUE_HIGH(ret), \ - VALUE_LOW(val), \ - VALUE_HIGH(val), \ - oi); \ - return BSWAP(ret); \ -} - -GEN_ATOMIC_HELPER(fetch_and) -GEN_ATOMIC_HELPER(fetch_or) -GEN_ATOMIC_HELPER(fetch_xor) -GEN_ATOMIC_HELPER(and_fetch) -GEN_ATOMIC_HELPER(or_fetch) -GEN_ATOMIC_HELPER(xor_fetch) - -#undef GEN_ATOMIC_HELPER - -/* These helpers are, as a whole, full barriers. Within the helper, - * the leading barrier is explicit and the trailing barrier is within - * cmpxchg primitive. - * - * Trace this load + RMW loop as a single RMW op. This way, regardless - * of CF_PARALLEL's value, we'll trace just a read and a write. - */ #define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, vaddr addr, \ ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \ { \ XDATA_TYPE *haddr, ldo, ldn, old, new, val =3D xval; \ - haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, retaddr= ); \ + bool need_bswap =3D get_memop(oi) & MO_BSWAP; \ + haddr =3D atomic_mmu_lookup(env_cpu(env), addr, oi, DATA_SIZE, \ + retaddr, &need_bswap); \ smp_mb(); \ ldn =3D qatomic_read__nocheck(haddr); \ - do { \ - ldo =3D ldn; old =3D BSWAP(ldo); new =3D FN(old, val); \ - ldn =3D qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \ - } while (ldo !=3D ldn); \ + if (need_bswap) { \ + do { \ + ldo =3D ldn; old =3D BSWAP(ldo); \ + new =3D FN(old, val); \ + ldn =3D qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \ + } while (ldo !=3D ldn); \ + } \ + else{ \ + do { \ + ldo =3D ldn; old =3D ldo; \ + new =3D FN(old, val); \ + ldn =3D qatomic_cmpxchg__nocheck(haddr, ldo, new); \ + } while (ldo !=3D ldn); \ + } \ ATOMIC_MMU_CLEANUP; \ atomic_trace_rmw_post(env, addr, \ - VALUE_LOW(old), \ - VALUE_HIGH(old), \ - VALUE_LOW(xval), \ - VALUE_HIGH(xval), \ - oi); \ + VALUE_LOW(old), \ + VALUE_HIGH(old), \ + VALUE_LOW(xval), \ + VALUE_HIGH(xval), \ + oi); \ return RET; \ } =20 @@ -309,18 +221,10 @@ GEN_ATOMIC_HELPER_FN(umin_fetch, MIN, DATA_TYPE, new) GEN_ATOMIC_HELPER_FN(smax_fetch, MAX, SDATA_TYPE, new) GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new) =20 -/* Note that for addition, we need to use a separate cmpxchg loop instead - of bswaps for the reverse-host-endian helpers. */ -#define ADD(X, Y) (X + Y) -GEN_ATOMIC_HELPER_FN(fetch_add, ADD, DATA_TYPE, old) -GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new) -#undef ADD - #undef GEN_ATOMIC_HELPER_FN -#endif /* DATA_SIZE < 16 */ +#endif /* DATA SIZE < 16 */ =20 #undef END -#endif /* DATA_SIZE > 1 */ =20 #undef BSWAP #undef ABI_TYPE diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 87e14bde4f..841b54e41d 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1808,7 +1808,7 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Mem= OpIdx oi, * or io operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, - int size, uintptr_t retaddr) + int size, uintptr_t retaddr, bool *need_bsw= ap) { uintptr_t mmu_idx =3D get_mmuidx(oi); MemOp mop =3D get_memop(oi); @@ -1894,6 +1894,14 @@ static void *atomic_mmu_lookup(CPUState *cpu, vaddr = addr, MemOpIdx oi, notdirty_write(cpu, addr, size, full, retaddr); } =20 + if (unlikely(tlb_addr & TLB_BSWAP)) { + assert(!( ( full->slow_flags[MMU_DATA_STORE] + ^ full->slow_flags[MMU_DATA_LOAD ]) + & TLB_BSWAP)); + + *need_bswap =3D !need_bswap; + } + if (unlikely(tlb_addr & TLB_WATCHPOINT)) { int wp_flags =3D 0; =20 diff --git a/accel/tcg/tcg-runtime.h b/accel/tcg/tcg-runtime.h index c23b5e66c4..02679b1fdb 100644 --- a/accel/tcg/tcg-runtime.h +++ b/accel/tcg/tcg-runtime.h @@ -44,24 +44,16 @@ DEF_HELPER_FLAGS_4(st_i128, TCG_CALL_NO_WG, void, env, = i64, i128, i32) =20 DEF_HELPER_FLAGS_5(atomic_cmpxchgb, TCG_CALL_NO_WG, i32, env, i64, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgw_be, TCG_CALL_NO_WG, +DEF_HELPER_FLAGS_5(atomic_cmpxchgw, TCG_CALL_NO_WG, i32, env, i64, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgw_le, TCG_CALL_NO_WG, - i32, env, i64, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgl_be, TCG_CALL_NO_WG, - i32, env, i64, i32, i32, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgl_le, TCG_CALL_NO_WG, +DEF_HELPER_FLAGS_5(atomic_cmpxchgl, TCG_CALL_NO_WG, i32, env, i64, i32, i32, i32) #ifdef CONFIG_ATOMIC64 -DEF_HELPER_FLAGS_5(atomic_cmpxchgq_be, TCG_CALL_NO_WG, - i64, env, i64, i64, i64, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgq_le, TCG_CALL_NO_WG, +DEF_HELPER_FLAGS_5(atomic_cmpxchgq, TCG_CALL_NO_WG, i64, env, i64, i64, i64, i32) #endif #if HAVE_CMPXCHG128 -DEF_HELPER_FLAGS_5(atomic_cmpxchgo_be, TCG_CALL_NO_WG, - i128, env, i64, i128, i128, i32) -DEF_HELPER_FLAGS_5(atomic_cmpxchgo_le, TCG_CALL_NO_WG, +DEF_HELPER_FLAGS_5(atomic_cmpxchgo, TCG_CALL_NO_WG, i128, env, i64, i128, i128, i32) #endif =20 @@ -72,29 +64,19 @@ DEF_HELPER_FLAGS_5(nonatomic_cmpxchgo, TCG_CALL_NO_WG, #define GEN_ATOMIC_HELPERS(NAME) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w), \ TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l), \ TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_le), \ - TCG_CALL_NO_WG, i64, env, i64, i64, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q_be), \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), q), \ TCG_CALL_NO_WG, i64, env, i64, i64, i32) #else #define GEN_ATOMIC_HELPERS(NAME) \ DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), b), \ TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_le), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w_be), \ - TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_le), \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), w), \ TCG_CALL_NO_WG, i32, env, i64, i32, i32) \ - DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l_be), \ + DEF_HELPER_FLAGS_4(glue(glue(atomic_, NAME), l), \ TCG_CALL_NO_WG, i32, env, i64, i32, i32) #endif /* CONFIG_ATOMIC64 */ =20 diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index f25d80e2dc..0c7443a16e 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -1268,7 +1268,7 @@ uint64_t cpu_ldq_code_mmu(CPUArchState *env, vaddr ad= dr, * Do not allow unaligned operations to proceed. Return the host address. */ static void *atomic_mmu_lookup(CPUState *cpu, vaddr addr, MemOpIdx oi, - int size, uintptr_t retaddr) + int size, uintptr_t retaddr, bool *need_bsw= ap) { MemOp mop =3D get_memop(oi); int a_bits =3D memop_alignment_bits(mop); diff --git a/include/accel/tcg/cpu-ldst-common.h b/include/accel/tcg/cpu-ld= st-common.h index 8bf17c2fab..b07f1827ce 100644 --- a/include/accel/tcg/cpu-ldst-common.h +++ b/include/accel/tcg/cpu-ldst-common.h @@ -36,22 +36,13 @@ void cpu_st16_mmu(CPUArchState *env, vaddr addr, Int128= val, uint32_t cpu_atomic_cmpxchgb_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_le_mmu(CPUArchState *env, vaddr addr, +uint32_t cpu_atomic_cmpxchgw_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_le_mmu(CPUArchState *env, vaddr addr, +uint32_t cpu_atomic_cmpxchgl_mmu(CPUArchState *env, vaddr addr, uint32_t cmpv, uint32_t newv, MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_le_mmu(CPUArchState *env, vaddr addr, - uint64_t cmpv, uint64_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgw_be_mmu(CPUArchState *env, vaddr addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint32_t cpu_atomic_cmpxchgl_be_mmu(CPUArchState *env, vaddr addr, - uint32_t cmpv, uint32_t newv, - MemOpIdx oi, uintptr_t retaddr); -uint64_t cpu_atomic_cmpxchgq_be_mmu(CPUArchState *env, vaddr addr, +uint64_t cpu_atomic_cmpxchgq_mmu(CPUArchState *env, vaddr addr, uint64_t cmpv, uint64_t newv, MemOpIdx oi, uintptr_t retaddr); =20 @@ -63,19 +54,14 @@ TYPE cpu_atomic_ ## NAME ## SUFFIX ## _mmu \ #ifdef CONFIG_ATOMIC64 #define GEN_ATOMIC_HELPER_ALL(NAME) \ GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_le) \ - GEN_ATOMIC_HELPER(NAME, uint64_t, q_be) + GEN_ATOMIC_HELPER(NAME, uint32_t, w) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l) \ + GEN_ATOMIC_HELPER(NAME, uint64_t, q) #else #define GEN_ATOMIC_HELPER_ALL(NAME) \ GEN_ATOMIC_HELPER(NAME, uint32_t, b) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, w_be) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_le) \ - GEN_ATOMIC_HELPER(NAME, uint32_t, l_be) + GEN_ATOMIC_HELPER(NAME, uint32_t, w) \ + GEN_ATOMIC_HELPER(NAME, uint32_t, l) #endif =20 GEN_ATOMIC_HELPER_ALL(fetch_add) @@ -103,12 +89,9 @@ GEN_ATOMIC_HELPER_ALL(xchg) #undef GEN_ATOMIC_HELPER_ALL #undef GEN_ATOMIC_HELPER =20 -Int128 cpu_atomic_cmpxchgo_le_mmu(CPUArchState *env, vaddr addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); -Int128 cpu_atomic_cmpxchgo_be_mmu(CPUArchState *env, vaddr addr, - Int128 cmpv, Int128 newv, - MemOpIdx oi, uintptr_t retaddr); +Int128 cpu_atomic_cmpxchgo_mmu(CPUArchState *env, vaddr addr, + Int128 cmpv, Int128 newv, + MemOpIdx oi, uintptr_t retaddr); =20 uint8_t cpu_ldb_code_mmu(CPUArchState *env, vaddr addr, MemOpIdx oi, uintptr_t ra); diff --git a/target/m68k/op_helper.c b/target/m68k/op_helper.c index f29ae12af8..d138bb6742 100644 --- a/target/m68k/op_helper.c +++ b/target/m68k/op_helper.c @@ -806,13 +806,13 @@ static void do_cas2l(CPUM68KState *env, uint32_t regs= , uint32_t a1, uint32_t a2, if ((a1 & 7) =3D=3D 0 && a2 =3D=3D a1 + 4) { c =3D deposit64(c2, 32, 32, c1); u =3D deposit64(u2, 32, 32, u1); - l =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, c, u, oi, ra); + l =3D cpu_atomic_cmpxchgq_mmu(env, a1, c, u, oi, ra); l1 =3D l >> 32; l2 =3D l; } else if ((a2 & 7) =3D=3D 0 && a1 =3D=3D a2 + 4) { c =3D deposit64(c1, 32, 32, c2); u =3D deposit64(u1, 32, 32, u2); - l =3D cpu_atomic_cmpxchgq_be_mmu(env, a2, c, u, oi, ra); + l =3D cpu_atomic_cmpxchgq_mmu(env, a2, c, u, oi, ra); l2 =3D l >> 32; l1 =3D l; } else diff --git a/target/s390x/tcg/mem_helper.c b/target/s390x/tcg/mem_helper.c index f1acb1618f..996e10ece3 100644 --- a/target/s390x/tcg/mem_helper.c +++ b/target/s390x/tcg/mem_helper.c @@ -1838,7 +1838,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, uint32_t ov; =20 if (parallel) { - ov =3D cpu_atomic_cmpxchgl_be_mmu(env, a1, cv, nv, oi4, ra= ); + ov =3D cpu_atomic_cmpxchgl_mmu(env, a1, cv, nv, oi4, ra); } else { ov =3D cpu_ldl_mmu(env, a1, oi4, ra); cpu_stl_mmu(env, a1, (ov =3D=3D cv ? nv : ov), oi4, ra); @@ -1856,7 +1856,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, =20 if (parallel) { #ifdef CONFIG_ATOMIC64 - ov =3D cpu_atomic_cmpxchgq_be_mmu(env, a1, cv, nv, oi8, ra= ); + ov =3D cpu_atomic_cmpxchgq_mmu(env, a1, cv, nv, oi8, ra); #else /* Note that we asserted !parallel above. */ g_assert_not_reached(); @@ -1884,7 +1884,7 @@ static uint32_t do_csst(CPUS390XState *env, uint32_t = r3, uint64_t a1, } cpu_st16_mmu(env, a1, nv, oi16, ra); } else if (HAVE_CMPXCHG128) { - ov =3D cpu_atomic_cmpxchgo_be_mmu(env, a1, cv, nv, oi16, r= a); + ov =3D cpu_atomic_cmpxchgo_mmu(env, a1, cv, nv, oi16, ra); cc =3D !int128_eq(ov, cv); } else { /* Note that we asserted !parallel above. */ diff --git a/tcg/tcg-op-ldst.c b/tcg/tcg-op-ldst.c index 548496002d..8db45d8f0c 100644 --- a/tcg/tcg-op-ldst.c +++ b/tcg/tcg-op-ldst.c @@ -813,16 +813,12 @@ typedef void (*gen_atomic_op_i64)(TCGv_i64, TCGv_env,= TCGv_i64, # define WITH_ATOMIC128(X) #endif =20 -static void * const table_cmpxchg[(MO_SIZE | MO_BSWAP) + 1] =3D { +static void * const table_cmpxchg[MO_SIZE + 1] =3D { [MO_8] =3D gen_helper_atomic_cmpxchgb, - [MO_16 | MO_LE] =3D gen_helper_atomic_cmpxchgw_le, - [MO_16 | MO_BE] =3D gen_helper_atomic_cmpxchgw_be, - [MO_32 | MO_LE] =3D gen_helper_atomic_cmpxchgl_le, - [MO_32 | MO_BE] =3D gen_helper_atomic_cmpxchgl_be, - WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_cmpxchgq_le) - WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_cmpxchgq_be) - WITH_ATOMIC128([MO_128 | MO_LE] =3D gen_helper_atomic_cmpxchgo_le) - WITH_ATOMIC128([MO_128 | MO_BE] =3D gen_helper_atomic_cmpxchgo_be) + [MO_16] =3D gen_helper_atomic_cmpxchgw, + [MO_32] =3D gen_helper_atomic_cmpxchgl, + WITH_ATOMIC64([MO_64] =3D gen_helper_atomic_cmpxchgq) + WITH_ATOMIC128([MO_128] =3D gen_helper_atomic_cmpxchgo) }; =20 static void tcg_gen_nonatomic_cmpxchg_i32_int(TCGv_i32 retv, TCGTemp *addr, @@ -871,7 +867,7 @@ static void tcg_gen_atomic_cmpxchg_i32_int(TCGv_i32 ret= v, TCGTemp *addr, } =20 memop =3D tcg_canonicalize_memop(memop, 0, 0); - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + gen =3D table_cmpxchg[memop & MO_SIZE]; tcg_debug_assert(gen !=3D NULL); =20 oi =3D make_memop_idx(memop & ~MO_SIGN, idx); @@ -952,7 +948,7 @@ static void tcg_gen_atomic_cmpxchg_i64_int(TCGv_i64 ret= v, TCGTemp *addr, gen_atomic_cx_i64 gen; =20 memop =3D tcg_canonicalize_memop(memop, 1, 0); - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + gen =3D table_cmpxchg[memop & MO_SIZE]; if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); @@ -1074,7 +1070,7 @@ static void tcg_gen_atomic_cmpxchg_i128_int(TCGv_i128= retv, TCGTemp *addr, return; } =20 - gen =3D table_cmpxchg[memop & (MO_SIZE | MO_BSWAP)]; + gen =3D table_cmpxchg[memop & MO_SIZE]; if (gen) { MemOpIdx oi =3D make_memop_idx(memop, idx); TCGv_i64 a64 =3D maybe_extend_addr64(addr); @@ -1202,14 +1198,11 @@ static void do_atomic_op_i64(TCGv_i64 ret, TCGTemp = *addr, TCGv_i64 val, } =20 #define GEN_ATOMIC_HELPER(NAME, OP, NEW) \ -static void * const table_##NAME[(MO_SIZE | MO_BSWAP) + 1] =3D { \ +static void * const table_##NAME[MO_SIZE + 1] =3D { \ [MO_8] =3D gen_helper_atomic_##NAME##b, \ - [MO_16 | MO_LE] =3D gen_helper_atomic_##NAME##w_le, \ - [MO_16 | MO_BE] =3D gen_helper_atomic_##NAME##w_be, \ - [MO_32 | MO_LE] =3D gen_helper_atomic_##NAME##l_le, \ - [MO_32 | MO_BE] =3D gen_helper_atomic_##NAME##l_be, \ - WITH_ATOMIC64([MO_64 | MO_LE] =3D gen_helper_atomic_##NAME##q_le) \ - WITH_ATOMIC64([MO_64 | MO_BE] =3D gen_helper_atomic_##NAME##q_be) \ + [MO_16] =3D gen_helper_atomic_##NAME##w, \ + [MO_32] =3D gen_helper_atomic_##NAME##l, \ + WITH_ATOMIC64([MO_64] =3D gen_helper_atomic_##NAME##q) \ }; \ void tcg_gen_atomic_##NAME##_i32_chk(TCGv_i32 ret, TCGTemp *addr, \ TCGv_i32 val, TCGArg idx, \ --=20 2.47.2 From nobody Sat Nov 15 03:13:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 21 Aug 2025 14:33:52 +0300 (MSK) Received: by mail-nwsmtp-smtp-production-main-95.iva.yp-c.yandex.net (smtp/Yandex) with ESMTPSA id mXRF5KIMdSw0-drlzVLBJ; Thu, 21 Aug 2025 14:33:51 +0300 X-Yandex-Fwd: 1 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=yandex.ru; s=mail; t=1755776031; bh=S5qocysp9rn6PF15wrmedXeRPPht07oTCPHs/xiDtnk=; h=Message-ID:Date:In-Reply-To:Cc:Subject:References:To:From; b=fnTxfGaAQM4fJ+PAvWsS1wK3dszZltTUMkLiwNhBVKYTUiR/BssEYDeBQjYqiw97b zL3mXLEPjaDTBq7ViEWBaMF968xiUMYYohbuPR36L14jsL33JUO2KK65LNBJUtLTGG xQnAZDwItk4HxA4JBo2ymLOzxNCOOVH4D61/F3N8= Authentication-Results: mail-nwsmtp-smtp-production-main-95.iva.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Danila Zhebryakov To: qemu-devel@nongnu.org Cc: Chinmay Rath , Nicholas Piggin , Riku Voipio , Ilya Leoshkevich , qemu-ppc@nongnu.org, Paolo Bonzini , David Hildenbrand , qemu-s390x@nongnu.org, Laurent Vivier , Thomas Huth , Richard Henderson , Danila Zhebryakov Subject: [PATCH 2/3] target/ppc: Add support for LE pages on PowerPC booke206 mmu Date: Thu, 21 Aug 2025 14:33:46 +0300 Message-ID: <20250821113348.91339-3-d.zhebryakov@yandex.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250821113348.91339-1-d.zhebryakov@yandex.ru> References: <20250821113348.91339-1-d.zhebryakov@yandex.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a02:6b8:c0e:500:1:45:d181:d102; envelope-from=d.zhebryakov@yandex.ru; helo=forward102a.mail.yandex.net X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, T_SPF_TEMPERROR=0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 21 Aug 2025 09:26:25 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @yandex.ru) X-ZM-MESSAGEID: 1755782863864116600 Content-Type: text/plain; charset="utf-8" Add support for passing TLB_BSWAP flag from powerpc booke206 MMU Fix instruction fetches from LE pages being treated as MMIO This change should not affect SPARC, as its instruction fetches are always = BE Signed-off-by: Danila Zhebryakov --- accel/tcg/cputlb.c | 12 +++++------- target/ppc/cpu.h | 4 ++++ target/ppc/mmu-booke.c | 5 +++++ target/ppc/mmu_helper.c | 17 +++++++++++++++-- target/ppc/translate.c | 29 ++++++++++++++++++++++++++++- 5 files changed, 57 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 841b54e41d..396e510f1b 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -1401,7 +1401,8 @@ static int probe_access_internal(CPUState *cpu, vaddr= addr, flags |=3D full->slow_flags[access_type]; =20 /* Fold all "mmio-like" bits into TLB_MMIO. This is not RAM. */ - if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY | TLB_CHECK_ALIGN= ED)) + if (unlikely(flags & ~(TLB_WATCHPOINT | TLB_NOTDIRTY + | TLB_CHECK_ALIGNED | TLB_BSWAP)) || (access_type !=3D MMU_INST_FETCH && force_mmio)) { *phost =3D NULL; return TLB_MMIO; @@ -1792,12 +1793,9 @@ static bool mmu_lookup(CPUState *cpu, vaddr addr, Me= mOpIdx oi, mmu_watch_or_dirty(cpu, &l->page[1], type, ra); } =20 - /* - * Since target/sparc is the only user of TLB_BSWAP, and all - * Sparc accesses are aligned, any treatment across two pages - * would be arbitrary. Refuse it until there's a use. - */ - tcg_debug_assert((flags & TLB_BSWAP) =3D=3D 0); + if (unlikely(flags & TLB_BSWAP)) { + l->memop ^=3D MO_BSWAP; + } } =20 return crosspage; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 6b90543811..127b05c865 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1186,6 +1186,10 @@ struct ppc_radix_page_info { uint32_t entries[PPC_PAGE_SIZES_MAX_SZ]; }; =20 +/*************************************************************************= ****/ +/* PowerPC usage of the PAGE_TARGET_1 bit for TLB little-endian bit */ +#define PAGE_LE PAGE_TARGET_1 + /*************************************************************************= ****/ /* Dynamic Execution Control Register */ =20 diff --git a/target/ppc/mmu-booke.c b/target/ppc/mmu-booke.c index 55e5dd7c6b..dc72bbf21f 100644 --- a/target/ppc/mmu-booke.c +++ b/target/ppc/mmu-booke.c @@ -357,6 +357,11 @@ found_tlb: } =20 *prot =3D 0; + + if (tlb->mas2 & MAS2_E) { + *prot |=3D PAGE_LE; + } + if (pr) { if (tlb->mas7_3 & MAS3_UR) { *prot |=3D PAGE_READ; diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index ac60705402..20282edaaa 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -27,6 +27,7 @@ #include "exec/cputlb.h" #include "exec/page-protection.h" #include "exec/target_page.h" +#include "exec/tlb-flags.h" #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" @@ -1368,8 +1369,20 @@ bool ppc_cpu_tlb_fill(CPUState *cs, vaddr eaddr, int= size, =20 if (ppc_xlate(cpu, eaddr, access_type, &raddr, &page_size, &prot, mmu_idx, !probe)) { - tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE_MAS= K, - prot, mmu_idx, 1UL << page_size); + if (prot & PAGE_LE) { + CPUTLBEntryFull full =3D { + .phys_addr =3D raddr & TARGET_PAGE_MASK, + .attrs =3D MEMTXATTRS_UNSPECIFIED, + .prot =3D prot, + .lg_page_size =3D ctz64(1UL << page_size), + .tlb_fill_flags =3D TLB_BSWAP + }; + tlb_set_page_full(cs, mmu_idx, eaddr & TARGET_PAGE_MASK, &full= ); + + } else { + tlb_set_page(cs, eaddr & TARGET_PAGE_MASK, raddr & TARGET_PAGE= _MASK, + prot, mmu_idx, 1UL << page_size); + } return true; } if (probe) { diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 27f90c3cc5..8cf50a0221 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -24,7 +24,9 @@ #include "exec/target_page.h" #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" +#include "accel/tcg/probe.h" #include "qemu/host-utils.h" +#include "exec/tlb-flags.h" =20 #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -219,6 +221,27 @@ static inline bool need_byteswap(const DisasContext *c= tx) #endif } =20 +#ifndef CONFIG_USER_ONLY +static bool is_page_little_endian(CPUPPCState *env, vaddr addr) +{ + CPUTLBEntryFull *full; + void *host; + int mmu_idx =3D ppc_env_mmu_index(env, true); + int flags; + + flags =3D probe_access_full_mmu(env, addr, 0, MMU_INST_FETCH, mmu_idx, + &host, &full); + assert(!(flags & TLB_INVALID_MASK)); + + return full->tlb_fill_flags & TLB_BSWAP; +} +#else +static bool is_page_little_endian(CPUPPCState *env, vaddr addr) +{ + return false; +} +#endif + /* True when active word size < size of target_long. */ #ifdef TARGET_PPC64 # define NARROW_MODE(C) (!(C)->sf_mode) @@ -6577,7 +6600,11 @@ static void ppc_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) ctx->base.pc_next, ctx->mem_idx, (int)msr_ir); =20 ctx->cia =3D pc =3D ctx->base.pc_next; - insn =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx)); + bool tlb_is_le =3D is_page_little_endian(env, ctx->base.pc_next); + + + insn =3D translator_ldl_swap(env, dcbase, pc, need_byteswap(ctx) + || tlb_is_le); ctx->base.pc_next =3D pc +=3D 4; =20 if (!is_prefix_insn(ctx, insn)) { --=20 2.47.2 From nobody Sat Nov 15 03:13:54 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=yandex.ru ARC-Seal: i=1; a=rsa-sha256; t=1755782880; cv=none; d=zohomail.com; s=zohoarc; b=WQRpg52yx5JlEofr2OJ6YA4LS/TYnBw5SVStxnwv7/SBjdQ4phNs88RO4qgwNc1Qe8n3mfuv/UdXaDdqckgbCgkNXdCYqAKCmeRzL3uK+SbcL92RkP9Yg5mvpR8bhTSs9tKaHfErgVBaHA63JHqPDII+KKXDmD3ndAQ+8QrfSWw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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bh=GAkEQW9/oBNuV+QIcNUtxT7Jhur2BTbBORvnpc90fP4=; h=Message-ID:Date:In-Reply-To:Cc:Subject:References:To:From; b=snyOKz5VqAWrVUt+1cmuDSTg+LzvR903W2VxuVatWTZXzjUBNEAcExnPJi+GrNHhb Z0aMzeQ7m6dB+WmpL1RdSBNgzaapvls4ePNlkvIbbGzHZwXf2IzYAZmawUbv8PpKKO OVGyq0RhYAgUvPGpEjnNPcyFqHWUx4+FXzVziqKY= Authentication-Results: mail-nwsmtp-smtp-production-main-95.iva.yp-c.yandex.net; dkim=pass header.i=@yandex.ru From: Danila Zhebryakov To: qemu-devel@nongnu.org Cc: Chinmay Rath , Nicholas Piggin , Riku Voipio , Ilya Leoshkevich , qemu-ppc@nongnu.org, Paolo Bonzini , David Hildenbrand , qemu-s390x@nongnu.org, Laurent Vivier , Thomas Huth , Richard Henderson , Danila Zhebryakov Subject: [PATCH 3/3] target/ppc: fix GDB stub to work correctly with LE pages Date: Thu, 21 Aug 2025 14:33:47 +0300 Message-ID: <20250821113348.91339-4-d.zhebryakov@yandex.ru> X-Mailer: git-send-email 2.47.2 In-Reply-To: <20250821113348.91339-1-d.zhebryakov@yandex.ru> References: <20250821113348.91339-1-d.zhebryakov@yandex.ru> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a02:6b8:c02:900:1:45:d181:d102; envelope-from=d.zhebryakov@yandex.ru; helo=forward102b.mail.yandex.net X-Spam_score_int: -27 X-Spam_score: -2.8 X-Spam_bar: -- X-Spam_report: (-2.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_LOW=-0.7, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Mailman-Approved-At: Thu, 21 Aug 2025 09:26:26 -0400 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @yandex.ru) X-ZM-MESSAGEID: 1755782882337124100 Content-Type: text/plain; charset="utf-8" GDB is expected to be set to the endianness of the currently running code, = which may be in LE page. Bswap the registers accordingly. Signed-off-by: Danila Zhebryakov --- target/ppc/gdbstub.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-) diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c index 3b28d4e21c..89c783894c 100644 --- a/target/ppc/gdbstub.c +++ b/target/ppc/gdbstub.c @@ -19,6 +19,8 @@ */ #include "qemu/osdep.h" #include "cpu.h" +#include "accel/tcg/probe.h" +#include "exec/tlb-flags.h" #include "exec/gdbstub.h" #include "gdbstub/helpers.h" #include "internal.h" @@ -84,7 +86,20 @@ static int ppc_gdb_register_len(int n) void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len) { #ifndef CONFIG_USER_ONLY - if (!FIELD_EX64(env->msr, MSR, LE)) { + bool le_page =3D false; + + if (env->mmu_model =3D=3D POWERPC_MMU_BOOKE206) { + CPUTLBEntryFull *full; + void *host; + int mmu_idx =3D ppc_env_mmu_index(env, true); + + probe_access_full_mmu(env, env->nip, 0, MMU_INST_FETCH, mmu_idx, + &host, &full); + + le_page =3D full->tlb_fill_flags & TLB_BSWAP; + } + + if (!le_page && !FIELD_EX64(env->msr, MSR, LE)) { /* do nothing */ } else if (len =3D=3D 4) { bswap32s((uint32_t *)mem_buf); --=20 2.47.2