From nobody Sat Nov 15 05:35:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746128515926.0189060925031; Wed, 20 Aug 2025 20:15:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovlX-0004Bc-GU; Wed, 20 Aug 2025 23:15:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovlV-00045P-If for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:15:01 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovlS-0003gD-3C for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:15:00 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxidG9jqZovzoBAA--.2286S3; Thu, 21 Aug 2025 11:13:01 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S12; Thu, 21 Aug 2025 11:13:00 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 10/10] target/loongarch: Add bit A/D checking in TLB entry with PTW supported Date: Thu, 21 Aug 2025 11:12:56 +0800 Message-Id: <20250821031256.3451168-11-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S12 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746130386124100 Content-Type: text/plain; charset="utf-8" With read/write access, add bit A/D checking if hardware PTW is supported. If no matched, hardware page table walk is called. And then bit A/D is updated in PTE entry and TLB entry is updated also. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index e00a1fd748..b6a26cf2d3 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -648,6 +648,21 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, /* Data access */ context.addr =3D address; ret =3D get_physical_address(env, &context, access_type, mmu_idx, 0); + if (ret =3D=3D TLBRET_MATCH && context.mmu_index !=3D MMU_DA_IDX + && cpu_has_ptw(env)) { + bool need_mark =3D true; + + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(context.pte)) { + need_mark =3D false; + } else if (access_type !=3D MMU_DATA_STORE && pte_access(context.p= te)) { + need_mark =3D false; + } + + if (need_mark) { + ret =3D TLBRET_NOMATCH; + } + } + if (ret !=3D TLBRET_MATCH && cpu_has_ptw(env)) { /* Take HW PTW if TLB missed or bit P is zero */ if (ret =3D=3D TLBRET_NOMATCH || ret =3D=3D TLBRET_INVALID) { --=20 2.39.3