From nobody Sat Nov 15 05:35:48 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175574613320283.1561283000982; Wed, 20 Aug 2025 20:15:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjr-0000yO-Li; Wed, 20 Aug 2025 23:13:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjl-0000vz-OT for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjg-0003Yg-3G for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx1tC8jqZovDoBAA--.2239S3; Thu, 21 Aug 2025 11:13:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S11; Thu, 21 Aug 2025 11:13:00 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 09/10] target/loongarch: Update matched ptw bit A/D with PTW supported Date: Thu, 21 Aug 2025 11:12:55 +0800 Message-Id: <20250821031256.3451168-10-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S11 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746135638116600 Content-Type: text/plain; charset="utf-8" With hardware PTE supported, bit A will be set if there is read access or instruction fetch, and bit D will be set with write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 26 ++++++++++ target/loongarch/cpu_helper.c | 92 +++++++++++++++++++++++++++++++++-- 2 files changed, 114 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 4c227d4ef3..85d01e1bbe 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -61,6 +61,32 @@ static inline bool pte_write(CPULoongArchState *env, uin= t64_t entry) return !!writable; } =20 +/* + * The folloing functions should be called with PTW enable checked + * With hardware PTW enabled + * Bit D will be set by hardware with write access + * Bit A will be set by hardware with read/intruction fetch access + */ +static inline uint64_t pte_mkaccess(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, V, 1); +} + +static inline uint64_t pte_mkdirty(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, D, 1); +} + +static inline bool pte_access(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, V); +} + +static inline bool pte_dirty(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, D); +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index fe97f53f6d..5df433c838 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -106,16 +106,54 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MM= UContext *context, return TLBRET_MATCH; } =20 +static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys, + uint64_t old, uint64_t new) +{ + hwaddr addr1, l =3D 8; + MemoryRegion *mr; + uint8_t *ram_ptr; + uint64_t old1; + MemTxResult ret; + + rcu_read_lock(); + mr =3D address_space_translate(cs->as, phys, &addr1, &l, + false, MEMTXATTRS_UNSPECIFIED); + if (!memory_region_is_ram(mr)) { + /* + * Misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically. + */ + rcu_read_unlock(); + return MEMTX_ACCESS_ERROR; + } + + ram_ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); + old1 =3D qatomic_cmpxchg((uint64_t *)ram_ptr, cpu_to_le64(old), + cpu_to_le64(new)); + old1 =3D le64_to_cpu(old1); + if (old1 =3D=3D old) { + ret =3D MEMTX_OK; + } else { + ret =3D MEMTX_DECODE_ERROR; + } + rcu_read_unlock(); + + return ret; +} + TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, int access_type, int mmu_idx, int debug) { CPUState *cs =3D env_cpu(env); - target_ulong index, phys; + target_ulong index, phys =3D 0; uint64_t dir_base, dir_width; - uint64_t base; + uint64_t base, pte; int level; vaddr address; + TLBRet ret; + MemTxResult ret1; =20 +restart: address =3D context->addr; if ((address >> 63) & 0x1) { base =3D env->CSR_PGDH; @@ -144,6 +182,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext= *context, /* pte */ if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* Huge Page. base is pte */ + pte =3D base; base =3D FIELD_DP64(base, TLBENTRY, LEVEL, 0); base =3D FIELD_DP64(base, TLBENTRY, HUGE, 0); if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) { @@ -155,12 +194,13 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUConte= xt *context, context->pte_buddy[0] =3D base; context->pte_buddy[1] =3D base + BIT_ULL(dir_base); base +=3D (BIT_ULL(dir_base) & address); + index =3D 0; } else { /* Normal Page. base points to pte */ get_dir_base_width(env, &dir_base, &dir_width, 0); index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; - base =3D ldq_phys(cs->as, phys); + base =3D pte =3D ldq_phys(cs->as, phys); if (cpu_has_ptw(env)) { index &=3D 1; context->pte_buddy[index] =3D base; @@ -171,7 +211,51 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContex= t *context, =20 context->ps =3D dir_base; context->pte =3D base; - return loongarch_check_pte(env, context, access_type, mmu_idx); + ret =3D loongarch_check_pte(env, context, access_type, mmu_idx); + if (debug) { + return ret; + } + + /* + * Update bit A/D with hardware PTW supported + * + * Need atomic compchxg operation with pte update, other vCPUs may + * update pte at the same time. + */ + if (ret =3D=3D TLBRET_MATCH && cpu_has_ptw(env)) { + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(base)) { + return ret; + } + + if (access_type !=3D MMU_DATA_STORE && pte_access(base)) { + return ret; + } + + base =3D pte_mkaccess(pte); + if (access_type =3D=3D MMU_DATA_STORE) { + base =3D pte_mkdirty(base); + } + ret1 =3D loongarch_cmpxchg_phys(cs, phys, pte, base); + /* PTE updated by other CPU, reload PTE entry */ + if (ret1 =3D=3D MEMTX_DECODE_ERROR) { + goto restart; + } + + context->pte_buddy[index] =3D pte_mkaccess(context->pte_buddy[inde= x]); + if (access_type =3D=3D MMU_DATA_STORE) { + context->pte_buddy[index] =3D pte_mkdirty(context->pte_buddy[i= ndex]); + } + + /* Bit A/D need be updated with both Even/Odd page with huge pte */ + if (FIELD_EX64(base, TLBENTRY, HUGE)) { + context->pte_buddy[1] =3D pte_mkaccess(context->pte_buddy[1]); + if (access_type =3D=3D MMU_DATA_STORE) { + context->pte_buddy[1] =3D pte_mkdirty(context->pte_buddy[1= ]); + } + } + } + + return ret; } =20 static TLBRet loongarch_map_address(CPULoongArchState *env, --=20 2.39.3