From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746090221652.2918945921515; Wed, 20 Aug 2025 20:14:50 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjq-0000wz-8X; Wed, 20 Aug 2025 23:13:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovji-0000uF-M2 for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:10 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovje-0003Y6-0H for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:10 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8BxmdG5jqZopDoBAA--.2339S3; Thu, 21 Aug 2025 11:12:57 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S3; Thu, 21 Aug 2025 11:12:57 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 01/10] target/loongarch: Use auto method with PTW feature Date: Thu, 21 Aug 2025 11:12:47 +0800 Message-Id: <20250821031256.3451168-2-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S3 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746091145116600 Content-Type: text/plain; charset="utf-8" PTW is short for page table walker, it is hardware page table walker function. With PTW supported, hardware MMU will parse page table table and update TLB entries automatically. This patch adds type OnOffAuto for PTW feature setting. Signed-off-by: Bibo Mao --- target/loongarch/cpu.c | 22 ++++++++++++++++++++++ target/loongarch/cpu.h | 2 ++ 2 files changed, 24 insertions(+) diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 990985708e..92292e6009 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -495,12 +495,29 @@ static void loongarch_set_lasx(Object *obj, bool valu= e, Error **errp) cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, LASX, value); } =20 +static bool loongarch_get_ptw(Object *obj, Error **errp) +{ + return LOONGARCH_CPU(obj)->ptw !=3D ON_OFF_AUTO_OFF; +} + +static void loongarch_set_ptw(Object *obj, bool value, Error **errp) +{ + LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); + uint32_t val; + + cpu->ptw =3D value ? ON_OFF_AUTO_ON : ON_OFF_AUTO_OFF; + + val =3D cpu->env.cpucfg[2]; + cpu->env.cpucfg[2] =3D FIELD_DP32(val, CPUCFG2, HPTW, value); +} + static void loongarch_cpu_post_init(Object *obj) { LoongArchCPU *cpu =3D LOONGARCH_CPU(obj); =20 cpu->lbt =3D ON_OFF_AUTO_OFF; cpu->pmu =3D ON_OFF_AUTO_OFF; + cpu->ptw =3D ON_OFF_AUTO_OFF; cpu->lsx =3D ON_OFF_AUTO_AUTO; cpu->lasx =3D ON_OFF_AUTO_AUTO; object_property_add_bool(obj, "lsx", loongarch_get_lsx, @@ -508,6 +525,11 @@ static void loongarch_cpu_post_init(Object *obj) object_property_add_bool(obj, "lasx", loongarch_get_lasx, loongarch_set_lasx); /* lbt is enabled only in kvm mode, not supported in tcg mode */ + if (tcg_enabled()) { + object_property_add_bool(obj, "ptw", loongarch_get_ptw, + loongarch_set_ptw); + } + if (kvm_enabled()) { kvm_loongarch_cpu_post_init(cpu); } diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h index 3c5fcaa154..76e42f6d4e 100644 --- a/target/loongarch/cpu.h +++ b/target/loongarch/cpu.h @@ -158,6 +158,7 @@ FIELD(CPUCFG2, LBT_MIPS, 20, 1) FIELD(CPUCFG2, LBT_ALL, 18, 3) FIELD(CPUCFG2, LSPW, 21, 1) FIELD(CPUCFG2, LAM, 22, 1) +FIELD(CPUCFG2, HPTW, 24, 1) =20 /* cpucfg[3] bits */ FIELD(CPUCFG3, CCDMA, 0, 1) @@ -429,6 +430,7 @@ struct ArchCPU { uint32_t phy_id; OnOffAuto lbt; OnOffAuto pmu; + OnOffAuto ptw; OnOffAuto lsx; OnOffAuto lasx; OnOffAuto kvm_pv_ipi; --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746050830988.1257139318947; Wed, 20 Aug 2025 20:14:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjq-0000x5-L6; Wed, 20 Aug 2025 23:13:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjl-0000vy-EA for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjd-0003Y5-UR for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxK9K6jqZopzoBAA--.1303S3; Thu, 21 Aug 2025 11:12:58 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S4; Thu, 21 Aug 2025 11:12:57 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 02/10] target/loongarch: Add CSR_PWCH write helper function Date: Thu, 21 Aug 2025 11:12:48 +0800 Message-Id: <20250821031256.3451168-3-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S4 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746054884124100 Content-Type: text/plain; charset="utf-8" Bit HPTW_EN in register CSR_PWCH controls enabling hardware page table walker feature when PTW feature is enabled. Otherwise it is reserved bit. Here add register CSR_PWCH write helper function. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 2 ++ target/loongarch/tcg/csr_helper.c | 15 +++++++++++++++ target/loongarch/tcg/helper.h | 1 + .../tcg/insn_trans/trans_privileged.c.inc | 1 + 4 files changed, 19 insertions(+) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 0834e91f30..043b2f14b9 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -103,6 +103,8 @@ FIELD(CSR_PWCH, DIR3_BASE, 0, 6) FIELD(CSR_PWCH, DIR3_WIDTH, 6, 6) FIELD(CSR_PWCH, DIR4_BASE, 12, 6) FIELD(CSR_PWCH, DIR4_WIDTH, 18, 6) +FIELD(CSR_PWCH, HPTW_EN, 24, 1) +FIELD(CSR_PWCH, RESERVE, 25, 7) =20 #define LOONGARCH_CSR_STLBPS 0x1e /* Stlb page size */ FIELD(CSR_STLBPS, PS, 0, 5) diff --git a/target/loongarch/tcg/csr_helper.c b/target/loongarch/tcg/csr_h= elper.c index 4433167332..8c7168034e 100644 --- a/target/loongarch/tcg/csr_helper.c +++ b/target/loongarch/tcg/csr_helper.c @@ -141,3 +141,18 @@ target_ulong helper_csrwr_pwcl(CPULoongArchState *env,= target_ulong val) env->CSR_PWCL =3D val; return old_v; } + +target_ulong helper_csrwr_pwch(CPULoongArchState *env, target_ulong val) +{ + uint8_t has_ptw; + int64_t old_v =3D env->CSR_PWCH; + + val =3D FIELD_DP64(val, CSR_PWCH, RESERVE, 0); + has_ptw =3D FIELD_EX32(env->cpucfg[2], CPUCFG2, HPTW); + if (!has_ptw) { + val =3D FIELD_DP64(val, CSR_PWCH, HPTW_EN, 0); + } + + env->CSR_PWCH =3D val; + return old_v; + } diff --git a/target/loongarch/tcg/helper.h b/target/loongarch/tcg/helper.h index 1d5cb0198c..0f62119987 100644 --- a/target/loongarch/tcg/helper.h +++ b/target/loongarch/tcg/helper.h @@ -106,6 +106,7 @@ DEF_HELPER_2(csrwr_asid, i64, env, tl) DEF_HELPER_2(csrwr_tcfg, i64, env, tl) DEF_HELPER_2(csrwr_ticlr, i64, env, tl) DEF_HELPER_2(csrwr_pwcl, i64, env, tl) +DEF_HELPER_2(csrwr_pwch, i64, env, tl) DEF_HELPER_2(iocsrrd_b, i64, env, tl) DEF_HELPER_2(iocsrrd_h, i64, env, tl) DEF_HELPER_2(iocsrrd_w, i64, env, tl) diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/targe= t/loongarch/tcg/insn_trans/trans_privileged.c.inc index ecbfe23b63..224f98c5fb 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -79,6 +79,7 @@ void loongarch_csr_translate_init(void) SET_CSR_FUNC(ASID, NULL, gen_helper_csrwr_asid); SET_CSR_FUNC(PGD, gen_helper_csrrd_pgd, NULL); SET_CSR_FUNC(PWCL, NULL, gen_helper_csrwr_pwcl); + SET_CSR_FUNC(PWCH, NULL, gen_helper_csrwr_pwch); SET_CSR_FUNC(CPUID, gen_helper_csrrd_cpuid, NULL); SET_CSR_FUNC(TCFG, NULL, gen_helper_csrwr_tcfg); SET_CSR_FUNC(TVAL, gen_helper_csrrd_tval, NULL); --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746142372980.0805731190618; Wed, 20 Aug 2025 20:15:42 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjs-0000zA-Ga; Wed, 20 Aug 2025 23:13:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjk-0000vm-CC for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovje-0003Y9-DR for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:12 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Axjr+6jqZoqjoBAA--.1246S3; Thu, 21 Aug 2025 11:12:58 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S5; Thu, 21 Aug 2025 11:12:58 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 03/10] target/loongarch: Add present and write bit with pte entry Date: Thu, 21 Aug 2025 11:12:49 +0800 Message-Id: <20250821031256.3451168-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746143939124100 Content-Type: text/plain; charset="utf-8" With hardware PTW feature enabled, Present) bit and Write bit is checked by hardware, rather Valid bit and Dirty bit. Bit P means that the page is valid and present, and bit W means that the page is writable. The original V bit is treated as access bit, hardware sets this bit if there is read or write access. Bit D bit is updated by hardware if there is write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-csr.h | 2 ++ target/loongarch/cpu-mmu.h | 31 +++++++++++++++++++++++++++++++ target/loongarch/cpu_helper.c | 4 ++-- target/loongarch/tcg/tlb_helper.c | 14 +++++++------- 4 files changed, 42 insertions(+), 9 deletions(-) diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h index 043b2f14b9..345a51d04a 100644 --- a/target/loongarch/cpu-csr.h +++ b/target/loongarch/cpu-csr.h @@ -68,6 +68,8 @@ FIELD(TLBENTRY, PLV, 2, 2) FIELD(TLBENTRY, MAT, 4, 2) FIELD(TLBENTRY, G, 6, 1) FIELD(TLBENTRY, HUGE, 6, 1) +FIELD(TLBENTRY, P, 7, 1) +FIELD(TLBENTRY, W, 8, 1) FIELD(TLBENTRY, HGLOBAL, 12, 1) FIELD(TLBENTRY, LEVEL, 13, 2) FIELD(TLBENTRY_32, PPN, 8, 24) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 311bf7b2d7..e4f3199f44 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -29,6 +29,37 @@ typedef struct MMUContext { int mmu_index; } MMUContext; =20 +static inline bool cpu_has_ptw(CPULoongArchState *env) +{ + return !!FIELD_EX64(env->CSR_PWCH, CSR_PWCH, HPTW_EN); +} + +static inline bool pte_present(CPULoongArchState *env, uint64_t entry) +{ + uint8_t present; + + if (cpu_has_ptw(env)) { + present =3D FIELD_EX64(entry, TLBENTRY, P); + } else { + present =3D FIELD_EX64(entry, TLBENTRY, V); + } + + return !!present; +} + +static inline bool pte_write(CPULoongArchState *env, uint64_t entry) +{ + uint8_t writable; + + if (cpu_has_ptw(env)) { + writable =3D FIELD_EX64(entry, TLBENTRY, W); + } else { + writable =3D FIELD_EX64(entry, TLBENTRY, D); + } + + return !!writable; +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 6572d0a7cc..2e07049425 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -53,8 +53,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUCon= text *context, =20 tlb_entry =3D context->pte; tlb_ps =3D context->ps; - tlb_v =3D FIELD_EX64(tlb_entry, TLBENTRY, V); - tlb_d =3D FIELD_EX64(tlb_entry, TLBENTRY, D); + tlb_v =3D pte_present(env, tlb_entry); + tlb_d =3D pte_write(env, tlb_entry); tlb_plv =3D FIELD_EX64(tlb_entry, TLBENTRY, PLV); if (is_la64(env)) { tlb_ppn =3D FIELD_EX64(tlb_entry, TLBENTRY_64, PPN); diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 7a4de7e566..10c01ead3f 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -119,11 +119,9 @@ static void raise_mmu_exception(CPULoongArchState *env= , vaddr address, static void invalidate_tlb_entry(CPULoongArchState *env, int index) { target_ulong addr, mask, pagesize; - uint8_t tlb_ps; + uint8_t tlb_ps, tlb_v; LoongArchTLB *tlb =3D &env->tlb[index]; int mmu_idx; - uint8_t tlb_v0 =3D FIELD_EX64(tlb->tlb_entry0, TLBENTRY, V); - uint8_t tlb_v1 =3D FIELD_EX64(tlb->tlb_entry1, TLBENTRY, V); uint64_t tlb_vppn =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, VPPN); uint8_t tlb_e =3D FIELD_EX64(tlb->tlb_misc, TLB_MISC, E); =20 @@ -137,7 +135,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) addr =3D (tlb_vppn << R_TLB_MISC_VPPN_SHIFT) & ~mask; addr =3D sextract64(addr, 0, TARGET_VIRT_ADDR_SPACE_BITS); =20 - if (tlb_v0) { + tlb_v =3D pte_present(env, tlb->tlb_entry0); + if (tlb_v) { mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry0, TLBENTRY, PLV)); /* Even page is accessed in kernel mode */ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW0) { @@ -147,7 +146,8 @@ static void invalidate_tlb_entry(CPULoongArchState *env= , int index) mmu_idx, TARGET_LONG_BITS); } =20 - if (tlb_v1) { + tlb_v =3D pte_present(env, tlb->tlb_entry1); + if (tlb_v) { mmu_idx =3D BIT(FIELD_EX64(tlb->tlb_entry1, TLBENTRY, PLV)); /* Odd page is accessed in kernel mode */ if (tlb->tlb_misc & TLB_MISC_KM_PTE_LOW1) { @@ -362,8 +362,8 @@ void helper_tlbwr(CPULoongArchState *env) /* Check whether ASID/VPPN is the same */ if (old->tlb_misc =3D=3D new.tlb_misc) { /* Check whether pte is the same or invalid */ - tlb_v0 =3D FIELD_EX64(old->tlb_entry0, TLBENTRY, V); - tlb_v1 =3D FIELD_EX64(old->tlb_entry1, TLBENTRY, V); + tlb_v0 =3D pte_present(env, old->tlb_entry0); + tlb_v1 =3D pte_present(env, old->tlb_entry1); if ((!tlb_v0 || new.tlb_entry0 =3D=3D old->tlb_entry0) && (!tlb_v1 || new.tlb_entry1 =3D=3D old->tlb_entry1)) { skip_inv =3D true; --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746105085842.2500505832313; Wed, 20 Aug 2025 20:15:05 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjr-0000ya-Q5; Wed, 20 Aug 2025 23:13:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjj-0000uJ-1X for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:11 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovje-0003YB-0X for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:10 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx37+7jqZorToBAA--.1256S3; Thu, 21 Aug 2025 11:12:59 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S6; Thu, 21 Aug 2025 11:12:58 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 04/10] target/loongarch: Add function sptw_prepare_tlb before adding tlb entry Date: Thu, 21 Aug 2025 11:12:50 +0800 Message-Id: <20250821031256.3451168-5-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S6 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746107394124100 Content-Type: text/plain; charset="utf-8" With software page table walker, tlb entry comes from CSR registers. however with hardware page table walker, tlb entry comes from page table entry information directly, TLB CSR registers are not necessary. Here add function sptw_prepare_context(), get tlb entry information from TLB CSR registers. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 1 + target/loongarch/tcg/tlb_helper.c | 37 ++++++++++++++++++++----------- 2 files changed, 25 insertions(+), 13 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index e4f3199f44..c3e869234a 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -27,6 +27,7 @@ typedef struct MMUContext { int prot; int tlb_index; int mmu_index; + uint64_t pte_buddy[2]; } MMUContext; =20 static inline bool cpu_has_ptw(CPULoongArchState *env) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 10c01ead3f..fa216b92fd 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -174,42 +174,53 @@ static void invalidate_tlb(CPULoongArchState *env, in= t index) tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 0); } =20 -static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +/* Prepare tlb entry information in software PTW mode */ +static void sptw_prepare_context(CPULoongArchState *env, MMUContext *conte= xt) { - uint64_t lo0, lo1, csr_vppn; - uint16_t csr_asid; - uint8_t csr_ps; + uint64_t csr_vppn; =20 if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - csr_ps =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + context->ps =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); if (is_la64(env)) { csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN= ); } else { csr_vppn =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN= ); } - lo0 =3D env->CSR_TLBRELO0; - lo1 =3D env->CSR_TLBRELO1; + context->pte_buddy[0] =3D env->CSR_TLBRELO0; + context->pte_buddy[1] =3D env->CSR_TLBRELO1; } else { - csr_ps =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + context->ps =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); if (is_la64(env)) { csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN); } else { csr_vppn =3D FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN); } - lo0 =3D env->CSR_TLBELO0; - lo1 =3D env->CSR_TLBELO1; + context->pte_buddy[0] =3D env->CSR_TLBELO0; + context->pte_buddy[1] =3D env->CSR_TLBELO1; } =20 + context->addr =3D csr_vppn << R_TLB_MISC_VPPN_SHIFT; +} + +static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +{ + uint64_t csr_vppn; + uint16_t csr_asid; + MMUContext context; + + sptw_prepare_context(env, &context); + csr_vppn =3D context.addr >> R_TLB_MISC_VPPN_SHIFT; + /* Store page size in field PS */ tlb->tlb_misc =3D 0; - tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, csr_ps); + tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, context.ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid); =20 - tlb->tlb_entry0 =3D lo0; - tlb->tlb_entry1 =3D lo1; + tlb->tlb_entry0 =3D context.pte_buddy[0]; + tlb->tlb_entry1 =3D context.pte_buddy[1]; } =20 /* Return an random value between low and high */ --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746050224977.8962564739551; Wed, 20 Aug 2025 20:14:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjj-0000u6-CA; Wed, 20 Aug 2025 23:13:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjh-0000td-6T for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:09 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjd-0003YA-W9 for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:08 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx+tG7jqZosDoBAA--.2324S3; Thu, 21 Aug 2025 11:12:59 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S7; Thu, 21 Aug 2025 11:12:59 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 05/10] target/loongarch: Add common function get_tlb_random_index() Date: Thu, 21 Aug 2025 11:12:51 +0800 Message-Id: <20250821031256.3451168-6-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S7 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746053420116600 Content-Type: text/plain; charset="utf-8" With software PTW system, tlb index is calculated randomly when new TLB entry is added. For hardware PTW, it is the same logic to add new TLB entry. Here common function get_tlb_random_index() is added to get random tlb index when adding new TLB entry. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 39 +++++++++++++++++++------------ 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index fa216b92fd..67b8f95849 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -390,31 +390,21 @@ void helper_tlbwr(CPULoongArchState *env) old->tlb_entry1 =3D new.tlb_entry1; } =20 -void helper_tlbfill(CPULoongArchState *env) +static int get_tlb_random_index(CPULoongArchState *env, vaddr addr, int ps) { - uint64_t address, entryhi; + vaddr address; int index, set, i, stlb_idx; - uint16_t pagesize, stlb_ps; + uint16_t stlb_ps; uint16_t asid, tlb_asid; LoongArchTLB *tlb; uint8_t tlb_e; =20 - if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { - entryhi =3D env->CSR_TLBREHI; - /* Validity of pagesize is checked in helper_ldpte() */ - pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); - } else { - entryhi =3D env->CSR_TLBEHI; - /* Validity of pagesize is checked in helper_tlbrd() */ - pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); - } - /* Validity of stlb_ps is checked in helper_csrwr_stlbps() */ stlb_ps =3D FIELD_EX64(env->CSR_STLBPS, CSR_STLBPS, PS); asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); - if (pagesize =3D=3D stlb_ps) { + if (ps =3D=3D stlb_ps) { /* Only write into STLB bits [47:13] */ - address =3D entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHI= FT); + address =3D addr & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT); set =3D -1; stlb_idx =3D (address >> (stlb_ps + 1)) & 0xff; /* [0,255] */ for (i =3D 0; i < 8; ++i) { @@ -459,6 +449,25 @@ void helper_tlbfill(CPULoongArchState *env) } } =20 + return index; +} + +void helper_tlbfill(CPULoongArchState *env) +{ + uint64_t entryhi; + int index, pagesize; + + if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { + entryhi =3D env->CSR_TLBREHI; + /* Validity of pagesize is checked in helper_ldpte() */ + pagesize =3D FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS); + } else { + entryhi =3D env->CSR_TLBEHI; + /* Validity of pagesize is checked in helper_tlbrd() */ + pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); + } + + index =3D get_tlb_random_index(env, entryhi, pagesize); invalidate_tlb(env, index); fill_tlb_entry(env, env->tlb + index); } --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746051066816.6715682397062; Wed, 20 Aug 2025 20:14:11 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjq-0000xO-QD; Wed, 20 Aug 2025 23:13:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjk-0000vb-8K for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovje-0003YV-6N for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:11 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Dx+tG7jqZoszoBAA--.2327S3; Thu, 21 Aug 2025 11:12:59 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S8; Thu, 21 Aug 2025 11:12:59 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 06/10] target/loongarch: Add MMUContext parameter in fill_tlb_entry() Date: Thu, 21 Aug 2025 11:12:52 +0800 Message-Id: <20250821031256.3451168-7-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S8 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746054928124100 Content-Type: text/plain; charset="utf-8" Function fill_tlb_entry() can be used with hardware PTW in future, here add input parameter MMUContext in fill_tlb_entry(). Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 21 ++++++++++++--------- 1 file changed, 12 insertions(+), 9 deletions(-) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 67b8f95849..50c7583c6c 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -202,25 +202,24 @@ static void sptw_prepare_context(CPULoongArchState *e= nv, MMUContext *context) context->addr =3D csr_vppn << R_TLB_MISC_VPPN_SHIFT; } =20 -static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb) +static void fill_tlb_entry(CPULoongArchState *env, LoongArchTLB *tlb, + MMUContext *context) { uint64_t csr_vppn; uint16_t csr_asid; - MMUContext context; =20 - sptw_prepare_context(env, &context); - csr_vppn =3D context.addr >> R_TLB_MISC_VPPN_SHIFT; + csr_vppn =3D context->addr >> R_TLB_MISC_VPPN_SHIFT; =20 /* Store page size in field PS */ tlb->tlb_misc =3D 0; - tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, context.ps); + tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, PS, context->ps); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, VPPN, csr_vppn); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, E, 1); csr_asid =3D FIELD_EX64(env->CSR_ASID, CSR_ASID, ASID); tlb->tlb_misc =3D FIELD_DP64(tlb->tlb_misc, TLB_MISC, ASID, csr_asid); =20 - tlb->tlb_entry0 =3D context.pte_buddy[0]; - tlb->tlb_entry1 =3D context.pte_buddy[1]; + tlb->tlb_entry0 =3D context->pte_buddy[0]; + tlb->tlb_entry1 =3D context->pte_buddy[1]; } =20 /* Return an random value between low and high */ @@ -359,6 +358,7 @@ void helper_tlbwr(CPULoongArchState *env) LoongArchTLB *old, new; bool skip_inv =3D false; uint8_t tlb_v0, tlb_v1; + MMUContext context; =20 old =3D env->tlb + index; if (FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, NE)) { @@ -366,10 +366,11 @@ void helper_tlbwr(CPULoongArchState *env) return; } =20 + sptw_prepare_context(env, &context); new.tlb_misc =3D 0; new.tlb_entry0 =3D 0; new.tlb_entry1 =3D 0; - fill_tlb_entry(env, &new); + fill_tlb_entry(env, &new, &context); /* Check whether ASID/VPPN is the same */ if (old->tlb_misc =3D=3D new.tlb_misc) { /* Check whether pte is the same or invalid */ @@ -456,6 +457,7 @@ void helper_tlbfill(CPULoongArchState *env) { uint64_t entryhi; int index, pagesize; + MMUContext context; =20 if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) { entryhi =3D env->CSR_TLBREHI; @@ -467,9 +469,10 @@ void helper_tlbfill(CPULoongArchState *env) pagesize =3D FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS); } =20 + sptw_prepare_context(env, &context); index =3D get_tlb_random_index(env, entryhi, pagesize); invalidate_tlb(env, index); - fill_tlb_entry(env, env->tlb + index); + fill_tlb_entry(env, env->tlb + index, &context); } =20 void helper_tlbclr(CPULoongArchState *env) --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746049706255.62655209164643; Wed, 20 Aug 2025 20:14:09 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjp-0000wy-P5; Wed, 20 Aug 2025 23:13:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovji-0000uG-Nn for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:10 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovje-0003YN-09 for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:10 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxP_C8jqZotjoBAA--.2408S3; Thu, 21 Aug 2025 11:13:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S9; Thu, 21 Aug 2025 11:12:59 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 07/10] target/loongarch: Add debug parameter with loongarch_page_table_walker() Date: Thu, 21 Aug 2025 11:12:53 +0800 Message-Id: <20250821031256.3451168-8-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S9 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746053460116600 Content-Type: text/plain; charset="utf-8" Add debug parameter with function loongarch_page_table_walker(), in debug mode it is only to get physical address. And It used in future HW PTW usage, bit dirty and access will be updated in HW PTW mode. Also function loongarch_page_table_walker() is renamed as loongarch_ptw() for short. Signed-off-by: Bibo Mao --- target/loongarch/cpu_helper.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 2e07049425..5488d2d871 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -106,9 +106,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUC= ontext *context, return TLBRET_MATCH; } =20 -static TLBRet loongarch_page_table_walker(CPULoongArchState *env, - MMUContext *context, - int access_type, int mmu_idx) +static TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, + int access_type, int mmu_idx, int debug) { CPUState *cs =3D env_cpu(env); target_ulong index, phys; @@ -184,7 +183,7 @@ static TLBRet loongarch_map_address(CPULoongArchState *= env, * legal mapping, even if the mapping is not yet in TLB. return 0 = if * there is a valid map, else none zero. */ - return loongarch_page_table_walker(env, context, access_type, mmu_= idx); + return loongarch_ptw(env, context, access_type, mmu_idx, is_debug); } =20 return TLBRET_NOMATCH; --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746053521997.3470764285795; Wed, 20 Aug 2025 20:14:13 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjr-0000y9-8d; Wed, 20 Aug 2025 23:13:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjk-0000vr-JF for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovje-0003YZ-7D for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:12 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8CxHvC8jqZouToBAA--.2397S3; Thu, 21 Aug 2025 11:13:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S10; Thu, 21 Aug 2025 11:13:00 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 08/10] target/loongarch: Add basic hardware PTW support Date: Thu, 21 Aug 2025 11:12:54 +0800 Message-Id: <20250821031256.3451168-9-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S10 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746054951124100 Content-Type: text/plain; charset="utf-8" With software PTW, there is TLB refill exception if there is TLB miss. However with hardware PTW supported, hardware will search page table with TLB miss. Also if Present bit is not set, hardware PTW will take, it is used in odd/even TLB entry. For example in the first time odd TLB entry is valid and even TLB entry is 0. When software accesses with address from even page, there is no TLB miss only that TLB entry is 0. In this condition, hardwre PTW will happen also. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 2 ++ target/loongarch/cpu_helper.c | 15 +++++++++++++-- target/loongarch/tcg/tlb_helper.c | 26 ++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index c3e869234a..4c227d4ef3 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -67,6 +67,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUCon= text *context, TLBRet get_physical_address(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx, int is_debug); +TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, + int access_type, int mmu_idx, int debug); void get_dir_base_width(CPULoongArchState *env, uint64_t *dir_base, uint64_t *dir_width, target_ulong level); hwaddr loongarch_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index 5488d2d871..fe97f53f6d 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -106,8 +106,8 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MMUC= ontext *context, return TLBRET_MATCH; } =20 -static TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, - int access_type, int mmu_idx, int debug) +TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, + int access_type, int mmu_idx, int debug) { CPUState *cs =3D env_cpu(env); target_ulong index, phys; @@ -150,12 +150,23 @@ static TLBRet loongarch_ptw(CPULoongArchState *env, M= MUContext *context, base =3D FIELD_DP64(base, TLBENTRY, HGLOBAL, 0); base =3D FIELD_DP64(base, TLBENTRY, G, 1); } + + dir_base -=3D 1; + context->pte_buddy[0] =3D base; + context->pte_buddy[1] =3D base + BIT_ULL(dir_base); + base +=3D (BIT_ULL(dir_base) & address); } else { /* Normal Page. base points to pte */ get_dir_base_width(env, &dir_base, &dir_width, 0); index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; base =3D ldq_phys(cs->as, phys); + if (cpu_has_ptw(env)) { + index &=3D 1; + context->pte_buddy[index] =3D base; + context->pte_buddy[1 - index] =3D ldq_phys(cs->as, + phys + 8 * (1 - 2 * index)); + } } =20 context->ps =3D dir_base; diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index 50c7583c6c..e00a1fd748 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -621,6 +621,20 @@ static inline void tlb_set_accessed(CPULoongArchState = *env, vaddr address, tlb->tlb_misc |=3D TLB_MISC_KM_PTE(n); } =20 +static void ptw_update_tlb(CPULoongArchState *env, MMUContext *context) +{ + int index; + bool match; + + match =3D loongarch_tlb_search(env, context->addr, &index); + if (!match) { + index =3D get_tlb_random_index(env, context->addr, context->ps); + } + + invalidate_tlb(env, index); + fill_tlb_entry(env, env->tlb + index, context); +} + bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) @@ -634,6 +648,18 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, /* Data access */ context.addr =3D address; ret =3D get_physical_address(env, &context, access_type, mmu_idx, 0); + if (ret !=3D TLBRET_MATCH && cpu_has_ptw(env)) { + /* Take HW PTW if TLB missed or bit P is zero */ + if (ret =3D=3D TLBRET_NOMATCH || ret =3D=3D TLBRET_INVALID) { + ret =3D loongarch_ptw(env, &context, access_type, mmu_idx, 0); + if (ret =3D=3D TLBRET_MATCH) { + ptw_update_tlb(env, &context); + } + } else { + invalidate_tlb(env, context.tlb_index); + } + } + if (ret =3D=3D TLBRET_MATCH) { physical =3D context.physical; prot =3D context.prot; --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175574613320283.1561283000982; Wed, 20 Aug 2025 20:15:33 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjr-0000yO-Li; Wed, 20 Aug 2025 23:13:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovjl-0000vz-OT for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovjg-0003Yg-3G for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:13:13 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8Bx1tC8jqZovDoBAA--.2239S3; Thu, 21 Aug 2025 11:13:00 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S11; Thu, 21 Aug 2025 11:13:00 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 09/10] target/loongarch: Update matched ptw bit A/D with PTW supported Date: Thu, 21 Aug 2025 11:12:55 +0800 Message-Id: <20250821031256.3451168-10-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S11 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746135638116600 Content-Type: text/plain; charset="utf-8" With hardware PTE supported, bit A will be set if there is read access or instruction fetch, and bit D will be set with write access. Signed-off-by: Bibo Mao --- target/loongarch/cpu-mmu.h | 26 ++++++++++ target/loongarch/cpu_helper.c | 92 +++++++++++++++++++++++++++++++++-- 2 files changed, 114 insertions(+), 4 deletions(-) diff --git a/target/loongarch/cpu-mmu.h b/target/loongarch/cpu-mmu.h index 4c227d4ef3..85d01e1bbe 100644 --- a/target/loongarch/cpu-mmu.h +++ b/target/loongarch/cpu-mmu.h @@ -61,6 +61,32 @@ static inline bool pte_write(CPULoongArchState *env, uin= t64_t entry) return !!writable; } =20 +/* + * The folloing functions should be called with PTW enable checked + * With hardware PTW enabled + * Bit D will be set by hardware with write access + * Bit A will be set by hardware with read/intruction fetch access + */ +static inline uint64_t pte_mkaccess(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, V, 1); +} + +static inline uint64_t pte_mkdirty(uint64_t entry) +{ + return FIELD_DP64(entry, TLBENTRY, D, 1); +} + +static inline bool pte_access(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, V); +} + +static inline bool pte_dirty(uint64_t entry) +{ + return !!FIELD_EX64(entry, TLBENTRY, D); +} + bool check_ps(CPULoongArchState *ent, uint8_t ps); TLBRet loongarch_check_pte(CPULoongArchState *env, MMUContext *context, MMUAccessType access_type, int mmu_idx); diff --git a/target/loongarch/cpu_helper.c b/target/loongarch/cpu_helper.c index fe97f53f6d..5df433c838 100644 --- a/target/loongarch/cpu_helper.c +++ b/target/loongarch/cpu_helper.c @@ -106,16 +106,54 @@ TLBRet loongarch_check_pte(CPULoongArchState *env, MM= UContext *context, return TLBRET_MATCH; } =20 +static MemTxResult loongarch_cmpxchg_phys(CPUState *cs, hwaddr phys, + uint64_t old, uint64_t new) +{ + hwaddr addr1, l =3D 8; + MemoryRegion *mr; + uint8_t *ram_ptr; + uint64_t old1; + MemTxResult ret; + + rcu_read_lock(); + mr =3D address_space_translate(cs->as, phys, &addr1, &l, + false, MEMTXATTRS_UNSPECIFIED); + if (!memory_region_is_ram(mr)) { + /* + * Misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically. + */ + rcu_read_unlock(); + return MEMTX_ACCESS_ERROR; + } + + ram_ptr =3D qemu_map_ram_ptr(mr->ram_block, addr1); + old1 =3D qatomic_cmpxchg((uint64_t *)ram_ptr, cpu_to_le64(old), + cpu_to_le64(new)); + old1 =3D le64_to_cpu(old1); + if (old1 =3D=3D old) { + ret =3D MEMTX_OK; + } else { + ret =3D MEMTX_DECODE_ERROR; + } + rcu_read_unlock(); + + return ret; +} + TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext *context, int access_type, int mmu_idx, int debug) { CPUState *cs =3D env_cpu(env); - target_ulong index, phys; + target_ulong index, phys =3D 0; uint64_t dir_base, dir_width; - uint64_t base; + uint64_t base, pte; int level; vaddr address; + TLBRet ret; + MemTxResult ret1; =20 +restart: address =3D context->addr; if ((address >> 63) & 0x1) { base =3D env->CSR_PGDH; @@ -144,6 +182,7 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContext= *context, /* pte */ if (FIELD_EX64(base, TLBENTRY, HUGE)) { /* Huge Page. base is pte */ + pte =3D base; base =3D FIELD_DP64(base, TLBENTRY, LEVEL, 0); base =3D FIELD_DP64(base, TLBENTRY, HUGE, 0); if (FIELD_EX64(base, TLBENTRY, HGLOBAL)) { @@ -155,12 +194,13 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUConte= xt *context, context->pte_buddy[0] =3D base; context->pte_buddy[1] =3D base + BIT_ULL(dir_base); base +=3D (BIT_ULL(dir_base) & address); + index =3D 0; } else { /* Normal Page. base points to pte */ get_dir_base_width(env, &dir_base, &dir_width, 0); index =3D (address >> dir_base) & ((1 << dir_width) - 1); phys =3D base | index << 3; - base =3D ldq_phys(cs->as, phys); + base =3D pte =3D ldq_phys(cs->as, phys); if (cpu_has_ptw(env)) { index &=3D 1; context->pte_buddy[index] =3D base; @@ -171,7 +211,51 @@ TLBRet loongarch_ptw(CPULoongArchState *env, MMUContex= t *context, =20 context->ps =3D dir_base; context->pte =3D base; - return loongarch_check_pte(env, context, access_type, mmu_idx); + ret =3D loongarch_check_pte(env, context, access_type, mmu_idx); + if (debug) { + return ret; + } + + /* + * Update bit A/D with hardware PTW supported + * + * Need atomic compchxg operation with pte update, other vCPUs may + * update pte at the same time. + */ + if (ret =3D=3D TLBRET_MATCH && cpu_has_ptw(env)) { + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(base)) { + return ret; + } + + if (access_type !=3D MMU_DATA_STORE && pte_access(base)) { + return ret; + } + + base =3D pte_mkaccess(pte); + if (access_type =3D=3D MMU_DATA_STORE) { + base =3D pte_mkdirty(base); + } + ret1 =3D loongarch_cmpxchg_phys(cs, phys, pte, base); + /* PTE updated by other CPU, reload PTE entry */ + if (ret1 =3D=3D MEMTX_DECODE_ERROR) { + goto restart; + } + + context->pte_buddy[index] =3D pte_mkaccess(context->pte_buddy[inde= x]); + if (access_type =3D=3D MMU_DATA_STORE) { + context->pte_buddy[index] =3D pte_mkdirty(context->pte_buddy[i= ndex]); + } + + /* Bit A/D need be updated with both Even/Odd page with huge pte */ + if (FIELD_EX64(base, TLBENTRY, HUGE)) { + context->pte_buddy[1] =3D pte_mkaccess(context->pte_buddy[1]); + if (access_type =3D=3D MMU_DATA_STORE) { + context->pte_buddy[1] =3D pte_mkdirty(context->pte_buddy[1= ]); + } + } + } + + return ret; } =20 static TLBRet loongarch_map_address(CPULoongArchState *env, --=20 2.39.3 From nobody Sat Nov 15 03:14:59 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755746128515926.0189060925031; Wed, 20 Aug 2025 20:15:28 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovlX-0004Bc-GU; Wed, 20 Aug 2025 23:15:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uovlV-00045P-If for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:15:01 -0400 Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uovlS-0003gD-3C for qemu-devel@nongnu.org; Wed, 20 Aug 2025 23:15:00 -0400 Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxidG9jqZovzoBAA--.2286S3; Thu, 21 Aug 2025 11:13:01 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowJDxrcG4jqZodY5cAA--.63748S12; Thu, 21 Aug 2025 11:13:00 +0800 (CST) From: Bibo Mao To: Song Gao , Richard Henderson Cc: Jiaxun Yang , qemu-devel@nongnu.org Subject: [PATCH v2 10/10] target/loongarch: Add bit A/D checking in TLB entry with PTW supported Date: Thu, 21 Aug 2025 11:12:56 +0800 Message-Id: <20250821031256.3451168-11-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250821031256.3451168-1-maobibo@loongson.cn> References: <20250821031256.3451168-1-maobibo@loongson.cn> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowJDxrcG4jqZodY5cAA--.63748S12 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=114.242.206.163; envelope-from=maobibo@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZM-MESSAGEID: 1755746130386124100 Content-Type: text/plain; charset="utf-8" With read/write access, add bit A/D checking if hardware PTW is supported. If no matched, hardware page table walk is called. And then bit A/D is updated in PTE entry and TLB entry is updated also. Signed-off-by: Bibo Mao --- target/loongarch/tcg/tlb_helper.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/loongarch/tcg/tlb_helper.c b/target/loongarch/tcg/tlb_h= elper.c index e00a1fd748..b6a26cf2d3 100644 --- a/target/loongarch/tcg/tlb_helper.c +++ b/target/loongarch/tcg/tlb_helper.c @@ -648,6 +648,21 @@ bool loongarch_cpu_tlb_fill(CPUState *cs, vaddr addres= s, int size, /* Data access */ context.addr =3D address; ret =3D get_physical_address(env, &context, access_type, mmu_idx, 0); + if (ret =3D=3D TLBRET_MATCH && context.mmu_index !=3D MMU_DA_IDX + && cpu_has_ptw(env)) { + bool need_mark =3D true; + + if (access_type =3D=3D MMU_DATA_STORE && pte_dirty(context.pte)) { + need_mark =3D false; + } else if (access_type !=3D MMU_DATA_STORE && pte_access(context.p= te)) { + need_mark =3D false; + } + + if (need_mark) { + ret =3D TLBRET_NOMATCH; + } + } + if (ret !=3D TLBRET_MATCH && cpu_has_ptw(env)) { /* Take HW PTW if TLB missed or bit P is zero */ if (ret =3D=3D TLBRET_NOMATCH || ret =3D=3D TLBRET_INVALID) { --=20 2.39.3