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Fix that by introducing a fallback memory region which gets enabled if no inbound viewports are configured, as= the real HW would do. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/designware.h | 1 + hw/pci-host/designware.c | 30 +++++++++++++++++------------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designw= are.h index 34beee1285..342b09fd08 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -86,6 +86,7 @@ struct DesignwarePCIEHost { struct { AddressSpace address_space; MemoryRegion address_space_root; + MemoryRegion address_space_root_default; =20 MemoryRegion memory; MemoryRegion io; diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 2fd60a4817..d71133a456 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -347,6 +347,17 @@ static void designware_pcie_update_viewport(Designware= PCIERoot *root, break; } } + + bool one_mapped =3D false; + for (int j =3D 0; j < DESIGNWARE_PCIE_NUM_VIEWPORTS; j++) { + one_mapped |=3D memory_region_is_mapped(&root->viewports[DESIGNWAR= E_PCIE_VIEWPORT_INBOUND][j].mem); + } + + /* + * If no inbound iATU windows are configured, HW defaults to + * letting inbound TLPs to pass in. + */ + memory_region_set_enabled(&host->pci.address_space_root_default, !one_= mapped); } =20 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t addre= ss, @@ -477,19 +488,7 @@ static void designware_pcie_root_realize(PCIDevice *de= v, Error **errp) viewport->target =3D 0x0000000000000000ULL; viewport->limit =3D UINT32_MAX; viewport->cr[0] =3D DESIGNWARE_PCIE_ATU_TYPE_MEM; - - /* - * If no inbound iATU windows are configured, HW defaults to - * letting inbound TLPs to pass in. We emulate that by explici= tly - * configuring first inbound window to cover all of target's - * address space. - * - * NOTE: This will not work correctly for the case when first - * configured inbound window is window 0 - */ - viewport->cr[1] =3D (viewport->inbound && j =3D=3D 0) - ? DESIGNWARE_PCIE_ATU_ENABLE - : 0; + viewport->cr[1] =3D 0; =20 designware_pcie_update_viewport(root, viewport); } @@ -706,6 +705,11 @@ static void designware_pcie_host_realize(DeviceState *= dev, Error **errp) address_space_init(&s->pci.address_space, &s->pci.address_space_root, "pcie-bus-address-space"); + memory_region_init_alias(&s->pci.address_space_root_default, OBJECT(s), + "pcie-bus-inbound-default", get_system_memory= (), + 0, UINT32_MAX); + memory_region_add_subregion_overlap(&s->pci.address_space_root, 0, + &s->pci.address_space_root_default= , -10); pci_setup_iommu(pci->bus, &designware_iommu_ops, s); =20 qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); --=20 2.50.1