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Eliminate them now to make the code movement clearer. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 36 +++++++++++++++--------------------- 1 file changed, 15 insertions(+), 21 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index f6e49ce9b8..3a10dc9f99 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -390,8 +390,6 @@ static void designware_pcie_root_realize(PCIDevice *dev= , Error **errp) { DesignwarePCIERoot *root =3D DESIGNWARE_PCIE_ROOT(dev); DesignwarePCIEHost *host =3D designware_pcie_root_to_host(root); - MemoryRegion *host_mem =3D get_system_memory(); - MemoryRegion *address_space =3D &host->pci.memory; PCIBridge *br =3D PCI_BRIDGE(dev); DesignwarePCIEViewport *viewport; /* @@ -419,7 +417,6 @@ static void designware_pcie_root_realize(PCIDevice *dev= , Error **errp) msi_init(dev, 0x50, 32, true, true, &error_fatal); =20 for (i =3D 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) { - MemoryRegion *source, *destination, *mem; const char *direction; char *name; =20 @@ -430,20 +427,18 @@ static void designware_pcie_root_realize(PCIDevice *d= ev, Error **errp) viewport->limit =3D UINT32_MAX; viewport->cr[0] =3D DESIGNWARE_PCIE_ATU_TYPE_MEM; =20 - source =3D &host->pci.address_space_root; - destination =3D host_mem; direction =3D "Inbound"; =20 /* * Configure MemoryRegion implementing PCI -> CPU memory * access */ - mem =3D &viewport->mem; name =3D designware_pcie_viewport_name(direction, i, "MEM"); - memory_region_init_alias(mem, OBJECT(root), name, destination, - dummy_offset, dummy_size); - memory_region_add_subregion_overlap(source, dummy_offset, mem, -1); - memory_region_set_enabled(mem, false); + memory_region_init_alias(&viewport->mem, OBJECT(root), name, + get_system_memory(), dummy_offset, dummy_= size); + memory_region_add_subregion_overlap(&host->pci.address_space_root, + dummy_offset, &viewport->mem, = -1); + memory_region_set_enabled(&viewport->mem, false); g_free(name); =20 viewport =3D &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i= ]; @@ -454,33 +449,31 @@ static void designware_pcie_root_realize(PCIDevice *d= ev, Error **errp) viewport->limit =3D UINT32_MAX; viewport->cr[0] =3D DESIGNWARE_PCIE_ATU_TYPE_MEM; =20 - destination =3D &host->pci.memory; direction =3D "Outbound"; - source =3D host_mem; =20 /* * Configure MemoryRegion implementing CPU -> PCI memory * access */ - mem =3D &viewport->mem; name =3D designware_pcie_viewport_name(direction, i, "MEM"); - memory_region_init_alias(mem, OBJECT(root), name, destination, - dummy_offset, dummy_size); - memory_region_add_subregion(source, dummy_offset, mem); - memory_region_set_enabled(mem, false); + memory_region_init_alias(&viewport->mem, OBJECT(root), name, + &host->pci.memory, dummy_offset, dummy_si= ze); + memory_region_add_subregion(get_system_memory(), dummy_offset, + &viewport->mem); + memory_region_set_enabled(&viewport->mem, false); g_free(name); =20 /* * Configure MemoryRegion implementing access to configuration * space */ - mem =3D &viewport->cfg; name =3D designware_pcie_viewport_name(direction, i, "CFG"); memory_region_init_io(&viewport->cfg, OBJECT(root), &designware_pci_host_conf_ops, viewport, name, dummy_size); - memory_region_add_subregion(source, dummy_offset, mem); - memory_region_set_enabled(mem, false); + memory_region_add_subregion(get_system_memory(), dummy_offset, + &viewport->cfg); + memory_region_set_enabled(&viewport->cfg, false); g_free(name); } =20 @@ -506,7 +499,8 @@ static void designware_pcie_root_realize(PCIDevice *dev= , Error **errp) * in designware_pcie_root_update_msi_mapping() as a part of * initialization done by guest OS */ - memory_region_add_subregion(address_space, dummy_offset, &root->msi.io= mem); + memory_region_add_subregion(&host->pci.memory, dummy_offset, + &root->msi.iomem); memory_region_set_enabled(&root->msi.iomem, false); } =20 --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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This has several drawbacks: First, two MemoryRegion members are needed per viewport while maximum only one is ever used at a time. Second, for inbound viewports, the `cfg` member is never used nor initialized. Third, adding support for other types of memory such as I/O space would require adding ev= en more MemoryRegion members, one for each type. Fix these limiations by having just one MemoryRegion member which gets configured on demand. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/designware.h | 3 +- hw/pci-host/designware.c | 181 ++++++++++++++----------------- 2 files changed, 81 insertions(+), 103 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designw= are.h index a35a3bd06c..7dc8af049d 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -40,8 +40,7 @@ struct DesignwarePCIERootBus { =20 typedef struct DesignwarePCIEViewport { DesignwarePCIERoot *root; - - MemoryRegion cfg; + const char *name; MemoryRegion mem; =20 uint64_t base; diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 3a10dc9f99..7d47d8228f 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -272,33 +272,54 @@ static const MemoryRegionOps designware_pci_host_conf= _ops =3D { static void designware_pcie_update_viewport(DesignwarePCIERoot *root, DesignwarePCIEViewport *viewpo= rt) { + DesignwarePCIEHost *host =3D designware_pcie_root_to_host(root); const uint64_t target =3D viewport->target; const uint64_t base =3D viewport->base; const uint64_t size =3D (uint64_t)viewport->limit - base + 1; const bool enabled =3D viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; =20 - MemoryRegion *current, *other; - - if (viewport->cr[0] =3D=3D DESIGNWARE_PCIE_ATU_TYPE_MEM) { - current =3D &viewport->mem; - other =3D &viewport->cfg; - memory_region_set_alias_offset(current, target); - } else { - current =3D &viewport->cfg; - other =3D &viewport->mem; + if (memory_region_is_mapped(&viewport->mem)) { + memory_region_del_subregion(viewport->mem.container, &viewport->me= m); } + object_unparent(OBJECT(&viewport->mem)); =20 - /* - * An outbound viewport can be reconfigure from being MEM to CFG, - * to account for that we disable the "other" memory region that - * becomes unused due to that fact. - */ - memory_region_set_enabled(other, false); if (enabled) { - memory_region_set_size(current, size); - memory_region_set_address(current, base); + if (viewport->cr[0] =3D=3D DESIGNWARE_PCIE_ATU_TYPE_MEM) { + if (viewport->inbound) { + /* + * Configure MemoryRegion implementing PCI -> CPU memory + * access + */ + memory_region_init_alias(&viewport->mem, OBJECT(root), + viewport->name, get_system_memory= (), + target, size); + memory_region_add_subregion_overlap(&host->pci.address_spa= ce_root, + base, &viewport->mem, = -1); + } else { + /* + * Configure MemoryRegion implementing CPU -> PCI memory + * access + */ + memory_region_init_alias(&viewport->mem, OBJECT(root), + viewport->name, &host->pci.memory, + target, size); + memory_region_add_subregion(get_system_memory(), base, + &viewport->mem); + } + } else { + if (!viewport->inbound) { + /* + * Configure MemoryRegion implementing access to configura= tion + * space + */ + memory_region_init_io(&viewport->mem, OBJECT(root), + &designware_pci_host_conf_ops, + viewport, viewport->name, size); + memory_region_add_subregion(get_system_memory(), base, + &viewport->mem); + } + } } - memory_region_set_enabled(current, enabled); } =20 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t addre= ss, @@ -378,27 +399,16 @@ static void designware_pcie_root_config_write(PCIDevi= ce *d, uint32_t address, } } =20 -static char *designware_pcie_viewport_name(const char *direction, - unsigned int i, - const char *type) -{ - return g_strdup_printf("PCI %s Viewport %u [%s]", - direction, i, type); -} - static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) { DesignwarePCIERoot *root =3D DESIGNWARE_PCIE_ROOT(dev); DesignwarePCIEHost *host =3D designware_pcie_root_to_host(root); PCIBridge *br =3D PCI_BRIDGE(dev); - DesignwarePCIEViewport *viewport; /* * Dummy values used for initial configuration of MemoryRegions * that belong to a given viewport */ const hwaddr dummy_offset =3D 0; - const uint64_t dummy_size =3D 4; - size_t i; =20 br->bus_name =3D "dw-pcie"; =20 @@ -416,80 +426,49 @@ static void designware_pcie_root_realize(PCIDevice *d= ev, Error **errp) msi_nonbroken =3D true; msi_init(dev, 0x50, 32, true, true, &error_fatal); =20 - for (i =3D 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) { - const char *direction; - char *name; - - viewport =3D &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; - viewport->inbound =3D true; - viewport->base =3D 0x0000000000000000ULL; - viewport->target =3D 0x0000000000000000ULL; - viewport->limit =3D UINT32_MAX; - viewport->cr[0] =3D DESIGNWARE_PCIE_ATU_TYPE_MEM; - - direction =3D "Inbound"; - - /* - * Configure MemoryRegion implementing PCI -> CPU memory - * access - */ - name =3D designware_pcie_viewport_name(direction, i, "MEM"); - memory_region_init_alias(&viewport->mem, OBJECT(root), name, - get_system_memory(), dummy_offset, dummy_= size); - memory_region_add_subregion_overlap(&host->pci.address_space_root, - dummy_offset, &viewport->mem, = -1); - memory_region_set_enabled(&viewport->mem, false); - g_free(name); - - viewport =3D &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i= ]; - viewport->root =3D root; - viewport->inbound =3D false; - viewport->base =3D 0x0000000000000000ULL; - viewport->target =3D 0x0000000000000000ULL; - viewport->limit =3D UINT32_MAX; - viewport->cr[0] =3D DESIGNWARE_PCIE_ATU_TYPE_MEM; - - direction =3D "Outbound"; - - /* - * Configure MemoryRegion implementing CPU -> PCI memory - * access - */ - name =3D designware_pcie_viewport_name(direction, i, "MEM"); - memory_region_init_alias(&viewport->mem, OBJECT(root), name, - &host->pci.memory, dummy_offset, dummy_si= ze); - memory_region_add_subregion(get_system_memory(), dummy_offset, - &viewport->mem); - memory_region_set_enabled(&viewport->mem, false); - g_free(name); - - /* - * Configure MemoryRegion implementing access to configuration - * space - */ - name =3D designware_pcie_viewport_name(direction, i, "CFG"); - memory_region_init_io(&viewport->cfg, OBJECT(root), - &designware_pci_host_conf_ops, - viewport, name, dummy_size); - memory_region_add_subregion(get_system_memory(), dummy_offset, - &viewport->cfg); - memory_region_set_enabled(&viewport->cfg, false); - g_free(name); + for (size_t i =3D 0; i < ARRAY_SIZE(root->viewports); i++) { + static const char *names[][DESIGNWARE_PCIE_NUM_VIEWPORTS] =3D { + { + "PCI Outbound Viewport 0", + "PCI Outbound Viewport 1", + "PCI Outbound Viewport 2", + "PCI Outbound Viewport 3" + }, + { + "PCI Inbound Viewport 0", + "PCI Inbound Viewport 1", + "PCI Inbound Viewport 2", + "PCI Inbound Viewport 3" + }, + }; + + for (size_t j =3D 0; j < DESIGNWARE_PCIE_NUM_VIEWPORTS; j++) { + DesignwarePCIEViewport *viewport =3D &root->viewports[i][j]; + viewport->root =3D root; + viewport->name =3D names[i][j]; + viewport->inbound =3D i =3D=3D DESIGNWARE_PCIE_VIEWPORT_INBOUN= D; + viewport->base =3D 0x0000000000000000ULL; + viewport->target =3D 0x0000000000000000ULL; + viewport->limit =3D UINT32_MAX; + viewport->cr[0] =3D DESIGNWARE_PCIE_ATU_TYPE_MEM; + + /* + * If no inbound iATU windows are configured, HW defaults to + * letting inbound TLPs to pass in. We emulate that by explici= tly + * configuring first inbound window to cover all of target's + * address space. + * + * NOTE: This will not work correctly for the case when first + * configured inbound window is window 0 + */ + viewport->cr[1] =3D (viewport->inbound && j =3D=3D 0) + ? DESIGNWARE_PCIE_ATU_ENABLE + : 0; + + designware_pcie_update_viewport(root, viewport); + } } =20 - /* - * If no inbound iATU windows are configured, HW defaults to - * letting inbound TLPs to pass in. We emulate that by explicitly - * configuring first inbound window to cover all of target's - * address space. - * - * NOTE: This will not work correctly for the case when first - * configured inbound window is window 0 - */ - viewport =3D &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; - viewport->cr[1] =3D DESIGNWARE_PCIE_ATU_ENABLE; - designware_pcie_update_viewport(root, viewport); - memory_region_init_io(&root->msi.iomem, OBJECT(root), &designware_pci_host_msi_ops, root, "pcie-msi", 0x4); --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1755724897; cv=none; d=zohomail.com; s=zohoarc; b=IHptyKn2uCBvE5bV5u/yCllzNeQK3RZCMRq4Xwux5qDe8sHTkPCyweblmPpkFoUX/i/7zzc5x53WYg0mzbB3ghsY3IYtSPHK5YkKLALpp9u8cvtppBuzu/s1M209sJ/glVSFj2Hb+/q/NMwjVjES+1tpQhKbdHWKi3VNIc4oS1c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755724897; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PV5PRLX0fBzyIDbGMvnzpIIGMqO5fU+XNvrNfSXHklc=; b=E4hc5VEuJ4RotTcaI9QFMABPodWxaCeHD/cUWb/xYDhHZ5ha8hOCPp8sUjojm8fiOcys0eJcveDuY3rE/xiKpU1J9kxGH6uJVoqzwafeiDPt70nXp4kxer7SzOZgqwDjeqn9dr4RQS6W2O+ITdJ4tvOyQxBzMv8OpGvKwQy+mAE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755724897974580.3974076448284; Wed, 20 Aug 2025 14:21:37 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uoqDu-0005Ia-S8; Wed, 20 Aug 2025 17:19:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uoqDr-0005GX-Q4; Wed, 20 Aug 2025 17:19:55 -0400 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uoqDp-00050E-5N; Wed, 20 Aug 2025 17:19:55 -0400 Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-61a8f452c43so512339a12.0; Wed, 20 Aug 2025 14:19:52 -0700 (PDT) Received: from Provence.localdomain (dynamic-2a02-3100-249c-be00-0219-99ff-feb2-2458.310.pool.telefonica.de. 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This is both more efficient at runtime and resolves an attribute. Furthermore, if an invalid = PCI device is configured, a guest error is now logged since the error is now direclty related to a guest action. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/designware.h | 1 - hw/pci-host/designware.c | 54 +++++++++++++++++--------------- 2 files changed, 28 insertions(+), 27 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designw= are.h index 7dc8af049d..34beee1285 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -39,7 +39,6 @@ struct DesignwarePCIERootBus { }; =20 typedef struct DesignwarePCIEViewport { - DesignwarePCIERoot *root; const char *name; MemoryRegion mem; =20 diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 7d47d8228f..2a676c65a2 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -222,26 +222,18 @@ designware_pcie_root_config_read(PCIDevice *d, uint32= _t address, int len) static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr, uint64_t *val, unsigned l= en) { - DesignwarePCIEViewport *viewport =3D opaque; - DesignwarePCIERoot *root =3D viewport->root; - - const uint8_t busnum =3D DESIGNWARE_PCIE_ATU_BUS(viewport->target); - const uint8_t devfn =3D DESIGNWARE_PCIE_ATU_DEVFN(viewport->target); - PCIBus *pcibus =3D pci_get_bus(PCI_DEVICE(root)); - PCIDevice *pcidev =3D pci_find_device(pcibus, busnum, devfn); - - if (pcidev) { - addr &=3D pci_config_size(pcidev) - 1; - - if (val) { - pci_host_config_write_common(pcidev, addr, - pci_config_size(pcidev), - *val, len); - } else { - return pci_host_config_read_common(pcidev, addr, - pci_config_size(pcidev), - len); - } + PCIDevice *pcidev =3D opaque; + + addr &=3D pci_config_size(pcidev) - 1; + + if (val) { + pci_host_config_write_common(pcidev, addr, + pci_config_size(pcidev), + *val, len); + } else { + return pci_host_config_read_common(pcidev, addr, + pci_config_size(pcidev), + len); } =20 return UINT64_MAX; @@ -312,11 +304,22 @@ static void designware_pcie_update_viewport(Designwar= ePCIERoot *root, * Configure MemoryRegion implementing access to configura= tion * space */ - memory_region_init_io(&viewport->mem, OBJECT(root), - &designware_pci_host_conf_ops, - viewport, viewport->name, size); - memory_region_add_subregion(get_system_memory(), base, - &viewport->mem); + const uint8_t busnum =3D DESIGNWARE_PCIE_ATU_BUS(viewport-= >target); + const uint8_t devfn =3D DESIGNWARE_PCIE_ATU_DEVFN(viewport= ->target); + PCIBus *pcibus =3D pci_get_bus(PCI_DEVICE(root)); + PCIDevice *pcidev =3D pci_find_device(pcibus, busnum, devf= n); + + if (pcidev) { + memory_region_init_io(&viewport->mem, OBJECT(root), + &designware_pci_host_conf_ops, + pcidev, viewport->name, size); + memory_region_add_subregion(get_system_memory(), base, + &viewport->mem); + } else { + qemu_log_mask(LOG_GUEST_ERROR, "%s: No PCI device atta= ched" + " under busnum: %d, devfn: %d\n", __func= __, + (int)busnum, (int)devfn); + } } } } @@ -444,7 +447,6 @@ static void designware_pcie_root_realize(PCIDevice *dev= , Error **errp) =20 for (size_t j =3D 0; j < DESIGNWARE_PCIE_NUM_VIEWPORTS; j++) { DesignwarePCIEViewport *viewport =3D &root->viewports[i][j]; - viewport->root =3D root; viewport->name =3D names[i][j]; viewport->inbound =3D i =3D=3D DESIGNWARE_PCIE_VIEWPORT_INBOUN= D; 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At the same time, unimplemented memory types and guest errors are logged. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 27 ++++++++++++++++++++++++--- 1 file changed, 24 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 2a676c65a2..5ad7574924 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -44,7 +44,11 @@ #define DESIGNWARE_PCIE_ATU_VIEWPORT 0x900 #define DESIGNWARE_PCIE_ATU_REGION_INBOUND BIT(31) #define DESIGNWARE_PCIE_ATU_CR1 0x904 -#define DESIGNWARE_PCIE_ATU_TYPE_MEM (0x0 << 0) +#define DESIGNWARE_PCIE_ATU_TYPE_MEM 0x0 +#define DESIGNWARE_PCIE_ATU_TYPE_IO 0x2 +#define DESIGNWARE_PCIE_ATU_TYPE_CFG0 0x4 +#define DESIGNWARE_PCIE_ATU_TYPE_CFG1 0x5 +#define DESIGNWARE_PCIE_ATU_TYPE_MSG 0x10 #define DESIGNWARE_PCIE_ATU_CR2 0x908 #define DESIGNWARE_PCIE_ATU_ENABLE BIT(31) #define DESIGNWARE_PCIE_ATU_LOWER_BASE 0x90C @@ -268,6 +272,7 @@ static void designware_pcie_update_viewport(DesignwareP= CIERoot *root, const uint64_t target =3D viewport->target; const uint64_t base =3D viewport->base; const uint64_t size =3D (uint64_t)viewport->limit - base + 1; + const int iatu_type =3D viewport->cr[0]; const bool enabled =3D viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; =20 if (memory_region_is_mapped(&viewport->mem)) { @@ -276,7 +281,8 @@ static void designware_pcie_update_viewport(DesignwareP= CIERoot *root, object_unparent(OBJECT(&viewport->mem)); =20 if (enabled) { - if (viewport->cr[0] =3D=3D DESIGNWARE_PCIE_ATU_TYPE_MEM) { + switch (iatu_type) { + case DESIGNWARE_PCIE_ATU_TYPE_MEM: if (viewport->inbound) { /* * Configure MemoryRegion implementing PCI -> CPU memory @@ -298,7 +304,10 @@ static void designware_pcie_update_viewport(Designware= PCIERoot *root, memory_region_add_subregion(get_system_memory(), base, &viewport->mem); } - } else { + break; + + case DESIGNWARE_PCIE_ATU_TYPE_CFG0: + case DESIGNWARE_PCIE_ATU_TYPE_CFG1: if (!viewport->inbound) { /* * Configure MemoryRegion implementing access to configura= tion @@ -321,6 +330,18 @@ static void designware_pcie_update_viewport(Designware= PCIERoot *root, (int)busnum, (int)devfn); } } + break; + + case DESIGNWARE_PCIE_ATU_TYPE_IO: + case DESIGNWARE_PCIE_ATU_TYPE_MSG: + qemu_log_mask(LOG_UNIMP, "%s: Unimplemented iATU type %d", __f= unc__, + iatu_type); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Illegal iATU type %d", __f= unc__, + iatu_type); + break; } } } --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1755724911; cv=none; d=zohomail.com; s=zohoarc; b=gH7o7gM6So8jko2iiDD1aScOFWZHRBkBKWGWb8ZGpFHoFH1q7TM7tskJQQQRqSYzTDVg71FRHFQndc1cnelj5ggMEfLirYytkxeYRto5MU4QwA1G8CPBIKcd7ydJ9ac1Ffz/x7XJ3wfHpTg892hH8q1KfFtfT2PXEVW3PeHHAtg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755724911; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=JnU/2XOvhfKf0py0byocSk1ZC/ukvx07ErFoqRV6J40=; b=iipGCRcSGIKQ0aOS60NoVC6bsjBs3D4yo4qz+OiPSnCbG4OScGecAY5sW9dfsGRMW6y5k2b040ulBIyXE5/4h5xgMqDT+myrqDe5K3EGSQJhQUsQNWvtW0bDbGrHwjgsxB4nWKzUsrVM4/K+fzkWMMYpGWhJ6XZ6eAsyQ8qCF+k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 175572491147487.73036256403861; Wed, 20 Aug 2025 14:21:51 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uoqDx-0005KW-2g; Wed, 20 Aug 2025 17:20:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uoqDu-0005IS-Lf; Wed, 20 Aug 2025 17:19:58 -0400 Received: from mail-ed1-x533.google.com ([2a00:1450:4864:20::533]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uoqDr-00050e-SL; Wed, 20 Aug 2025 17:19:58 -0400 Received: by mail-ed1-x533.google.com with SMTP id 4fb4d7f45d1cf-61aa702c9ebso756519a12.3; Wed, 20 Aug 2025 14:19:54 -0700 (PDT) Received: from Provence.localdomain (dynamic-2a02-3100-249c-be00-0219-99ff-feb2-2458.310.pool.telefonica.de. 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Fix that. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 5ad7574924..7342207eb3 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -283,6 +283,7 @@ static void designware_pcie_update_viewport(DesignwareP= CIERoot *root, if (enabled) { switch (iatu_type) { case DESIGNWARE_PCIE_ATU_TYPE_MEM: + case DESIGNWARE_PCIE_ATU_TYPE_IO: if (viewport->inbound) { /* * Configure MemoryRegion implementing PCI -> CPU memory @@ -298,9 +299,12 @@ static void designware_pcie_update_viewport(Designware= PCIERoot *root, * Configure MemoryRegion implementing CPU -> PCI memory * access */ + MemoryRegion *mr =3D iatu_type =3D=3D DESIGNWARE_PCIE_ATU_= TYPE_IO + ? &host->pci.io + : &host->pci.memory; + memory_region_init_alias(&viewport->mem, OBJECT(root), - viewport->name, &host->pci.memory, - target, size); + viewport->name, mr, target, size); memory_region_add_subregion(get_system_memory(), base, &viewport->mem); } @@ -332,7 +336,6 @@ static void designware_pcie_update_viewport(DesignwareP= CIERoot *root, } break; =20 - case DESIGNWARE_PCIE_ATU_TYPE_IO: case DESIGNWARE_PCIE_ATU_TYPE_MSG: qemu_log_mask(LOG_UNIMP, "%s: Unimplemented iATU type %d", __f= unc__, iatu_type); --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1755724870; cv=none; d=zohomail.com; s=zohoarc; b=SHOgMrbRPqNAhrvUZXK4BB6Bkfu/yyjjYtbs2pfeW7PkZeplOhdp58/BATUybAH8sRPi7waZVBqWKDPoxm91tkfXQtCOHf4T0MT81ayew4WV+vviidH1UuBrApEZAZub6tp3Ps/Hvt3LGbqg+L+Y3gexg7c9iFvy6T3W/STfPLQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755724870; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=lYVlm45QQ3i2G9+d7L5TMWVG0rHC31MFiYi6MByt5lI=; b=Mlqdev0FEFilm3wV2RezpD35yJf5gd0iWN0kxA6+4hBSGQ2NjzlSKN9zs7/bTH4YLX2Zju3W9Lbo0gOQYz5ejF2isAwYf+AI7ArCanfkqif09FzrCfG3g0FgtObLei47tNa+A+fGAOObWI/2dymdAY4KaK5y5vMd3ag0onk2BWE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755724870637692.1880617668994; Wed, 20 Aug 2025 14:21:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uoqDx-0005Ko-9X; Wed, 20 Aug 2025 17:20:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uoqDu-0005IZ-RG; Wed, 20 Aug 2025 17:19:58 -0400 Received: from mail-ej1-x62c.google.com ([2a00:1450:4864:20::62c]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uoqDt-00050u-0G; Wed, 20 Aug 2025 17:19:58 -0400 Received: by mail-ej1-x62c.google.com with SMTP id a640c23a62f3a-afcb7a3ee3cso47694566b.2; Wed, 20 Aug 2025 14:19:56 -0700 (PDT) Received: from Provence.localdomain (dynamic-2a02-3100-249c-be00-0219-99ff-feb2-2458.310.pool.telefonica.de. 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This fixes illegal memory access by guests in the imx8mp-evk machine such that the FSL_IMX8MP_PCIE1_MEM unimplemented region can be omitted there. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 7342207eb3..1e29b7e6be 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -684,7 +684,7 @@ static void designware_pcie_host_realize(DeviceState *d= ev, Error **errp) "pcie.reg", 4 * 1024); sysbus_init_mmio(sbd, &s->mmio); =20 - memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16); + memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", UINT16_MAX); memory_region_init(&s->pci.memory, OBJECT(s), "pcie-bus-memory", UINT64_MAX); --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1755724878; cv=none; d=zohomail.com; s=zohoarc; b=ZjlXBD7BS9vi0rpSYzg2Z8NnOKRKga1IHOdqSSZO8qI2meqAgxB7K2VWQpf4+fZ4d/gCJPvJhrzGINmrfDGw776VOGxTjLWrHhy1NswrlwPlsf0bzbplPdDFzBQcIedYLOtRCnw7ytMMEbCL22ryASsWmlteCq4PNGmb8w1GHGY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755724878; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=8JUtot82YvSwyf3aXIjcJBWwXAuoQGNyUhMh8fZ0EZY=; b=XPsNi7mayjgozFQKcH92YKuis3VQjcJG725EIe2M6NR6zDnvCpXU/d+AxPhHwrGaZRHDwN2sdsrScIK9j7jBU1qJDx5uuHmlGD1KFSTyVn9NEz5Zo28oLyshWxAH56pjpqscKdRKKYJwLkTfeS3lc+4nNZNyxtRgjkHqwnzvS7Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755724878110931.8042073048164; Wed, 20 Aug 2025 14:21:18 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uoqDy-0005Lc-0K; Wed, 20 Aug 2025 17:20:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uoqDv-0005Jk-Tw; Wed, 20 Aug 2025 17:19:59 -0400 Received: from mail-ed1-x531.google.com ([2a00:1450:4864:20::531]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uoqDu-00051J-AE; Wed, 20 Aug 2025 17:19:59 -0400 Received: by mail-ed1-x531.google.com with SMTP id 4fb4d7f45d1cf-61a2a5b06cdso647554a12.1; Wed, 20 Aug 2025 14:19:57 -0700 (PDT) Received: from Provence.localdomain (dynamic-2a02-3100-249c-be00-0219-99ff-feb2-2458.310.pool.telefonica.de. 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Furthermore, inbound and outbound mappings are entirely defined by iATUs. Remove the hardcoded mapping of PCI memory space to match real hardware. Note that the device model attempts to implement the default inbound mapping by reusing an inbound iATU. However, Linux clears all iATUs during boot, including the one purposefully set up by the device model, resulting in no default mapping. This will be fixed in the next patch. Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 1e29b7e6be..2fd60a4817 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -703,8 +703,6 @@ static void designware_pcie_host_realize(DeviceState *d= ev, Error **errp) OBJECT(s), "pcie-bus-address-space-root", UINT64_MAX); - memory_region_add_subregion(&s->pci.address_space_root, - 0x0, &s->pci.memory); address_space_init(&s->pci.address_space, &s->pci.address_space_root, "pcie-bus-address-space"); --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1755724870; cv=none; d=zohomail.com; s=zohoarc; b=S8V8cm388jJVazFdDMmTHWHCm/sZWpDQTBiufARP1OJ2OsYlxf4HelS10yaG7+TyxUMSzCfb+zj03/xJZO5bzzP3CxjRJ0QBaiu2npjCGdTnAAtcJgmp2vam/O4KhwnawL7sUo7nVLedWPV2B29o2Gp6ghH2sHVoJ8NJUGw20nU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755724870; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=erIPPZ0BDsRCUdIVCLWmsfKr2++tLsVOASTjdmVI5yc=; b=Kzoy+UpEfUMNb12LCPBGYaiFftobN0NrapCRqfa5XGrGglMQLh1ZRE4QiXUw2Vr6frbQUIxKYPqshPR5RZisnIfrjKvJJqqoJq4HHC1ml98Umc9UWXrHV+ZPNgmP35dQNbC9SXfu1vGZc+0lYsSD3R3ipRGihJ7AVYVRH3xt4xQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755724870800131.02768577392635; Wed, 20 Aug 2025 14:21:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uoqDz-0005MS-PP; Wed, 20 Aug 2025 17:20:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uoqDx-0005L0-Eu; Wed, 20 Aug 2025 17:20:01 -0400 Received: from mail-ed1-x532.google.com ([2a00:1450:4864:20::532]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uoqDv-00051X-LV; Wed, 20 Aug 2025 17:20:01 -0400 Received: by mail-ed1-x532.google.com with SMTP id 4fb4d7f45d1cf-6188b7550c0so522348a12.2; Wed, 20 Aug 2025 14:19:59 -0700 (PDT) Received: from Provence.localdomain (dynamic-2a02-3100-249c-be00-0219-99ff-feb2-2458.310.pool.telefonica.de. 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Fix that by introducing a fallback memory region which gets enabled if no inbound viewports are configured, as= the real HW would do. Signed-off-by: Bernhard Beschow --- include/hw/pci-host/designware.h | 1 + hw/pci-host/designware.c | 30 +++++++++++++++++------------- 2 files changed, 18 insertions(+), 13 deletions(-) diff --git a/include/hw/pci-host/designware.h b/include/hw/pci-host/designw= are.h index 34beee1285..342b09fd08 100644 --- a/include/hw/pci-host/designware.h +++ b/include/hw/pci-host/designware.h @@ -86,6 +86,7 @@ struct DesignwarePCIEHost { struct { AddressSpace address_space; MemoryRegion address_space_root; + MemoryRegion address_space_root_default; =20 MemoryRegion memory; MemoryRegion io; diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index 2fd60a4817..d71133a456 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -347,6 +347,17 @@ static void designware_pcie_update_viewport(Designware= PCIERoot *root, break; } } + + bool one_mapped =3D false; + for (int j =3D 0; j < DESIGNWARE_PCIE_NUM_VIEWPORTS; j++) { + one_mapped |=3D memory_region_is_mapped(&root->viewports[DESIGNWAR= E_PCIE_VIEWPORT_INBOUND][j].mem); + } + + /* + * If no inbound iATU windows are configured, HW defaults to + * letting inbound TLPs to pass in. + */ + memory_region_set_enabled(&host->pci.address_space_root_default, !one_= mapped); } =20 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t addre= ss, @@ -477,19 +488,7 @@ static void designware_pcie_root_realize(PCIDevice *de= v, Error **errp) viewport->target =3D 0x0000000000000000ULL; viewport->limit =3D UINT32_MAX; viewport->cr[0] =3D DESIGNWARE_PCIE_ATU_TYPE_MEM; - - /* - * If no inbound iATU windows are configured, HW defaults to - * letting inbound TLPs to pass in. We emulate that by explici= tly - * configuring first inbound window to cover all of target's - * address space. - * - * NOTE: This will not work correctly for the case when first - * configured inbound window is window 0 - */ - viewport->cr[1] =3D (viewport->inbound && j =3D=3D 0) - ? DESIGNWARE_PCIE_ATU_ENABLE - : 0; + viewport->cr[1] =3D 0; =20 designware_pcie_update_viewport(root, viewport); } @@ -706,6 +705,11 @@ static void designware_pcie_host_realize(DeviceState *= dev, Error **errp) address_space_init(&s->pci.address_space, &s->pci.address_space_root, "pcie-bus-address-space"); + memory_region_init_alias(&s->pci.address_space_root_default, OBJECT(s), + "pcie-bus-inbound-default", get_system_memory= (), + 0, UINT32_MAX); + memory_region_add_subregion_overlap(&s->pci.address_space_root, 0, + &s->pci.address_space_root_default= , -10); pci_setup_iommu(pci->bus, &designware_iommu_ops, s); =20 qdev_realize(DEVICE(&s->root), BUS(pci->bus), &error_fatal); --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1755724870; cv=none; d=zohomail.com; s=zohoarc; b=dbqloP2r29FiOTdqYICyzbX7RfxLK67JD26SRRwCuO0m1yOO2hbBfTycHgFGAUqXWcwKMkRhL7wrgdwUSUTpwvDq9O3Ug8cBtOv30bJdtnSOeZ087v4Nc4iwIjHZzaeUYaE62/GL2RxLrbIHoF3BmMPQ6iQiRpS89j+KiqKn4OU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755724870; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=l1wUmDXrznirFi3ssCzqlRjHMYNyodcpLnP8rDITPzM=; b=ltyyp49OStby4GLbNa6tT+FAh1/cSVuC0S3xaDolPUE396US0xbadJlG9pmtd98lSrizrUcssHoo7GlNj0UXkqsDhB1O880JR2IGP+MM58cJ2Ol84sqIUpI+VhSx49oc+wUtdpv4jv8atl+Ju0kVjxW2uoRuuFPlbwh3iWtd7LI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755724870742502.31037969414865; Wed, 20 Aug 2025 14:21:10 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uoqE2-0005O2-2j; Wed, 20 Aug 2025 17:20:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uoqE0-0005N0-42; Wed, 20 Aug 2025 17:20:04 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uoqDy-00052D-7d; Wed, 20 Aug 2025 17:20:03 -0400 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-61a94bd82a5so607537a12.1; Wed, 20 Aug 2025 14:20:01 -0700 (PDT) Received: from Provence.localdomain (dynamic-2a02-3100-249c-be00-0219-99ff-feb2-2458.310.pool.telefonica.de. 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Signed-off-by: Bernhard Beschow --- hw/pci-host/designware.c | 33 ++++++++++++++++++++++----------- 1 file changed, 22 insertions(+), 11 deletions(-) diff --git a/hw/pci-host/designware.c b/hw/pci-host/designware.c index d71133a456..2dd4937e52 100644 --- a/hw/pci-host/designware.c +++ b/hw/pci-host/designware.c @@ -442,11 +442,6 @@ static void designware_pcie_root_realize(PCIDevice *de= v, Error **errp) DesignwarePCIERoot *root =3D DESIGNWARE_PCIE_ROOT(dev); DesignwarePCIEHost *host =3D designware_pcie_root_to_host(root); PCIBridge *br =3D PCI_BRIDGE(dev); - /* - * Dummy values used for initial configuration of MemoryRegions - * that belong to a given viewport - */ - const hwaddr dummy_offset =3D 0; =20 br->bus_name =3D "dw-pcie"; =20 @@ -484,6 +479,26 @@ static void designware_pcie_root_realize(PCIDevice *de= v, Error **errp) DesignwarePCIEViewport *viewport =3D &root->viewports[i][j]; viewport->name =3D names[i][j]; viewport->inbound =3D i =3D=3D DESIGNWARE_PCIE_VIEWPORT_INBOUN= D; + } + } + + memory_region_init_io(&root->msi.iomem, OBJECT(root), + &designware_pci_host_msi_ops, + root, "pcie-msi", 0x4); + memory_region_add_subregion(&host->pci.memory, 0, &root->msi.iomem); +} + +static void designware_pcie_root_reset(DeviceState *dev) +{ + DesignwarePCIERoot *root =3D DESIGNWARE_PCIE_ROOT(dev); + DesignwarePCIEViewport *viewport; + + pci_bridge_reset(dev); + + for (int i =3D 0; i < ARRAY_SIZE(root->viewports); i++) { + for (int j =3D 0; j < DESIGNWARE_PCIE_NUM_VIEWPORTS; j++) { + viewport =3D &root->viewports[i][j]; + viewport->base =3D 0x0000000000000000ULL; viewport->target =3D 0x0000000000000000ULL; viewport->limit =3D UINT32_MAX; @@ -494,17 +509,13 @@ static void designware_pcie_root_realize(PCIDevice *d= ev, Error **errp) } } =20 - memory_region_init_io(&root->msi.iomem, OBJECT(root), - &designware_pci_host_msi_ops, - root, "pcie-msi", 0x4); /* * We initially place MSI interrupt I/O region at address 0 and * disable it. It'll be later moved to correct offset and enabled * in designware_pcie_root_update_msi_mapping() as a part of * initialization done by guest OS */ - memory_region_add_subregion(&host->pci.memory, dummy_offset, - &root->msi.iomem); + memory_region_set_address(&root->msi.iomem, 0); memory_region_set_enabled(&root->msi.iomem, false); } =20 @@ -602,7 +613,7 @@ static void designware_pcie_root_class_init(ObjectClass= *klass, k->config_read =3D designware_pcie_root_config_read; k->config_write =3D designware_pcie_root_config_write; =20 - device_class_set_legacy_reset(dc, pci_bridge_reset); + device_class_set_legacy_reset(dc, designware_pcie_root_reset); /* * PCI-facing part of the host bridge, not usable without the * host-facing part, which can't be device_add'ed, yet. --=20 2.50.1 From nobody Sat Nov 15 03:03:56 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1755724885; cv=none; d=zohomail.com; s=zohoarc; b=NrSRiR3pVSAM8NaRb0bdhKcpLz3lLuVLtaDqtl/yfsvhK3o/gXPEEa007UM1M28pRtToJHIriFyI/opwSxz0p+cPXHO2BrxsOt8LXsN9n/FW6KL5xH4e6bONbsVi+dPOeNb2TERRYQ11U6Ob1fR4/A0Y06KjR2jFTcuJ9L2a2ms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1755724885; h=Content-Transfer-Encoding:Cc:Cc:Date:Date:From:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:Subject:To:To:Message-Id:Reply-To; bh=PeVRfk3VsZf+so/2hf9x9CGHxpMR/23OVPq3yUxSLhA=; b=D7hQ2i4zjPuNJNjJpA3+duX146+zbl0ECvrDNYlkhbP9fovygyaxWy365B76ca4rXyNdb0B7w9+7vKXmbehNu+oZdVsEoPocHoXQleNOlJlpZ0JUhiLhUAy4e9GJBavIrwrNHfY43R5E2h6RQ9+BjiTiwg1y9Cmmm4+jBLvRUwk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1755724885156267.7589218323217; Wed, 20 Aug 2025 14:21:25 -0700 (PDT) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uoqE2-0005O5-HC; Wed, 20 Aug 2025 17:20:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uoqE0-0005NK-Tk; Wed, 20 Aug 2025 17:20:04 -0400 Received: from mail-ed1-x52a.google.com ([2a00:1450:4864:20::52a]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1uoqDz-00052a-A0; Wed, 20 Aug 2025 17:20:04 -0400 Received: by mail-ed1-x52a.google.com with SMTP id 4fb4d7f45d1cf-6188b73bef3so654856a12.3; Wed, 20 Aug 2025 14:20:02 -0700 (PDT) Received: from Provence.localdomain (dynamic-2a02-3100-249c-be00-0219-99ff-feb2-2458.310.pool.telefonica.de. [2a02:3100:249c:be00:219:99ff:feb2:2458]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-61a755d9cfasm4161182a12.9.2025.08.20.14.20.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 20 Aug 2025 14:20:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1755724801; x=1756329601; darn=nongnu.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=PeVRfk3VsZf+so/2hf9x9CGHxpMR/23OVPq3yUxSLhA=; b=dRvLZOXAEa8SfZgzATNncEFryELaOnhuRm7seTHoOPzZmeUzTwefgRfobzgle6XMpx KcMjeveqnFFmsSxfB2O9PpRbNaJWYAspFKFMIDrRFDqFWA5+36Wq0Nij+IiX4Y2RumgF BizHGEszRrhyB7A5BpSiYuXQ8Ge77sDVF310DgF/oIMIjYMOZJVnEQi61lroYLs/832m fUSa9ma7TSUtA25fvCQXe/Dm1mPBgq8Dw8BnnuKMpd6hh/8h0qkGbPHLQ8smVEbRhmdz aFQ5JKYZqbmq4KenkBRHDagfoYpw8bye15jWRTEZ+aGggf3PDV6GJgSJGYL0ss5+xRHj OfcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755724801; x=1756329601; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=PeVRfk3VsZf+so/2hf9x9CGHxpMR/23OVPq3yUxSLhA=; b=hm217y+HHVakCQiaCom2m6aLIW+JjJdExsyKAEPnoLVAyR9gTJmzXY9NCsAM+iJ6Ye JUOQpfZK4xEiWsSiMXSbXxqg+KjXAF9nmlcyDF1G6/Vb/D7Tz798FcqXxsXcUBdBnIAm NeoUi4PA2pSeaDwCTTAe0n/6/Ia06HwP4F7TemsUXwhqnlqYVze3wWpRffZaq3xkAfvU nlgJajb4Gooh+fc/skX3Id/aKVnJra7rI1djaJCl2lyyGG8BYhaUT1mKG8ZFualIgFR3 /cI/WPfgkt72HihPMe7XNhrGn6hrhQUssx/u3J4Tgt588xofIHFGKvmN3ZYAE9oy8LeV jcMg== X-Forwarded-Encrypted: i=1; AJvYcCXLaMGU4hqvTsZLWCGVQlniIdo9RwausY8Ps2Sl/pH4kMwyBu3NmldVxkPtJVDfp1EWUjkFOq4NbA==@nongnu.org X-Gm-Message-State: AOJu0Yw7ZbkTgJPYFOVIuebV0RvxuopFh11HI9KRMpY3pRT3OJfeOloJ 9hxw5t70cdaQnq4vVL/beYkEvx5yFC/Ge/s27M/BxAOYk/hCuqqf1/oYNlNoH/14 X-Gm-Gg: ASbGncu8vnoouMs4vMHRWZpVH2pi+XFJM/N0+4byen+pFGKck/uBjjDHTM5JjU8T/ge MXL+MhPJlFoz0jtXkXs+MHIa2lm4PbT+9X26irH4sjRpGJ06lrkLAul78EtzgVCG46HxOjQ8420 zfJsvO0dJf2Y435ONkRQSbws0FrfRdBLud1ZMOR7LD4q0gQ82cIoE76QBN9wPSs44XIFt44GnIg YbeQupwCar+USQ4iNKyny+CVpqW/niL3c2BAkYs1XYsDI8CAQQcoaYyWdikJH6czcWTRzY98ocF pcr6C3FzTqTG2vZtGntOxDpt+enHb544RDN3ZQVqttTOH+LqyrdYjV8JkCRCCqBFHmF/wodFEOL iJfLhdbLTgoVL3SywemF0eRUMF9tDnkja3f9kI6hRsXL1Grg2xR6l3OkO4/YbfUVb9ENEXkluwt iJ3ZWfscYONaS1Tr+BkgZeUIWi4kOgbMRFRggIKv/Xl6EQxDPphOC9OA== X-Google-Smtp-Source: AGHT+IGd6MFMtd+Deaef2YizMDx8hhPfbLZYMq+9A3+3dqqPiaX8bsIFq8g6eYFK67HFUAAmszoH/w== X-Received: by 2002:a05:6402:524d:b0:61a:87c8:1b2c with SMTP id 4fb4d7f45d1cf-61bf87355aemr131371a12.27.1755724800973; Wed, 20 Aug 2025 14:20:00 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: Peter Maydell , Andrey Smirnov , qemu-arm@nongnu.org, Bernhard Beschow , Guenter Roeck Subject: [PATCH 10/10] hw/arm/fsl-imx8mp: Do not map PCI window as unimplemented Date: Wed, 20 Aug 2025 23:19:32 +0200 Message-ID: <20250820211932.27302-11-shentey@gmail.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250820211932.27302-1-shentey@gmail.com> References: <20250820211932.27302-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::52a; envelope-from=shentey@gmail.com; helo=mail-ed1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1755724887117124100 Content-Type: text/plain; charset="utf-8" Now that populating the PCI window via iATUs is functional, it's no longer necessary to cover the PCI window with an unimplemented memory region. Previously, this workaround was required because the device model failed to= map all configured memory regions, which caused Linux to emit backtraces during access attempts. Signed-off-by: Bernhard Beschow --- hw/arm/fsl-imx8mp.c | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/fsl-imx8mp.c b/hw/arm/fsl-imx8mp.c index 866f4d1d74..d66783c101 100644 --- a/hw/arm/fsl-imx8mp.c +++ b/hw/arm/fsl-imx8mp.c @@ -669,6 +669,7 @@ static void fsl_imx8mp_realize(DeviceState *dev, Error = **errp) case FSL_IMX8MP_I2C1 ... FSL_IMX8MP_I2C6: case FSL_IMX8MP_OCRAM: case FSL_IMX8MP_PCIE1: + case FSL_IMX8MP_PCIE1_MEM: case FSL_IMX8MP_PCIE_PHY1: case FSL_IMX8MP_RAM: case FSL_IMX8MP_SNVS_HP: --=20 2.50.1