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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3c3fab22726sm1094539f8f.37.2025.08.20.06.49.38 (version=TLS1_3 cipher=TLS_CHACHA20_POLY1305_SHA256 bits=256/256); Wed, 20 Aug 2025 06:49:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1755697779; x=1756302579; darn=nongnu.org; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:from:to:cc:subject:date:message-id:reply-to; bh=1JoKi1hqpbrpS2BDqIq6v3JJ/w73UgPs21kYdYCsdHA=; b=lN9I8nqb49BA6a+COmcVs2Vhda6bXDOgB5Nd3WA2zvMeEbd9xJKtGYAVbZzeb66O3I JhPZq485w+KFZE4+jS2X8IFTiKBOdQKH28lsJKzbAQnfOK7nelywIKNVm+YrWP5YWf7w QYTcUegPJPI96o4iyR6EGJT301GlJ7/i8Kv1BwG+ef8vy5PfTBxRgulEEhpTyGswd5LX 3rpXvXKpuw/AIE/WkSLdBf5Hxzfv3UuccxAPXd2O2mtbDg7fcwyUuD1TRSpDeWHWwHmP AZp81vvUnIjf/IMU1Sn5roySdRRAaZWczWVoRTBOY6UBiMZ10ftjJuH5fFftiJ3kh4P4 XoJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1755697779; x=1756302579; h=content-transfer-encoding:mime-version:message-id:date:subject:cc :to:from:x-gm-message-state:from:to:cc:subject:date:message-id :reply-to; bh=1JoKi1hqpbrpS2BDqIq6v3JJ/w73UgPs21kYdYCsdHA=; b=Pk1wOM9k7boOG3qFnTJOITje7TybrU56DkV3O1Imm9kW/k/JQEMDRM3OOIOMTKTBhS dLrysenoYEQqODBzE7LRlgSmRQjXWI+L4tl4Fy68Uthw0sw5aHNcP0eKlQI0uVG+yrFl 9i5GKKePMU4wgeUOugcrIA1o4DnRnPLeRol1TXViqjBbr9TGs7UDPQp931HoShCAmLV0 /254NOJAEX/dvFVB2rC+vtzM5ukDz6bUDsqtxz03CnNtEthkvST3lzPf7o5Y2cBKnojW gYQ+H2KOFG5HfmDM2p27BsDC1UZQh7aXpnJWcHBx0TCyFJgPHT1oysqFMDcB5R4/kjdR PUFg== X-Gm-Message-State: AOJu0YwLdiPhDN3OWrMxOThNmjD7yVXaUm54AD/iQxOUUDby1RJ3WpmS w6jmZ4QhgtjOjA0XfKZ0vZxZ7U3Nb13zgiWSojffc2+C9UdWgkjf9yFmGqmPQM/yS7AMnevlrT5 d7S8/ X-Gm-Gg: ASbGncsjHgLzMQFipUQ618HGNOeGrmIBDDAIc6SV4Qrdz7u2RX1VxPpxcG+hZ3ugmwy 6AfF97NxEdEpAZw5eT8wKYy5VWo61Nxk7W9zRbPtwttPa92VTNGgKEK23RbPww+LTQA3dn6FMI8 DSgEzKh+UGHygXvLyq55+r9XwWTYrXHZ5tIqKNqCfH+VJEc1oX06P0YGS4DwbnTfxwLaycg/Ni/ J4/nGqIzqdAArOv5Eo4f4BQuyR5xZb7RbysJvz6pU4uhVVBrZeEP3aeIeUydAHJl873pBS40NMB LrBDAQeh8IWNOSCH78OMkRz2M/77JaH5si7Oex2EGoHUD+gr8QMt5nA04RRrr8Ver3OITEbVBfI tFQQnpLpATHZ5saiM0CwisP72UEbzGjZkDPZZ/aXqWYqauynfHSmfrpPsxvZ8QnVP07Y5FQRSHq oCGw== X-Google-Smtp-Source: AGHT+IG7caQ641/rsKjQjpMyHFQAp3uSPRaRfIhTbADhiU8hROscCUz1IPM8O9KfZDVTZl11ICBdSg== X-Received: by 2002:a5d:5d0d:0:b0:3c2:9d64:125f with SMTP id ffacd0b85a97d-3c31553b888mr2886516f8f.28.1755697779151; Wed, 20 Aug 2025 06:49:39 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Richard Henderson , Pierrick Bouvier , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [RFC PATCH] tcg: Restrict qemu_ld2 and qemu_st2 opcodes to 32-bit hosts Date: Wed, 20 Aug 2025 15:49:37 +0200 Message-ID: <20250820134937.45077-1-philmd@linaro.org> X-Mailer: git-send-email 2.51.0 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=philmd@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1755697817798116600 qemu_ld2 and qemu_st2 opcodes are band-aid for 32-bit hosts and can't be reached on 64-bit ones. See in commit 3bedb9d3e28 ("tcg: Convert qemu_ld{2} to TCGOutOpLoad{2}") and 86fe5c2597c ("tcg: Convert qemu_st{2} to TCGOutOpLdSt{2}") their constraint is C_NotImplemented. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- tcg/tcg.c | 27 ++++++++++++++------------- 1 file changed, 14 insertions(+), 13 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index afac55a203a..ff1a8b71789 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1221,9 +1221,7 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { OUTOP(INDEX_op_or, TCGOutOpBinary, outop_or), OUTOP(INDEX_op_orc, TCGOutOpBinary, outop_orc), OUTOP(INDEX_op_qemu_ld, TCGOutOpQemuLdSt, outop_qemu_ld), - OUTOP(INDEX_op_qemu_ld2, TCGOutOpQemuLdSt2, outop_qemu_ld2), OUTOP(INDEX_op_qemu_st, TCGOutOpQemuLdSt, outop_qemu_st), - OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2), OUTOP(INDEX_op_rems, TCGOutOpBinary, outop_rems), OUTOP(INDEX_op_remu, TCGOutOpBinary, outop_remu), OUTOP(INDEX_op_rotl, TCGOutOpBinary, outop_rotl), @@ -1248,6 +1246,8 @@ static const TCGOutOp * const all_outop[NB_OPS] =3D { =20 #if TCG_TARGET_REG_BITS =3D=3D 32 OUTOP(INDEX_op_brcond2_i32, TCGOutOpBrcond2, outop_brcond2), + OUTOP(INDEX_op_qemu_ld2, TCGOutOpQemuLdSt2, outop_qemu_ld2), + OUTOP(INDEX_op_qemu_st2, TCGOutOpQemuLdSt2, outop_qemu_st2), OUTOP(INDEX_op_setcond2_i32, TCGOutOpSetcond2, outop_setcond2), #else OUTOP(INDEX_op_bswap64, TCGOutOpUnary, outop_bswap64), @@ -5829,17 +5829,6 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) } break; =20 - case INDEX_op_qemu_ld2: - case INDEX_op_qemu_st2: - { - const TCGOutOpQemuLdSt2 *out =3D - container_of(all_outop[op->opc], TCGOutOpQemuLdSt2, base); - - out->out(s, type, new_args[0], new_args[1], - new_args[2], new_args[3]); - } - break; - case INDEX_op_brcond: { const TCGOutOpBrcond *out =3D &outop_brcond; @@ -5887,6 +5876,16 @@ static void tcg_reg_alloc_op(TCGContext *s, const TC= GOp *op) break; =20 #if TCG_TARGET_REG_BITS =3D=3D 32 + case INDEX_op_qemu_ld2: + case INDEX_op_qemu_st2: + { + const TCGOutOpQemuLdSt2 *out =3D + container_of(all_outop[op->opc], TCGOutOpQemuLdSt2, base); + + out->out(s, type, new_args[0], new_args[1], + new_args[2], new_args[3]); + } + break; case INDEX_op_brcond2_i32: { const TCGOutOpBrcond2 *out =3D &outop_brcond2; @@ -5912,6 +5911,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCG= Op *op) } break; #else + case INDEX_op_qemu_ld2: + case INDEX_op_qemu_st2: case INDEX_op_brcond2_i32: case INDEX_op_setcond2_i32: g_assert_not_reached(); --=20 2.51.0