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Iglesias" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , "Frederic Konrad" , Sai Pavan Boddu Subject: [PATCH v2 39/47] target/arm/tcg/cpu64: add the cortex-a78ae CPU Date: Wed, 20 Aug 2025 10:25:38 +0200 Message-ID: <20250820082549.69724-40-luc.michel@amd.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20250820082549.69724-1-luc.michel@amd.com> References: <20250820082549.69724-1-luc.michel@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CO1PEPF000075F0:EE_|PH8PR12MB7027:EE_ X-MS-Office365-Filtering-Correlation-Id: f51d0115-70d4-451a-f7e5-08dddfc364fb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0; ARA:13230040|82310400026|36860700013|376014|1800799024; X-Microsoft-Antispam-Message-Info: =?us-ascii?Q?A0Oi0taO+12lYL4CFocPVjpHbMDYZv3Xs1rVGPrw977dTDv/A1GKJOWg+6MS?= =?us-ascii?Q?fORPV7RXXSLLAory+y2cSPWFsMfl5wteyKg/eUl7U6PMtQPZzpziIIzU1/nw?= =?us-ascii?Q?Dr4oRLh+bOG4Y1hax8/SWBsLdUXDMPYcmI01YJPOQL7oi16Ugpwy2cA1LCqY?= =?us-ascii?Q?++wrT+OjIYU/dANy5zMqI3wKLbEqXZIzvUPi94aTNuUgH9iRgWKWehs7Vxa2?= =?us-ascii?Q?xjEgPkENZU8MTHW7tCRu0EpayZtNHm1IBjvXMO8Cul8k8IRSVN7SWeUHiHSl?= =?us-ascii?Q?7EHr74ebJYkZ2XxfysRyguLrbZu/85E2Zx6EfBMjfuCNSaQkhcF9Ap+tl7/c?= =?us-ascii?Q?PhdQgedXIWAKLhmaT7AJMQIwGEDAbh62X7nX0dwAyFQcYyf9F8LuvFUfQAT6?= =?us-ascii?Q?0Sdn1rNDhdTbImrq6R5pnoefLRc70xCRcuM+LoGcKEc+rXVgpF5dMcOPgvdV?= =?us-ascii?Q?s3e0ux7QRg33CbF+nr694NYcC/HUg/LBqmM0HBU8EwVcxxqwX5DjrV46N1EW?= =?us-ascii?Q?XBi1CjgIBWt5g41vmo/fwQN/HRaH39kX/Dr/9ucdZgUvC2T7EGPE+TPnFdas?= =?us-ascii?Q?uFfLNcO4zISmpfCrlHvu+NWsTMs5lYRozmGlUS0aotX8tbZ5SJVJCo7EG/Si?= =?us-ascii?Q?3KB98Tx6ZYCNmIAh02T+4WRey1mesFZg3SmDuZv/TW/CVtDHEnQ9Wb2oiqoo?= =?us-ascii?Q?3gH8qPdxzdrBoIPk+cd2ZHIYzGUJkJc1mfaL45LLoUoiZa15cBX6AMTpHMgm?= =?us-ascii?Q?E9h8+i7BuCErjRqfpWRW7lOeDIOQMQNpXK0rEu0FqHIM+G/WoMUiNonsudOV?= =?us-ascii?Q?J6+6c24tn9g99DclsGfkNG4n6xAgLdYPN84+qtW6upjuOovfO8VICkV64vXI?= =?us-ascii?Q?o8nZ9ZnlkN2vmfpguNjif0uNzv1dsmGAK14bSOfvc/cd7z2RJBJTDrJkLIlO?= =?us-ascii?Q?zWPs22SOAJkDjk1a1wxgfk9KtOK2AHqrMxgN1Qfzz8OHhm9cunrFFzkS7d7K?= =?us-ascii?Q?RS4K0PUkroFHURSZc7oOOWDy1oqGu/bokMFRsRpU21BWPgwCh0+2bDLqdVRq?= =?us-ascii?Q?CENI/Za2n4OO0jBrAAmQnt0hHCe6Txwy1+eqLFHCulTprT78ai9q3B+Qa72T?= =?us-ascii?Q?YH/488XHjQ/VhVjek83G8OOAG4uRItk7kp6BFrB+bjNGconDfqpdJWD1718w?= =?us-ascii?Q?Z1Ce/Hn5i65rfGICkI0y105deF4c3TBqxmK8tbEJDhBvRAX0PCdUebxJvyqz?= =?us-ascii?Q?CpepZQC4unuT4e0pxZxCpQVSE42Mu8izGn5v0dhoEOgGfW0WYWdMoeQrPRXp?= =?us-ascii?Q?TMIwPsfdK1j4Wk+Ty6sllQZD3aCNe0IWB3hUCfacak0Kle2tiTNmoEFCzP9b?= =?us-ascii?Q?c+B471uRSCgg4sPJ+PhwRYkahtvccTH3ACNbOUAhFFsm9nAccl32f0mTroK/?= =?us-ascii?Q?jKxkPXI03yZEcGM/IjjQmVb2PpCp+UEiES56y0LxiNKgwKf41PRSTxMxCJ/i?= =?us-ascii?Q?j07x8JPS8uiF9+BhTv1kOj8IsRiVFLxyXnYr?= X-Forefront-Antispam-Report: CIP:165.204.84.17; CTRY:US; LANG:en; SCL:1; SRV:; IPV:CAL; SFV:NSPM; H:SATLEXMB03.amd.com; PTR:InfoDomainNonexistent; CAT:NONE; SFS:(13230040)(82310400026)(36860700013)(376014)(1800799024); DIR:OUT; SFP:1101; X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Aug 2025 08:27:26.0988 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: f51d0115-70d4-451a-f7e5-08dddfc364fb X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXMB03.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CO1PEPF000075F0.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: PH8PR12MB7027 Received-SPF: permerror client-ip=2a01:111:f403:2417::62d; envelope-from=Luc.Michel@amd.com; helo=NAM12-DM6-obe.outbound.protection.outlook.com X-Spam_score_int: -10 X-Spam_score: -1.1 X-Spam_bar: - X-Spam_report: (-1.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FORGED_SPF_HELO=1, SPF_HELO_PASS=-0.001, T_SPF_TEMPERROR=0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @amd.com) X-ZM-MESSAGEID: 1755678601243116600 Content-Type: text/plain; charset="utf-8" Add support for the ARM Cortex-A78AE CPU. Signed-off-by: Luc Michel --- target/arm/tcg/cpu64.c | 79 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 79 insertions(+) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 35cddbafa4c..b56677c1a5d 100644 --- a/target/arm/tcg/cpu64.c +++ b/target/arm/tcg/cpu64.c @@ -404,10 +404,84 @@ static void aarch64_a76_initfn(Object *obj) =20 /* From D5.1 AArch64 PMU register summary */ cpu->isar.reset_pmcr_el0 =3D 0x410b3000; } =20 +static void aarch64_a78ae_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + ARMISARegisters *isar =3D &cpu->isar; + + cpu->dtb_compatible =3D "arm,cortex-a78ae"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_BACKCOMPAT_CNTFRQ); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + SET_IDREG(isar, CLIDR, 0x82000023); + cpu->ctr =3D 0x9444c004; + cpu->dcz_blocksize =3D 4; + SET_IDREG(isar, ID_AA64DFR0, 0x0000000110305408ull); + SET_IDREG(isar, ID_AA64ISAR0, 0x0010100010211120ull); + SET_IDREG(isar, ID_AA64ISAR1, 0x0000000001200031ull); + SET_IDREG(isar, ID_AA64MMFR0, 0x0000000000101125ull); + SET_IDREG(isar, ID_AA64MMFR1, 0x0000000010212122ull); + SET_IDREG(isar, ID_AA64MMFR2, 0x0000000100001011ull); + SET_IDREG(isar, ID_AA64PFR0, 0x1100000010111112ull); /* GIC filled in = later */ + SET_IDREG(isar, ID_AA64PFR1, 0x0000000000000010ull); + SET_IDREG(isar, ID_AFR0, 0x00000000); + SET_IDREG(isar, ID_DFR0, 0x04010088); + SET_IDREG(isar, ID_ISAR0, 0x02101110); + SET_IDREG(isar, ID_ISAR1, 0x13112111); + SET_IDREG(isar, ID_ISAR2, 0x21232042); + SET_IDREG(isar, ID_ISAR3, 0x01112131); + SET_IDREG(isar, ID_ISAR4, 0x00010142); + SET_IDREG(isar, ID_ISAR5, 0x01011121); + SET_IDREG(isar, ID_ISAR6, 0x00000010); + SET_IDREG(isar, ID_MMFR0, 0x10201105); + SET_IDREG(isar, ID_MMFR1, 0x40000000); + SET_IDREG(isar, ID_MMFR2, 0x01260000); + SET_IDREG(isar, ID_MMFR3, 0x02122211); + SET_IDREG(isar, ID_MMFR4, 0x00021110); + SET_IDREG(isar, ID_PFR0, 0x10010131); + SET_IDREG(isar, ID_PFR1, 0x00010000); /* GIC filled in later */ + SET_IDREG(isar, ID_PFR2, 0x00000011); + cpu->midr =3D 0x410fd421; /* r0p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + /* 64KB L1 dcache */ + cpu->ccsidr[0] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 7); + /* 64KB L1 icache */ + cpu->ccsidr[1] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 4, 64, 64 * KiB, = 2); + /* 512KB L2 cache */ + cpu->ccsidr[2] =3D make_ccsidr(CCSIDR_FORMAT_LEGACY, 8, 64, 512 * KiB,= 7); + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; + + /* From D5.1 AArch64 PMU register summary */ + cpu->isar.reset_pmcr_el0 =3D 0x41223000; +} + static void aarch64_a64fx_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); ARMISARegisters *isar =3D &cpu->isar; =20 @@ -1313,10 +1387,15 @@ void aarch64_max_tcg_initfn(Object *obj) static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a35", .initfn =3D aarch64_a35_initfn }, { .name =3D "cortex-a55", .initfn =3D aarch64_a55_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, + /* + * The Cortex-A78AE differs slightly from the plain Cortex-A78. We don= 't + * currently model the latter. + */ + { .name =3D "cortex-a78ae", .initfn =3D aarch64_a78ae_initfn }, { .name =3D "cortex-a710", .initfn =3D aarch64_a710_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "neoverse-v1", .initfn =3D aarch64_neoverse_v1_init= fn }, { .name =3D "neoverse-n2", .initfn =3D aarch64_neoverse_n2_init= fn }, --=20 2.50.1