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Fri, 15 Aug 2025 05:27:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 6/7] target/arm: Implement FEAT_LSE128 Date: Fri, 15 Aug 2025 22:26:52 +1000 Message-ID: <20250815122653.701782-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250815122653.701782-1-richard.henderson@linaro.org> References: <20250815122653.701782-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1755260944778116600 Content-Type: text/plain; charset="utf-8" This feature contains the LDCLRP, LDSETP, and SWPP instructions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu-features.h | 5 ++++ target/arm/tcg/translate-a64.c | 49 ++++++++++++++++++++++++++++++++++ target/arm/tcg/a64.decode | 7 +++++ 3 files changed, 61 insertions(+) diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h index e3d4c3d382..182b301c86 100644 --- a/target/arm/cpu-features.h +++ b/target/arm/cpu-features.h @@ -411,6 +411,11 @@ static inline bool isar_feature_aa64_lse(const ARMISAR= egisters *id) return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) !=3D 0; } =20 +static inline bool isar_feature_aa64_lse128(const ARMISARegisters *id) +{ + return FIELD_EX64_IDREG(id, ID_AA64ISAR0, ATOMIC) >=3D 3; +} + static inline bool isar_feature_aa64_rdm(const ARMISARegisters *id) { return FIELD_EX64_IDREG(id, ID_AA64ISAR0, RDM) !=3D 0; diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c index d0639e29cf..976bf4df32 100644 --- a/target/arm/tcg/translate-a64.c +++ b/target/arm/tcg/translate-a64.c @@ -3753,6 +3753,55 @@ TRANS_FEAT(LDUMAX, aa64_lse, do_atomic_ld, a, tcg_ge= n_atomic_fetch_umax_i64, 0, TRANS_FEAT(LDUMIN, aa64_lse, do_atomic_ld, a, tcg_gen_atomic_fetch_umin_i6= 4, 0, false) TRANS_FEAT(SWP, aa64_lse, do_atomic_ld, a, tcg_gen_atomic_xchg_i64, 0, fal= se) =20 +typedef void Atomic128ThreeOpFn(TCGv_i128, TCGv_i64, TCGv_i128, TCGArg, Me= mOp); + +static bool do_atomic128_ld(DisasContext *s, arg_atomic128 *a, + Atomic128ThreeOpFn *fn, bool invert) +{ + MemOp mop; + int rlo, rhi; + TCGv_i64 clean_addr, tlo, thi; + TCGv_i128 t16; + + if (a->rt =3D=3D 31 || a->rt2 =3D=3D 31 || a->rt =3D=3D a->rt2) { + return false; + } + if (a->rn =3D=3D 31) { + gen_check_sp_alignment(s); + } + mop =3D check_atomic_align(s, a->rn, MO_128); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, a->rn), false, + a->rn !=3D 31, mop); + + rlo =3D (s->be_data =3D=3D MO_LE ? a->rt : a->rt2); + rhi =3D (s->be_data =3D=3D MO_LE ? a->rt2 : a->rt); + + tlo =3D read_cpu_reg(s, rlo, true); + thi =3D read_cpu_reg(s, rhi, true); + if (invert) { + tcg_gen_not_i64(tlo, tlo); + tcg_gen_not_i64(thi, thi); + } + /* + * The tcg atomic primitives are all full barriers. Therefore we + * can ignore the Acquire and Release bits of this instruction. + */ + t16 =3D tcg_temp_new_i128(); + tcg_gen_concat_i64_i128(t16, tlo, thi); + + fn(t16, clean_addr, t16, get_mem_index(s), mop); + + tcg_gen_extr_i128_i64(cpu_reg(s, rlo), cpu_reg(s, rhi), t16); + return true; +} + +TRANS_FEAT(LDCLRP, aa64_lse128, do_atomic128_ld, + a, tcg_gen_atomic_fetch_and_i128, true) +TRANS_FEAT(LDSETP, aa64_lse128, do_atomic128_ld, + a, tcg_gen_atomic_fetch_or_i128, false) +TRANS_FEAT(SWPP, aa64_lse128, do_atomic128_ld, + a, tcg_gen_atomic_xchg_i128, false) + static bool trans_LDAPR(DisasContext *s, arg_LDAPR *a) { bool iss_sf =3D ldst_iss_sf(a->sz, false, false); diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode index 8c798cde2b..70ed9610af 100644 --- a/target/arm/tcg/a64.decode +++ b/target/arm/tcg/a64.decode @@ -536,6 +536,13 @@ SWP .. 111 0 00 . . 1 ..... 1000 00 ..... = ..... @atomic =20 LDAPR sz:2 111 0 00 1 0 1 11111 1100 00 rn:5 rt:5 =20 +# Atomic 128-bit memory operations +&atomic128 rn rt rt2 a r +@atomic128 ........ a:1 r:1 . rt2:5 ...... rn:5 rt:5 &atomic128 +LDCLRP 00011001 . . 1 ..... 000100 ..... ..... @atomic128 +LDSETP 00011001 . . 1 ..... 001100 ..... ..... @atomic128 +SWPP 00011001 . . 1 ..... 100000 ..... ..... @atomic128 + # Load/store register (pointer authentication) =20 # LDRA immediate is 10 bits signed and scaled, but the bits aren't all con= tiguous --=20 2.43.0