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Thu, 14 Aug 2025 06:08:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Pierrick Bouvier Subject: [PATCH v3 83/85] tests/tcg/aarch64: Add gcsstr Date: Thu, 14 Aug 2025 22:57:50 +1000 Message-ID: <20250814125752.164107-84-richard.henderson@linaro.org> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250814125752.164107-1-richard.henderson@linaro.org> References: <20250814125752.164107-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: qemu-devel-bounces+importer=patchew.org@nongnu.org X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1755177918720116600 Content-Type: text/plain; charset="utf-8" Add some infrastructure for testing gcs in userspace. Validate successful and trapped executions of GCSSTR. Reviewed-by: Pierrick Bouvier Signed-off-by: Richard Henderson --- tests/tcg/aarch64/gcs.h | 71 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/gcsstr.c | 48 +++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 5 +++ 3 files changed, 124 insertions(+) create mode 100644 tests/tcg/aarch64/gcs.h create mode 100644 tests/tcg/aarch64/gcsstr.c diff --git a/tests/tcg/aarch64/gcs.h b/tests/tcg/aarch64/gcs.h new file mode 100644 index 0000000000..99cb4d4e38 --- /dev/null +++ b/tests/tcg/aarch64/gcs.h @@ -0,0 +1,71 @@ +/* + * Linux kernel fallback API definitions for GCS and test helpers. + * + * Copyright (c) 2025 Linaro Ltd + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#ifndef PR_GET_SHADOW_STACK_STATUS +#define PR_GET_SHADOW_STACK_STATUS 74 +#endif +#ifndef PR_SET_SHADOW_STACK_STATUS +#define PR_SET_SHADOW_STACK_STATUS 75 +#endif +#ifndef PR_LOCK_SHADOW_STACK_STATUS +#define PR_LOCK_SHADOW_STACK_STATUS 76 +#endif +#ifndef PR_SHADOW_STACK_ENABLE +# define PR_SHADOW_STACK_ENABLE (1 << 0) +# define PR_SHADOW_STACK_WRITE (1 << 1) +# define PR_SHADOW_STACK_PUSH (1 << 2) +#endif +#ifndef SHADOW_STACK_SET_TOKEN +#define SHADOW_STACK_SET_TOKEN (1 << 0) +#endif +#ifndef SHADOW_STACK_SET_MARKER +#define SHADOW_STACK_SET_MARKER (1 << 1) +#endif +#ifndef SEGV_CPERR +#define SEGV_CPERR 10 +#endif +#ifndef __NR_map_shadow_stack +#define __NR_map_shadow_stack 453 +#endif + +/* + * Macros, and implement the syscall inline, lest we fail + * the checked return from any function call. + */ +#define enable_gcs(flags) \ + do { = \ + register long num __asm__ ("x8") =3D __NR_prctl; = \ + register long arg1 __asm__ ("x0") =3D PR_SET_SHADOW_STACK_STATUS; = \ + register long arg2 __asm__ ("x1") =3D PR_SHADOW_STACK_ENABLE | fla= gs; \ + register long arg3 __asm__ ("x2") =3D 0; = \ + register long arg4 __asm__ ("x3") =3D 0; = \ + register long arg5 __asm__ ("x4") =3D 0; = \ + asm volatile("svc #0" = \ + : "+r"(arg1) = \ + : "r"(arg2), "r"(arg3), "r"(arg4), "r"(arg5), "r"(num= ) \ + : "memory", "cc"); = \ + if (arg1) { = \ + errno =3D -arg1; = \ + perror("PR_SET_SHADOW_STACK_STATUS"); = \ + exit(2); = \ + } = \ + } while (0) + +#define gcspr() \ + ({ uint64_t *r; asm volatile("mrs %0, s3_3_c2_c5_1" : "=3Dr"(r)); r; }) diff --git a/tests/tcg/aarch64/gcsstr.c b/tests/tcg/aarch64/gcsstr.c new file mode 100644 index 0000000000..b045aee925 --- /dev/null +++ b/tests/tcg/aarch64/gcsstr.c @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "gcs.h" + +/* + * A single garbage store to the gcs stack. + * The asm inside must be unique, so disallow inlining. + */ +void __attribute__((noinline)) +test_gcsstr(void) +{ + register uint64_t *ptr __asm__("x0") =3D gcspr(); + /* GCSSTR x1, x0 */ + __asm__("inst_gcsstr: .inst 0xd91f1c01" : : "r"(--ptr)); +} + +static void test_sigsegv(int sig, siginfo_t *info, void *vuc) +{ + ucontext_t *uc =3D vuc; + uint64_t inst_gcsstr; + + __asm__("adr %0, inst_gcsstr" : "=3Dr"(inst_gcsstr)); + assert(uc->uc_mcontext.pc =3D=3D inst_gcsstr); + assert(info->si_code =3D=3D SEGV_CPERR); + /* TODO: Dig for ESR and verify syndrome. */ + exit(0); +} + +int main() +{ + struct sigaction sa =3D { + .sa_sigaction =3D test_sigsegv, + .sa_flags =3D SA_SIGINFO, + }; + + /* Enable GCSSTR and test the store succeeds. */ + enable_gcs(PR_SHADOW_STACK_WRITE); + test_gcsstr(); + + /* Disable GCSSTR and test the resulting sigsegv. */ + enable_gcs(0); + if (sigaction(SIGSEGV, &sa, NULL) < 0) { + perror("sigaction"); + exit(1); + } + test_gcsstr(); + abort(); +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 16ddcf4f88..0347a36e8d 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -75,6 +75,11 @@ AARCH64_TESTS +=3D $(SME_TESTS) $(SME_TESTS): CFLAGS +=3D $(CROSS_AS_HAS_ARMV9_SME) endif =20 +# GCS Tests +GCS_TESTS +=3D gcsstr +AARCH64_TESTS +=3D $(GCS_TESTS) +$(GCS_TESTS): gcs.h + # System Registers Tests AARCH64_TESTS +=3D sysregs =20 --=20 2.43.0